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产品型号CDC536DBR的概述

芯片 CDC536DBR 概述 CDC536DBR 是一款集成电路（IC），属于时钟生成和时钟信号处理器的类型。此芯片主要用于在电子系统中提供高精度和高稳定性的时钟信号，广泛应用于通信、计算机、消费电子和工业自动化等领域。其设计目的是为了满足高速数字电路对时钟信号特性的高要求，具有低抖动、低功耗和高性能等优点。芯片详细参数 CDC536DBR 的关键参数包括： - 工作电压：提供多种工作电压选项，通常在 3.3V 到 5V 之间，具体使用时需参考数据手册。 - 输入频率范围：支持从几 MHz 到数百 MHz 的输入频率，适应不同的应用需求。 - 输出频率：可根据不同的配置信息输出多种频率，适合系统对时钟频率的严格要求。 - 功耗：此芯片具有较低的功耗特性，一般在几百毫瓦的范围内，适合于低功耗设计。 - 相位噪声：相位噪声低于 -110dBc/Hz，确保时钟信号的稳定性和精确性。 - ...

产品型号CDC536DBR的Datasheet PDF文件预览

CDC536

www.ti.com

SCAS378G–APRIL 1994–REVISED JULY 2004

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES

DB OR DL PACKAGE

(TOP VIEW)

•

Low-Output Skew for Clock-Distribution and

Clock-Generation Applications

•

Operates at 3.3-V V_CC

AGND

CLKIN

SEL

GND

1Y1

AGND

Distributes One Clock Input to Six Outputs

26 FBIN

One Select Input Configures Three Outputs to

Operate at One-Half or Double the Input

Frequency

TEST

CLR

•

No External RC Network Required

2Y1

External Feedback Pin (FBIN) Is Used to

Synchronize the Outputs to the Clock Input

21 GND

19 2Y2

GND

1Y2 10

•

Application for Synchronous DRAM,

High-Speed Microprocessor

GND

1Y3

Negative-Edge-Triggered Clear for

Half-Frequency Outputs

2Y3

15 GND

•

TTL-Compatible Inputs and Outputs

Outputs Drive 50-Ω Parallel-Terminated

Transmission Lines

•

State-of-the-Art EPIC-IIB™ BiCMOS Design

Significantly Reduces Power Dissipation

Distributed V_CCand Ground Pins Reduce

Switching Noise

Packaged in Plastic 28-Pin Shrink Small

Outline Package

DESCRIPTION

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely

align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically

designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to

100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V

V_CCand is designed to drive a 50-W transmission line.

The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock

(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between

CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input

configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed

back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty

cycle at the input clock.

Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.

When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass

the PLL. TEST should be strapped to GND for normal operation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-IIB is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDC536

www.ti.com

SCAS378G–APRIL 1994–REVISED JULY 2004

Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for

the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application of a

fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback

signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of

all outputs via OE.

The CDC536 is characterized for operation from 0°C to 70°C.

DETAILED DESCRIPTION OF OUTPUT CONFIGURATIONS

The voltage-controlled oscillator (VCO) in the CDC536 has a frequency range of 100 MHz to 200 MHz, twice the

operating frequency range of the CDC536 outputs. The output of the VCO is divided by two and by four to

provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The SEL0

and SEL1 inputs determine which of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the

frequency of this output matches that of the CLKIN signals. In the case that a VCO/2 output is wired to FBIN, the

VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at the same or one-half

the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or twice the

CLKIN frequency.

Output Configuration A

Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to the

FBIN input. The input frequency range for the CLKIN input is 50 MHz to 100 MHz when using output

configuration A. Outputs configured as 1/2× outputs operate at half the CLKIN frequency, while outputs

configured as 1× outputs operate at the same frequency as the CLKIN input.

Table 1. Output Configuration A

INPUTS

SEL

OUTPUTS

1/2×

FREQUENCY

1×

FREQUENCY

None

1Yn

All

2Yn

Output Configuration B

Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to

FBIN. The input frequency range for the CLKIN input is 25 MHz to 50 MHz when using output configuration B.

Outputs configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs

operate at double the frequency of the CLKIN input.

Table 2. Output Configuration B

INPUTS

SEL

OUTPUTS

1×

2×

FREQUENCY

All

None

2Yn

1Yn

CDC536

www.ti.com

SCAS378G–APRIL 1994–REVISED JULY 2004

FUNCTIONAL BLOCK DIAGRAM

CLR

FBIN

Phase-Lock Loop

CLKIN

TEST

SEL

1Y1

1Y2

1Y3

2Y1

2Y2

2Y3

CDC536

www.ti.com

SCAS378G–APRIL 1994–REVISED JULY 2004

FUNCTIONAL BLOCK DIAGRAM (continued)

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Clock input. CLKIN provides the clock signal to be distributed by the CDC536 clock-driver circuit. CLKIN is

used to provide the reference signal to the integrated phase-lock loop that generates the clock output

signals. CLKIN must have a fixed frequency and fixed phase in order for the phase-lock loop to obtain

phase lock. Once the circuit is powered up and a valid CLKIN signal is applied, a stabilization time is

required for the phase-lock loop to phase lock the feedback signal to its reference signal.

CLKIN

CLR

CLR is used for testing purposes only. Connect CLR to GND for normal operation.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of

the six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to

obtain zero phase delay between the FBIN and differential CLKIN inputs.

FBIN

Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE

is high, all outputs are in the high-impedance state. Since the feedback signal for the phase-lock loop is

taken directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop;

therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is

required before the phase-lock loop obtains phase lock.

Output configuration select. SEL selects the output configuration for each output bank (e.g. 1×, 1/2×, or

2×).(see Tables 1 and 2).

SEL

TEST is used to bypass the phase-lock loop circuitry for factory testing of the device. When TEST is low,

all outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that

bypasses the PLL circuitry. TEST should be grounded for normal operation.

TEST

These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The

relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle

of the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal.

1Y1-1Y3

7, 10, 13

These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency

and the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty

cycle of the Y output signals is nominally 50% independent of the duty cycle of the CLKIN signal.

2Y1-2Y3 22, 19, 16

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

-0.5 V to 4.6 V

-0.5 V to 7 V

-0.5 V to 5.5 V

64 mA

Supply voltage range, V_CC

(2)

Input voltage range, V_I(see

)

(2)

Voltage range applied to any output in the high state or power-off state, V_O(see

Current into any output in the low state, I_O

Input clamp current, I_IK(V_I< 0)

)

-20 mA

Output clamp current, I_OK(V_O< 0)

-50 mA

Maximum power dissipation at T_A= 55°C (in still air) (see ⁽³⁾):

DB package

DL package

0.68 W

0.7 W

Operating free-air temperature range, T_A

Storage temperature range, T_stg

0°C to 70°C

-65°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils. For

more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book,

literature number SCBD002.

CDC536

www.ti.com

SCAS378G–APRIL 1994–REVISED JULY 2004

(1)

RECOMMENDED OPERATING CONDITIONS (SEE

)

MIN

MAX UNIT

V_CC

V_IH

V_IL

V_I

Supply voltage

3.6

High-level input voltage

Low-level input voltage

Input voltage

0.8

5.5

I_OH

I_OL

T_A

High-level output current

Low-level output current

Operating free-air temperature

°C

(1) Unused inputs must be held high or low.

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

T_A= 25°C

PARAMETER

TEST CONDITIONS

I_I= -18 mA

UNIT

MIN MAX

V_IK

V_CC= 3 V,

1.2

V_CC= MIN to MAX⁽¹⁾

V_CC= 3 V,

I_OH= -100 µA

I_OH= -32 mA

I_OL= 100 µA

I_OL= 32 mA

V_I= 3.6 V

V_CC-0.2

V_OH

V_CC= 3 V,

0.2

0.5

±10

±1

V_OL

V_CC= 3 V,

V_CC= 0 or MAX⁽¹⁾

I_I

µA

V_CC= 3.6 V,

V_I= V_CCor GND

V_O= 3 V

I_OZH

I_OZL

V_CC= 3.6 V,

µA

V_CC= 3.6 V,

V_O= 0

Outputs high

Outputs low

I_CC

V_CC= 3.6 V, I_O= 0, V_I= V_CCor GND

Outputs disabled

C_i

V_I= V_CCor GND

V_O= V_CCor GND

C_o

(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

TIMING REQUIREMENTS

over recommended ranges of supply voltage and operating free-air temperature

MIN

MAX UNIT

When VCO is operating at four times the CLKIN frequency

When VCO is operating at double the CLKIN frequency

MHz

100

f_clock

Clock frequency

Input clock duty cycle

40%

60%

After SEL

After OE↓

µs

Stabilization time⁽¹⁾

After power up

After CLKIN

(1) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to

be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications

for propagation delay and skew parameters given in the switching characteristics table are not applicable.

CDC536

www.ti.com

SCAS378G–APRIL 1994–REVISED JULY 2004

SWITCHING CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature, C_L= 30 pF (see ⁽¹⁾and Figure 1 and

Figure 2)

FROM

(INPUT)

(OUTPUT)

PARAMETER

MIN

MAX UNIT

f_max

Duty cycle

100

45%

500

MHz

55%

(2)

t_{phase error}

CLKIN↑

+500

200

0.5

Jitter_(pk-pk)

(2)

t_sk(o)

t_sk(pr)

t_r

t_f

1.4

(1) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

(2) The propagation delay, t_{phase error}, is dependent on the feedback path from any output to FBIN. The t_{phase error}, t_sk(o), and t_sk(pk)

specifications are only valid for equal loading of all outputs.

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

Input

1.5 V

phase error

From Output

Under Test

2 V

0.8 V

2 V

Output

500 W

1.5 V

0.8 V

= 30 pF

(see note A)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

LOAD CIRCUIT FOR OUTPUTS

A. NOTES: . C_Lincludes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR≤ 100 MHz, Z_O= 50 Ω, t_r≤ 2.5 ns,

t_f≤ 2.5 ns.

C. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

CDC536

www.ti.com

SCAS378G–APRIL 1994–REVISED JULY 2004

PARAMETER MEASUREMENT INFORMATION (continued)

CLKIN

phase error 1

Outputs

Operating

at 1/2 CLKIN

Frequency

phase error 2

phase error 3

phase error 4

phase error 7

Outputs

Operating

at CLKIN

phase error 5

phase error 8

Frequency

phase error 9

phase error 6

A. NOTES: . Output skew, t_sk(o), is calculated as the greater of:

•

The difference between the fastest and slowest of t_{phase error n}(n = 1, 2, . . . 6)

The difference between the fastest and slowest of t_{phase error n}(n = 7, 8, 9)

B. Process skew, t_sk(pr), is calculated as the greater of:

•

The difference between the maximum and minimum t_{phase error n}(n = 1, 2, . . . 6) across multiple devices under

identical operating conditions.

•

The difference between the maximum and minimum t_phase

identical operating conditions.

(n = 7, 8, 9) across multiple devices under

error

Figure 2. Skew Waveforms and Calculations

CDC536

www.ti.com

SCAS378G–APRIL 1994–REVISED JULY 2004

PARAMETER MEASUREMENT INFORMATION (continued)

CLKIN

phase error 10

Outputs

Operating

at CLKIN

phase error 11

Frequency

phase error 12

phase error 13

Outputs

Operating

at 2× CLKIN

Frequency

phase error 14

phase error 15

A. NOTES: . Output skew, t_sk(o), is calculated as the greater of:

The difference between the fastest and slowest of t_{phase error n}(n = 10, 11, . . . 15)

B. Process skew, t_sk(pr), is calculated as the greater of:

•

The difference between the maximum and minimum t_phase

under identical operating conditions.

(n = 10, 11, . . . 15) across multiple devices

error

Figure 3. Waveforms for Calculation of t_sk(o)and t_sk(pr)

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2006

PACKAGING INFORMATION

Orderable Device

CDC536DB

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CDC536DBG4

CDC536DBR

SSOP

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CDC536DBRG4

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CDC536DL

OBSOLETE

SSOP

TBD

Call TI

CDC536DLR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

CDC536DBR

SSOP

2000

330.0

16.4

8.1

10.4

2.5

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SSOP DB 28

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 33.0

CDC536DBR

2000

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

0.0135 (0,343)

0.008 (0,203)

0.005 (0,13)

0.010 (0,25)

0.005 (0,13)

0.299 (7,59)

0.291 (7,39)

0.420 (10,67)

0.395 (10,03)

Gage Plane

0.010 (0,25)

0°–ā8°

0.040 (1,02)

0.020 (0,51)

Seating Plane

0.004 (0,10)

0.008 (0,20) MIN

PINS **

0.110 (2,79) MAX

0.630

DIM

0.380

(9,65)

0.730

A MAX

A MIN

(16,00) (18,54)

0.370

(9,40)

0.620

0.720

(15,75) (18,29)

4040048/E 12/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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CDC536DBR产品参数

型号:	CDC536DBR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SSOP
包装说明：	SSOP, SSOP28,.3
针数：	28
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
风险等级：	1.6
Is Samacsys：	N
系列：	536
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e4
长度：	10.2 mm
负载电容（CL）：	30 pF
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.032 A
湿度敏感等级：	1
功能数量：	1
反相输出次数：
端子数量：	28
实输出次数：	6
最高工作温度：	70 °C
最低工作温度：
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP28,.3
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.5 ns
座面最大高度：	2 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	BICMOS
温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.3 mm
最小 fmax：	100 MHz
Base Number Matches：	1

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