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  • CDCE913PWR图
  • 深圳市欧昇科技有限公司

     该会员已使用本站10年以上
  • CDCE913PWR 现货库存
  • 数量9000 
  • 厂家TI 
  • 封装TSSOP-14 
  • 批号2021+ 
  • 假一罚十原装现货
  • QQ:2885514621QQ:2885514621 复制
    QQ:1017582752QQ:1017582752 复制
  • 0755-83237676 QQ:2885514621QQ:1017582752
  • CDCE913PWR图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • CDCE913PWR 现货库存
  • 数量13500 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495
  • CDCE913PWR图
  • 集好芯城

     该会员已使用本站13年以上
  • CDCE913PWR 现货库存
  • 数量17636 
  • 厂家TI(德州仪器) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • CDCE913PWR图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • CDCE913PWR 现货库存
  • 数量5300 
  • 厂家TI/德州仪器? 
  • 封装TSSOP14 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
  • QQ:2353549508QQ:2353549508 复制
    QQ:2885134615QQ:2885134615 复制
  • 0755-83201583 QQ:2353549508QQ:2885134615
  • CDCE913PWR图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • CDCE913PWR 现货库存
  • 数量4785 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号23+ 
  • 原装现货,实货实报
  • QQ:892152356QQ:892152356 复制
  • 0755-82777852 QQ:892152356
  • CDCE913PWR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • CDCE913PWR 现货库存
  • 数量5000 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号23+ 
  • 全新原装,欢迎查询
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • CDCE913PWR图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • CDCE913PWR 现货库存
  • 数量64800 
  • 厂家TI 
  • 封装新批号 
  • 批号TSSOP-14 
  • 只做原装,假一罚十,实单好谈
  • QQ:1134344845QQ:1134344845 复制
    QQ:847984313QQ:847984313 复制
  • 86-0755-83536093 QQ:1134344845QQ:847984313
  • CDCE913PWR图
  • 深圳市创德丰电子有限公司

     该会员已使用本站15年以上
  • CDCE913PWR 现货库存
  • 数量305 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号2239+ 
  • 一定原装房间现货
  • QQ:2851807192QQ:2851807192 复制
    QQ:2851807191QQ:2851807191 复制
  • 86-755-83226910, QQ:2851807192QQ:2851807191
  • CDCE913PWR图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • CDCE913PWR 现货库存
  • 数量23200 
  • 厂家TI 
  • 封装N/A 
  • 批号21+ 
  • 全新原装有现货库存--价格有优势
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • CDCE913PWR图
  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • CDCE913PWR 现货库存
  • 数量650 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号20+ 
  • 受权代理!全新原装现货特价热卖!
  • QQ:1258645397QQ:1258645397 复制
    QQ:876098337QQ:876098337 复制
  • 0755-83238902 QQ:1258645397QQ:876098337
  • CDCE913PWR图
  • 深圳市楷兴电子科技有限公司

     该会员已使用本站7年以上
  • CDCE913PWR 现货库存
  • 数量89700 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号21+ 
  • 全新进口原装现货,代理渠道假一赔十
  • QQ:2881475151QQ:2881475151 复制
  • 0755-83016042 QQ:2881475151
  • CDCE913PWR图
  • 深圳市欧昇科技有限公司

     该会员已使用本站2年以上
  • CDCE913PWR 现货库存
  • 数量
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号1444+ 
  • 全新原装现货低低价出
  • QQ:2885528234QQ:2885528234 复制
  • -0755-83220848 QQ:2885528234
  • CDCE913PW图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • CDCE913PW 现货库存
  • 数量90 
  • 厂家TI 
  • 封装TSSOP (PW) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • CDCE913PW图
  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
  • CDCE913PW 现货库存
  • 数量18500 
  • 厂家TI(德州仪器) 
  • 封装TSSOP-14 
  • 批号23+ 
  • ★★全网低价,原装原包★★
  • QQ:1483430049QQ:1483430049 复制
  • 0755-83235525 QQ:1483430049
  • CDCE913PWR图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • CDCE913PWR 现货库存
  • 数量20550 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号21+ 
  • ■正纳电子专业元器件代理
  • QQ:2881664480QQ:2881664480 复制
  • 0755-83532193 QQ:2881664480
  • CDCE913PW图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • CDCE913PW
  • 数量5300 
  • 厂家TI(德州仪器) 
  • 封装TSSOP-14 
  • 批号21+ 
  • 全新原装正品,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • CDCE913PW图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CDCE913PW
  • 数量10718 
  • 厂家TI(德州仪器) 
  • 封装TSSOP14 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • CDCE913PW图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • CDCE913PW
  • 数量8800 
  • 厂家TI 
  • 封装TSSOP16 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
  • QQ:3533288158QQ:3533288158 复制
    QQ:408391813QQ:408391813 复制
  • 0755-84876394 QQ:3533288158QQ:408391813
  • CDCE913PW图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • CDCE913PW
  • 数量5166 
  • 厂家TI 
  • 封装SSOP16 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:221698708QQ:221698708 复制
  • 0755-83222787 QQ:1950791264QQ:221698708
  • CDCE913PW图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • CDCE913PW
  • 数量5600 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号23+ 
  • 100%深圳原装现货库存
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • CDCE913PWR图
  • 集好芯城

     该会员已使用本站13年以上
  • CDCE913PWR
  • 数量18305 
  • 厂家TI/德州仪器 
  • 封装TSSOP 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • CDCE913PWR图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • CDCE913PWR
  • 数量8800 
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号新年份 
  • 羿芯诚只做原装,原厂渠道,价格优势可谈!
  • QQ:2853992132QQ:2853992132 复制
  • 0755-82570683 QQ:2853992132
  • CDCE913PWR图
  • 深圳市芯达科技有限公司

     该会员已使用本站9年以上
  • CDCE913PWR
  • 数量25000 
  • 厂家TI 
  • 封装TSSOP-14 
  • 批号2018+ 
  • 一级专营品牌全新原装热卖
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • CDCE913PWR图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CDCE913PWR
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • CDCE913PW图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CDCE913PW
  • 数量24483 
  • 厂家TI 
  • 封装TSSOP 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • CDCE913PW图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • CDCE913PW
  • 数量25820 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号23+ 
  • 只做原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • CDCE913PW图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CDCE913PW
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装14-TSSOP 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • CDCE913PWR图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • CDCE913PWR
  • 数量5000 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号23+ 
  • 原装正品长期供货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • CDCE913PWR图
  • 深圳市英科美电子有限公司

     该会员已使用本站8年以上
  • CDCE913PWR
  • 数量13000 
  • 厂家TI原厂原装 
  • 封装TSSOP-14 
  • 批号21+ 
  • 原标原盘正品深圳现货
  • QQ:1106866800QQ:1106866800 复制
  • 0755-23903058 QQ:1106866800
  • CDCE913PW图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CDCE913PW
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装14-TSSOP 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • CDCE913PW图
  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
  • CDCE913PW
  • 数量6824 
  • 厂家TI 
  • 封装原厂封装 
  • 批号22+ 
  • 原装正品★真实库存★价格优势★欢迎来电洽谈
  • QQ:1686616797QQ:1686616797 复制
    QQ:2440138151QQ:2440138151 复制
  • 0755-22655674 QQ:1686616797QQ:2440138151
  • CDCE913PWR图
  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • CDCE913PWR
  • 数量12245 
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号22+ 
  • 现货,原厂原装假一罚十!
  • QQ:2885659458QQ:2885659458 复制
    QQ:2885657384QQ:2885657384 复制
  • 0755-83952260 QQ:2885659458QQ:2885657384
  • CDCE913PWR图
  • 深圳市积美福电子科技有限公司

     该会员已使用本站4年以上
  • CDCE913PWR
  • 数量8000 
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号21+ 
  • 自己原包装现货 实单?|原装?| 现货
  • QQ:647176908QQ:647176908 复制
    QQ:499959596QQ:499959596 复制
  • 0755-83228296 QQ:647176908QQ:499959596
  • CDCE913PW图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • CDCE913PW
  • 数量5000 
  • 厂家TI 
  • 封装 
  • 批号16+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62106431 QQ:857273081QQ:1594462451
  • CDCE913PW图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CDCE913PW
  • 数量339 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • CDCE913PW图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • CDCE913PW
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装14-TSSOP 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 96-010-62104931 QQ:2880824479QQ:1344056792
  • CDCE913PW图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • CDCE913PW
  • 数量98500 
  • 厂家MOLEX 
  • 封装 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • CDCE913PW图
  • 北京耐芯威科技有限公司

     该会员已使用本站13年以上
  • CDCE913PW
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装14-TSSOP 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 86-010-010-62104931 QQ:2880824479QQ:1344056792
  • CDCE913PW图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CDCE913PW
  • 数量12500 
  • 厂家TI 
  • 封装Original 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657

产品型号CDCE913PW的概述

CDCE913PW芯片概述 CDCE913PW是德州仪器公司(Texas Instruments, TI)推出的一款高性能时钟发生器。该芯片广泛应用于通信、消费电子、计算机及工业控制等领域。CDCE913PW通过其灵活的输出频率和低抖动特性,帮助设计人员解决时钟引导、时钟分配及时钟恢复等挑战。 详细参数 CDCE913PW的一些关键规格参数如下: 1. 输入频率范围:支持的输入频率范围为10MHz至200MHz,可以兼容多种时钟源。 2. 输出频率范围:单个输出可配置的频率范围广泛,高最高可达1GHz;多个输出频率均可通过内部PLL(相位锁定环路)生成。 3. 低抖动性能:该芯片的典型时钟输出抖动为0.4ps RMS,非常适合高端应用中的时钟要求,确保系统性能的可靠性。 4. 操作电压:工作电压范围为3.3V ± 5%,适用性强,且功耗低。 5. 输出配置:具有多达8个独立可编...

产品型号CDCE913PW的Datasheet PDF文件预览

CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs  
1
FEATURES  
Flexible Clock Driver  
2345  
Member of Programmable Clock Generator  
Family  
Three User-Definable Control Inputs  
[S0/S1/S2] e.g., SSC Selection,  
Frequency Switching, Output Enable or  
Power Down  
CDCE913/CDCEL913: 1-PLL, 3 Outputs  
CDCE925/CDCEL925: 2-PLL, 5 Outputs  
CDCE937/CDCEL937: 3-PLL, 7 Outputs  
CDCE949/CDCEL949: 4-PLL, 9 Outputs  
Programmable SSC Modulation  
Enables 0-PPM Clock Generation  
Generates Common Clock Frequencies  
Used With TI-DaVinci™, OMAP™, DSPs  
In-System Programmability and EEPROM  
Serial Programmable Volatile Register  
Generates Highly Accurate Clocks for  
Video, Audio, USB, IEEE1394, RFID,  
Bluetooth™, WLAN, Ethernet™, and  
GPS  
Nonvolatile EEPROM to Store Customer  
Setting  
Flexible Input Clocking Concept  
External Crystal: 8 MHz to 32 MHz  
On-Chip VCXO: Pull Range ±150 ppm  
Single-Ended LVCMOS up to 160 MHz  
1.8-V Device Power Supply  
Separate Output Supply Pins  
CDCE913: 3.3 V and 2.5 V  
CDCEL913: 1.8 V  
Free Selectable Output Frequency up to  
230 MHz  
Wide Temperature Range –40°C to 85°C  
Low-Noise PLL Core  
Packaged in TSSOP  
PLL Loop Filter Components Integrated  
Low Period Jitter (Typical 50 ps)  
Development and Programming Kit for Easy  
PLL Design and Programming (TI Pro-Clock™)  
APPLICATIONS  
D-TV, STB, IP-STB, DVD-Player, DVD-Recorder,  
Printer  
V
V
GND  
DD  
DDOUT  
V
ctr  
LV  
CMOS  
Y1  
Xin/CLK 1  
S0 2  
14 Xout  
VCXO  
XO  
13 S1/SDA  
12 S2/SCL  
11 Y1  
Divider  
and  
Output  
V
V
3
4
5
6
7
DD  
LV  
CMOS  
LVCMOS  
Y2  
Y3  
ctr  
PLL  
Control  
10 GND  
GND  
DDOUT  
DDOUT  
EEPROM  
Programming  
and  
Control Register  
with SSC  
V
V
3
9
8
Y2  
Y3  
LV  
CMOS  
S2/S1/S0 or  
SDA/SCL  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
4
5
DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments.  
Bluetooth is a trademark of Bluetooth SIG.  
I2C is a trademark of Philips Electronics.  
Ethernet is a trademark of Xerox Corporattion.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007, Texas Instruments Incorporated  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
DESCRIPTION  
The CDCE913 and CDCEL913 are modular PLL-based low-cost, high-performance, programmable clock  
synthesizers, multipliers, and dividers. They generate up to 3 output clocks from a single input frequency. Each  
output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated configurable  
PLL.  
The CDCx913 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to 3.3 V for  
CDCE913.  
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load  
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.  
Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external  
control signal, i.e. PWM signal.  
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth,  
Ethernet, GPS) or interface (USB, IEEE1394, Memory Stick) clocks from e.g., a 27-MHz reference input  
frequency.  
The PLL supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking which is  
a common technique to reduce electro-magnetic interference (EMI).  
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically  
adjusted to achieve high stability and optimized jitter transfer characteristic.  
The device supports non-volatile EEPROM programming for ease customization of the device to the application.  
It is preset to a factory default configuration (see the DEFAULT DEVICE CONFIGURATION section). It can be  
re-programmed to a different application configuration before PCB assembly, or re-programmed by in-system  
programming. All device settings are programmable through SDA/SCL bus, a 2-wire serial interface.  
Three programmable control inputs, S0, S1 and S2, can be used to select different frequencies, or change SSC  
setting for lowering EMI, or other control features like, outputs disable to low, outputs 3-state, power down, PLL  
bypass etc).  
The CDCx913 operates in a 1.8-V environment. It is characterized for operation from –40°C to 85°C  
Terminal Functions for CDCE913, CDCEL913  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
Y1–Y3  
PIN TSSOP14  
11, 9, 8  
O
LVCMOS outputs  
Xin/CLK  
Xout  
1
14  
4
I
Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus)  
Crystal oscillator output (leave open or pullup when not used)  
VCXO control voltage (leave open or pullup when not used)  
1.8-V power supply for the device  
O
I
VCtrl  
VDD  
3
Power  
CDCEL913: 1.8-V supply for all outputs  
VDDOUT  
6, 7  
Power  
CDCE913: 3.3-V or 2.5-V supply for all outputs  
GND  
S0  
5, 10  
2
Ground Ground  
User-programmable control input S0; LVCMOS inputs; internal pullup 500k  
SDA: bidirectional serial data input/output (default configuration), LVCMOS internal  
I/O or I pullup; or  
S1: user-programmable control input; LVCMOS inputs; internal pullup 500k  
I
SDA/S1  
SCL/S2  
13  
12  
SCL: serial clock input LVCMOS (default configuration), internal pullup 500k or  
S2: user-programmable control input; LVCMOS inputs; internal pullup 500k  
I
2
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Copyright © 2007, Texas Instruments Incorporated  
Product Folder Link(s): CDCE913 CDCEL913  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
V
GND  
V
DD  
DDOUT  
Input Clock  
V
ctr  
LV  
Pdiv1  
Y1  
CMOS  
10-Bit  
Xin/CLK  
VCXO  
XO  
LV  
CMOS  
Pdiv2  
7-Bit  
Y2  
Y3  
PLL 1  
LVCMOS  
with SSC  
Xout  
LV  
CMOS  
Pdiv3  
7-Bit  
PLL Bypass  
EEPROM  
Programming  
and  
S0  
S1/SDA  
S2/SCL  
SDA/SCL  
Register  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)(1)  
VALUE  
–0.5 to 2.5  
–0.5 to VDD + 0.5  
–0.5 to VDD + 0.5  
20  
UNIT  
V
VDD  
VI  
Supply voltage range  
Input voltage range(2)  
Output voltage range(2)  
Input current (VI < 0, VI > VDD  
Continuous output current  
Storage temperature range  
V
VO  
II  
V
)
mA  
mA  
°C  
°C  
IO  
50  
Tstg  
TJ  
–65 to 150  
125  
Maximum junction temperature  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
PACKAGE THERMAL RESISTANCE for TSSOP (PW) PACKAGE(1)(2)  
over operating free-air temperature range (unless otherwise noted)  
AIRFLOW  
(lfm)  
TSSOP14  
°C/W  
PARAMETER  
0
112  
105  
102  
97  
150  
250  
500  
TJA  
Thermal resistance junction-to-ambient  
TJC  
Thermal resistance junction-to-case  
46  
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
Copyright © 2007, Texas Instruments Incorporated  
Submit Documentation Feedback  
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Product Folder Link(s): CDCE913 CDCEL913  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
RECOMMENDED OPERATING CONDITIONS  
MIN  
1.7  
2.3  
1.7  
NOM  
MAX  
1.9  
UNIT  
VDD  
VO  
Device supply voltage  
1.8  
V
Output Yx supply voltage for CDCE913, VDDOUT  
Output Yx supply voltage for CDCEL913, VDDOUT  
Low-level input voltage LVCMOS  
High-level input voltage LVCMOS  
Input voltage threshold LVCMOS  
Input voltage range S0  
3.6  
1.9  
V
VIL  
0.3 VDD  
V
V
V
VIH  
0.7 VDD  
VI (thresh)  
0.5 VDD  
0
0
0
1.9  
3.6  
1.9  
±12  
±10  
±8  
VI(S)  
V
V
Input voltage range S1, S2, SDA, SCL; VI(thresh) = 0.5 VDD  
Input voltage range CLK  
VI(CLK)  
Output current (VDDOUT = 3.3 V)  
Output current (VDDOUT = 2.5 V)  
Output current (VDDOUT = 1.8 V)  
Output load LVCMOS  
IOH /IOL  
mA  
CL  
TA  
15  
pF  
Operating free-air temperature  
–40  
85  
°C  
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS(1)  
MIN  
NOM  
MAX  
32  
UNIT  
MHz  
fXtal  
ESR  
fPR  
Crystal input frequency range (fundamental mode)  
Effective series resistance  
Pulling range (0 V VCtrl 1.8 V)(2)  
Frequency control voltage, VCtrl  
Pullability ratio  
8
27  
100  
±120  
0
±150  
ppm  
V
VDD  
220  
20  
C0/C1  
CL  
On-chip load capacitance at Xin and Xout  
0
pF  
(1) For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).  
(2) Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm  
applies for crystal listed in the application report (SCAA085).  
EEPROM SPECIFICATION  
MIN  
100  
10  
TYP  
MAX  
UNIT  
cycles  
years  
EEcyc  
EEret  
Programming cycles of EEPROM  
Data retention  
1000  
4
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Copyright © 2007, Texas Instruments Incorporated  
Product Folder Link(s): CDCE913 CDCEL913  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
TIMING REQUIREMENTS  
over recommended ranges of supply voltage, load, and operating free-air temperature  
MIN  
NOM  
MAX  
UNIT  
CLK_IN REQUIREMENTS  
PLL bypass mode  
0
8
160  
160  
3
fCLK  
tr / tf  
LVCMOS clock input frequency  
MHz  
ns  
PLL mode  
Rise and fall time CLK signal (20% to 80%)  
Duty cycle CLK at VDD/2  
40%  
60%  
STANDARD  
MODE  
FAST  
MODE  
UNIT  
MIN  
MAX  
MIN  
MAX  
SDA/SCL TIMING REQUIREMENTS (see Figure 12)  
fSCL  
SCL clock frequency  
0
4.7  
4
100  
0
0.6  
0.6  
1.3  
0.6  
0
400  
kHz  
μs  
μs  
μs  
μs  
μs  
ns  
ns  
ns  
μs  
μs  
tsu(START)  
th(START)  
tw(SCLL)  
tw(SCLH)  
th(SDA)  
tsu(SDA)  
tr  
START setup time (SCL high before SDA low)  
START hold time (SCL low after SDA low)  
SCL low-pulse duration  
4.7  
4
SCL high-pulse duration  
SDA hold time (SDA valid after SCL low)  
SDA setup time  
0
3.45  
0.9  
250  
100  
SCL/SDA input rise time  
1000  
300  
300  
300  
tf  
SCL/SDA input fall time  
tsu(STOP)  
tBUS  
STOP setup time  
4
0.6  
1.3  
Bus free time between a STOP and START condition  
4.7  
Copyright © 2007, Texas Instruments Incorporated  
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Product Folder Link(s): CDCE913 CDCEL913  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
DEVICE CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
OVERALL PARAMETER  
TEST CONDITIONS  
MIN TYP(1)  
MAX  
UNIT  
All outputs off, fCLK = 27 MHz, All PLLS on  
fVCO = 135 MHz;  
fOUT = 27 MHz  
11  
9
IDD  
Supply current (see Figure 3)  
mA  
Per PLL  
VDDOUT = 3.3 V  
VDDOUT = 1.8 V  
1.3  
0.7  
No load, all outputs on,  
fOUT = 27 MHz  
IDD(OUT)  
Supply current (see Figure 4 and Figure 5)  
mA  
Power-down current. Every circuit powered  
down except SDA/SCL  
IDD(PD)  
V(PUC)  
fVCO  
fIN = 0 MHz,  
VDD = 1.9 V  
30  
μA  
Supply voltage Vdd threshold for power-up  
control circuit  
0.85  
1.45  
230  
V
VCO frequency range of PLL  
80  
230  
230  
MHz  
VDDOUT = 3.3 V  
VDDOUT = 1.8 V  
fOUT  
LVCMOS output frequency  
MHz  
LVCMOS PARAMETER  
VIK  
II  
LVCMOS input voltage  
VDD = 1.7 V; II = –18 mA  
VI = 0 V or VDD; VDD = 1.9 V  
VI = VDD; VDD = 1.9 V  
VI = 0 V; VDD = 1.9 V  
VIClk = 0 V or VDD  
–1.2  
±5  
5
V
LVCMOS Input current  
μA  
μA  
μA  
IIH  
IIL  
LVCMOS Input current for S0/S1/S2  
LVCMOS Input current for S0/S1/S2  
Input capacitance at Xin/Clk  
Input capacitance at Xout  
–4  
6
2
3
CI  
VIXout = 0 V or VDD  
pF  
Input capacitance at S0/S1/S2  
VIS = 0 V or VDD  
CDCE913 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE  
VDDOUT = 3 V, IOH = –0.1 mA  
2.9  
2.4  
2.2  
VOH  
LVCMOS high-level output voltage  
VDDOUT = 3 V, IOH = –8 mA  
VDDOUT = 3 V, IOH = –12 mA  
VDDOUT = 3 V, IOL = 0.1 mA  
VDDOUT = 3 V, IOL = 8 mA  
VDDOUT = 3 V, IOL = 12 mA  
PLL bypass  
V
V
0.1  
0.5  
0.8  
VOL  
LVCMOS low-level output voltage  
tPLH, tPHL Propagation delay  
3.2  
0.6  
50  
ns  
ns  
ps  
ps  
ps  
tr/tf  
Rise and fall time  
Cycle-to-cycle jitter(2)  
Peak-to-peak period jitter(3)  
Output skew (4) , See Table 2  
VDDOUT = 3.3 V (20%–80%)  
1 PLL switching, Y2-to-Y3  
1 PLL switching, Y2-to-Y3  
fOUT = 50 MHz; Y1-to-Y3  
fVCO = 100 MHz; Pdiv = 1  
(3)  
tjit(cc)  
tjit(per)  
tsk(o)  
odc  
70  
100  
60  
60  
(5)  
Output duty cycle  
45%  
55%  
CDCE913 – LVCMOS PARAMETER for VDDOUT = 2.5 V – Mode  
VDDOUT = 2.3 V, IOH = –0.1 mA  
2.2  
1.7  
1.6  
VOH  
LVCMOS high-level output voltage  
LVCMOS low-level output voltage  
VDDOUT = 2.3 V, IOH = –6 mA  
VDDOUT = 2.3 V, IOH = –10 mA  
VDDOUT = 2.3 V, IOL = 0.1 mA  
VDDOUT = 2.3 V, IOL = 6 mA  
VDDOUT = 2.3 V, IOL = 10 mA  
PLL bypass  
V
V
0.1  
0.5  
0.7  
VOL  
tPLH, tPHL Propagation delay  
3.6  
0.8  
50  
ns  
ns  
ps  
ps  
ps  
tr/tf  
Rise and fall time  
Cycle-to-cycle jitter(2)  
Peak-to-peak period jitter(3)  
Output skew(4) , See Table 2  
Output duty cycle(5)  
VDDOUT = 2.5 V (20%–80%)  
1 PLL switching, Y2-to-Y3  
1 PLL switching, Y2-to-Y3  
fOUT = 50 MHz; Y1-to-Y3  
fVCO = 100 MHz; Pdiv = 1  
(3)  
tjit(cc)  
tjit(per)  
tsk(o)  
odc  
70  
100  
60  
60  
45%  
55%  
(1) All typical values are at respective nominal VDD  
.
(2) 10000 cycles.  
(3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).  
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.  
(5) odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr)  
6
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Product Folder Link(s): CDCE913 CDCEL913  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
DEVICE CHARACTERISTICS (continued)  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN TYP(1)  
MAX  
UNIT  
V
CDCEL913 — LVCMOS PARAMETER for VDDOUT = 1.8 V – Mode  
VDDOUT = 1.7 V, IOH = –0.1 mA  
1.6  
1.4  
1.1  
VOH  
LVCMOS high-level output voltage  
LVCMOS low-level output voltage  
VDDOUT = 1.7 V, IOH = –4 mA  
VDDOUT = 1.7 V, IOH = –8 mA  
VDDOUT = 1.7 V, IOL = 0.1 mA  
VDDOUT = 1.7 V, IOL = 4 mA  
VDDOUT = 1.7 V, IOL = 8 mA  
PLL bypass  
0.1  
0.3  
0.6  
VOL  
V
tPLH, tPHL Propagation delay  
2.6  
0.7  
80  
ns  
ns  
ps  
ps  
ps  
tr/tf  
Rise and fall time  
Cycle-to-cycle jitter  
VDDOUT = 1.8 V (20%–80%)  
1 PLL switching, Y2-to-Y3  
1 PLL switching, Y2-to-Y3  
fOUT = 50 MHz; Y1-to-Y3  
fVCO = 100 MHz; Pdiv = 1  
(6)(7)  
tjit(cc)  
tjit(per)  
tsk(o)  
odc  
110  
130  
50  
Peak-to-peak period jitter(7)  
Output skew(8) , See Table 2  
Output duty cycle(9)  
100  
45%  
55%  
SDA/SCL PARAMETER  
VIK  
IIH  
SCL and SDA input clamp voltage  
VDD = 1.7 V; II = –18 mA  
VI = VDD; VDD = 1.9 V  
–1.2  
±10  
V
μA  
V
SCL and SDA input current  
SDA/SCL input high voltage(10)  
SDA/SCL input low voltage(10)  
SDA low-level output voltage  
SCL/SDA Input capacitance  
VIH  
VIL  
VOL  
CI  
0.7 VDD  
0.3 VDD  
0.2 VDD  
10  
V
IOL = 3 mA, VDD = 1.7 V  
VI = 0 V or VDD  
V
3
pF  
(6) 10000 cycles.  
(7) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).  
(8) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.  
(9) odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr)  
(10) SDA and SCL pins are 3.3 V tolerant.  
PARAMETER MEASUREMENT INFORMATION  
CDCE913  
CDCEL913  
1 kW  
LVCMOS  
10 pF  
1 kW  
Figure 1. Test Load  
CDCE913  
CDCEL913  
LVCMOS  
LVCMOS  
Series  
Termination  
~ 18 W  
Line Impedance  
Zo = 50 W  
Typical Driver  
Impedance  
~ 32 W  
Figure 2. Test Load for 50-Board Environment  
Copyright © 2007, Texas Instruments Incorporated  
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Product Folder Link(s): CDCE913 CDCEL913  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
TYPICAL CHARACTERISTICS  
CDCE913, CDCEL913  
SUPPLY CURRENT  
vs  
CDCE913  
OUTPUT CURRENT  
vs  
PLL FREQUENCY  
OUTPUT FREQUENCY  
30  
16  
V
= 1.8 V  
V
V
= 1.8 V,  
DD  
DD  
14  
= 3.3 V,  
DDOUT  
25  
20  
15  
10  
5
no load  
3 Outputs on  
12  
10  
8
1 PLL on  
1 Output on  
6
4
all PLL off  
2
0
all Outputs off  
0
10 30 50 70 90 110 130 150 170 190 210 230  
10  
60  
f
110  
160  
210  
f
- Output Frequency - MHz  
- Frequency - MHz  
OUT  
VCO  
Figure 3.  
Figure 4.  
CDCEL913  
OUTPUT CURRENT  
vs  
OUTPUT FREQUENCY  
4.5  
V
= 1.8 V,  
DD  
4
3.5  
3
V
= 1.8 V,  
DDOUT  
no load  
3 Outputs on  
2.5  
2
1 Output on  
1.5  
1
all Outputs off  
0.5  
0
10 30 50 70 90 110 130 150 170 190 210 230  
f
- Output Frequency - MHz  
OUT  
Figure 5.  
8
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APPLICATION INFORMATION  
CONTROL TERMINAL CONFIGURATION  
The CDCE913/CDCEL913 has three user-definable control terminals (S0, S1, and S2) which allow external  
control of device settings. They can be programmed to any of the following functions:  
Spread spectrum clocking selection spread type and spread amount selection  
Frequency selection switching between any of two user-defined frequencies  
Output state selection output configuration and power down control  
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.  
Table 1. Control Terminal Definition  
External Control Bits  
PLL1 Setting  
Y1Setting  
PLL Frequency  
Selection  
Control Function  
SSC Selection Output Y2/Y3 Selection  
Output Y1 and Power-Down Selection  
Table 2. PLLx Setting (can be selected for each PLL individual)(1)  
SSC Selection (Center/Down)  
SSCx [3-bits]  
Center  
0% (off)  
±0.25%  
±0.5%  
Down  
0% (off)  
–0.25%  
–0.5%  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
±0.75%  
±1.0%  
–0.75%  
–1.0%  
±1.25%  
±1.5%  
–1.25%  
–1.5%  
±2.0%  
–2.0%  
FREQUENCY SELECTION(2)  
FSx  
0
FUNCTION  
Frequency0  
Frequency1  
1
OUTPUT SELECTION(3) (Y2 ... Y3)  
YxYx  
FUNCTION  
0
1
State0  
State1  
(1) Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;  
(2) Frequency0 and Frequency1 can be any frequency within the specified fVCO range.  
(3) State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,  
3-state, low or active  
Table 3. Y1 Setting(1)  
Y1 SELECTION  
Y1  
0
FUNCTION  
State 0  
1
State 1  
(1) State0 and State1 are user definable in Generic Configuration  
Register and can be power down, 3-state, low, or active.  
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S1/SDA and S2/SCL pins of the CDCE913/CDCEL913 are dual function pins. In default configuration they are  
defined as SDA/SCL for the serial programming interface. They can be programmed as control-pins (S1/S2) by  
setting the appropriate bits in the EEPROM. Note that the changes to the Control Register (Bit [6] of Byte 02h)  
have no effect until they are written into the EEPROM.  
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is  
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).  
S0 is not a multi use pin; it is a control pin only.  
DEFAULT DEVICE CONFIGURATION  
The internal EEPROM of CDCE913/CDCEL913 is pre-configured with a factory default configuration as shown in  
Figure 6 (The input frequency is passed through the output as a default).This allows the device to operate in  
default mode without the extra production step of programming it. The default setting appears after power is  
supplied or after power-down/up sequence until it is reprogrammed by the user to a different application  
configuration. A new register setting is programmed via the serial SDA/SCL Interface.  
V
V
DDOUT  
GND  
DD  
Input Clock  
LV  
CMOS  
Pdiv1 =1  
Y1 = 27 MHz  
Y2 = 27 MHz  
Y3 = 27 MHz  
Xin  
27 MHz  
Crystal  
X-tal  
LV  
CMOS  
PLL1  
power down  
Pdiv2 = 1  
Xout  
S0  
LV  
CMOS  
Pdiv3 = 1  
PLL Bypass  
EEPROM  
1 = Output Enabled  
0 = Output 3-State  
Programming  
and  
SDA  
SCL  
SDA/SCL  
Register  
Programming Bus  
Figure 6. Default Configuration  
A different default setting can be programmed upon customer request. Contact Texas Instruments sales or  
marketing representative for more information.  
Table 4 shows the factory default setting for the Control Terminal Register. Note that even though 8 different  
register settings are possible, in default configuration, only the first two settings (0 and 1) can be selected with  
S0, as S1 and S2 are configured as programming pins in default mode.  
Table 4. Factory Default Setting for Control Terminal Register(1)  
Y1  
Output Selection  
Y1  
PLL1 Settings  
External Control Pins  
Frequency Selection  
SSC Selection  
Output Selection  
Y2Y3  
S2  
S1  
S0  
0
FS1  
SSC1  
off  
SCL (I2C)  
SCL (I2C)  
SDA (I2C)  
SDA (I2C)  
3-state  
fVCO1_0  
fVCO1_0  
3-state  
1
enabled  
off  
enabled  
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any  
control-pin function but they are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode  
switches all outputs ON or OFF (as previously predefined).  
SDA/SCL SERIAL INTERFACE  
The CDCE913/CDCEL913 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the  
popular SMBus or I2C specification. It operates in the standard-mode transfer (up to 100kbit/s) and fast-mode  
transfer (up to 400kbit/s) and supports 7-bit addressing.  
The S1/SDA and S2/SCL pins of the CDCE913/CDCEL913 are dual function pins. In the default configuration  
they are used as SDA/SCL serial programming interface. They can be re-programmed as general purpose  
control pins, S1 and S2, by changing the corresponding EEPROM setting, Byte 02h, Bit [6].  
10  
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DATA PROTOCOL  
The device supports Byte Write and Byte Read and Block Write and Block Read operations.  
For Byte Write/Read operations, the system controller can individually access addressed bytes.  
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with  
most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of  
Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction, all  
bytes defined in the Byte Count must be readout to correctly finish the read cycle.  
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to  
each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.  
If the EEPROM Write Cycle is initiated, the internal SDA registers are written into the EEPROM. During this Write  
Cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read  
out during the programming sequence (Byte Read or Block Read). The programming status can be monitored by  
EEPIP, byte 01h–bit 6.  
The offset of the indexed byte is encoded in the command code, as described in Table 5.  
Table 5. Slave Receiver Address (7 Bits)  
DEVICE  
A6  
1
A5  
1
A4  
0
A3  
0
A2  
1
A1(1)  
A0(1)  
R/W  
1/0  
1/0  
1/0  
1/0  
CDCE913/CDCEL913  
CDCE925/CDCEL925  
CDCE937/CDCEL937  
CDCE949/CDCEL949  
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
(1) Address bits A0 and A1 are programmable via the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to 4 devices connected to  
the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.  
COMMAND CODE DEFINITION  
Table 6. Command Code Definition  
BIT  
DESCRIPTION  
0 = Block Read or Block Write operation  
1 = Byte Read or Byte Write operation  
7
(6:0)  
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.  
Generic Programming Sequence  
1
7
1
1
8
1
1
S
Slave Address  
A
Data Byte  
A
P
R/W  
MSB  
LSB  
MSB  
LSB  
S
Start Condition  
Sr Repeated Start Condition  
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx  
Acknowledge (ACK = 0 and NACK =1)  
Stop Condition  
R/W  
A
P
Master-to-Slave Transmission  
Slave-to-Master Transmission  
Figure 7. Generic Programming Sequence  
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Byte Write Programming Sequence  
1
7
1
1
8
1
8
1
1
S
Slave Address  
Wr  
A
CommandCode  
A
Data Byte  
A
P
Figure 8. Byte Write Protocol  
Byte Read Programming Sequence  
1
7
1
1
8
1
1
7
1
1
S
Slave Address  
Wr  
A
CommandCode  
A
S
Slave Address  
Rd  
A
8
1
1
Data Byte  
A
P
Figure 9. Byte Read Protocol  
Block Write Programming Sequence(1)  
1
7
1
1
8
1
8
1
S
Slave Address  
Wr  
A
CommandCode  
A
Byte Count = N  
A
8
1
8
1
8
1
1
Data Byte 0  
A
Data Byte 1  
A
Data Byte N-1  
A
P
(1) Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose  
and should not be overwritten.  
Figure 10. Block Write Protocol  
Block Read Programming Sequence  
1
7
1
1
8
1
1
7
1
1
S
Slave Address  
Wr  
A
CommandCode  
A
Sr  
Slave Address  
Rd  
A
8
1
8
1
8
1
1
Byte Count N  
A
Data Byte 0  
A
Data Byte N-1  
A
P
Figure 11. Block Read Protocol  
Timing Diagram for the SDA/SCL Serial Control Interface  
Bit 7 (MSB)  
Bit 6  
Bit 0 (LSB)  
P
S
A
P
t
w(SCLL)  
t
w(SCLH)  
t
r
t
f
V
IH  
SCL  
V
IL  
t
t
t
su(START)  
h(START)  
su(SDA)  
t
h(SDA)  
t
su(STOP)  
t
f
t
t
r
(BUS)  
V
IH  
SDA  
V
IL  
Figure 12. Timing Diagram for SDA/SCL Serial Control Interface  
12  
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SDA/SCL HARDWARE INTERFACE  
Figure 13 shows how the CDCE913/CDCEL913 clock synthesizer is connected to the SDA/SCL serial interface  
bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the  
maximum) if many devices are connected.  
Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected  
devices. The recommended pullup value is 4.7 k. It must meet the minimum sink current of 3 mA at  
VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C™ Bus specification).  
CDCE913  
CDCEL913  
R
R
P
Master  
SDA  
P
Slave  
SCL  
C
C
BUS  
BUS  
Figure 13. SDA / SCL Hardware Interface  
SDA/SCL CONFIGURATION REGISTERS  
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and  
explanations describe the programmable functions of the CDCE913/CDCEL913. All settings can be manually  
written into the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI  
Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for  
optimized performance at lowest jitter.  
Table 7. SDA/SCL Registers  
Address Offset  
Register Description  
Generic Configuration Register  
PLL1 Configuration Register  
Table  
Table 9  
Table 10  
00h  
10h  
The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the  
Control Terminal Register. The user can predefine up to eight different control settings. These settings then can  
be selected by the external control pins, S0, S1, and S2. See the Control Terminal Configuration section.  
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Table 8. Configuration Register,  
External Control Terminals  
Y1  
PLL1 Settings  
SSC Selection  
External Control  
Pins  
Output Selection  
Frequency Selection  
Output Selection  
S2  
0
S1  
0
S0  
0
Y1  
FS1  
SSC1  
Y2Y3  
0
1
2
3
4
5
6
7
Y1_0  
Y1_1  
Y1_2  
Y1_3  
Y1_4  
Y1_5  
Y1_6  
Y1_7  
04h  
FS1_0  
FS1_1  
FS1_2  
FS1_3  
FS1_4  
FS1_5  
FS1_6  
FS1_7  
13h  
SSC1_0  
SSC1_1  
SSC1_2  
SSC1_3  
SSC1_4  
SSC1_5  
SSC1_6  
SSC1_7  
10h–12h  
Y2Y3_0  
Y2Y3_1  
Y2Y3_2  
Y2Y3_3  
Y2Y3_4  
Y2Y3_5  
Y2Y3_6  
Y2Y3_7  
15h  
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Address Offset(1)  
(1) Address Offset refers to the byte address in the Configuration Register in Table 9 and Table 10.  
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Table 9. Generic Configuration Register  
Offset(1)  
Bit(2)  
7
Acronym  
E_EL  
RID  
Default(3)  
Description  
Xb  
0h  
1h  
0b  
Device identification (read-only): 1 is CDCE913 (3.3 V out), 0 is CDCEL913 (1.8 V out)  
Revision Identification Number (read only)  
00h  
6:4  
3:0  
7
VID  
Vendor Identification Number (read only)  
Reserved – always write 0  
0 – EEPROM programming is completed  
1 – EEPROM is in programming mode  
6
5
EEPIP  
0b  
0b  
EEPROM Programming Status4:(4) (read only)  
Permanently Lock EEPROM Data(5)  
0 – EEPROM is not locked  
1 – EEPROM will be permanently locked  
EELOCK  
Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)  
01h  
4
PWDN  
INCLK  
0b  
0 – device active (PLL1 and all outputs are enabled)  
1 – device power down (PLL1 in power down and all outputs in 3-state)  
00 – Xtal  
10 – LVCMOS  
11 – reserved  
3:2  
00b  
Input clock selection:  
01 – VCXO  
1:0  
7
SLAVE_ADR  
M1  
01b  
1b  
Address Bits A0 and A1 of the Slave Receiver Address  
Clock source selection for output Y1:  
0 – input clock  
1 – PLL1 clock  
Operation mode selection for pin 12/13(6)  
6
SPICON  
0b  
0 – serial programming interface SDA (pin 13) and SCL (pin 12)  
1 – control pins S1 (pin 13) and S2 (pin 12)  
02h  
03h  
04h  
5:4  
3:2  
Y1_ST1  
Y1_ST0  
11b  
01b  
Y1-State0/1 Definition  
00 – device power down (all PLLs in power down and all  
outputs in 3-State)  
01 – Y1 disabled to 3-state  
10 – Y1 disabled to low  
11 – Y1 enabled  
1:0  
7:0  
7
Pdiv1 [9:8]  
Pdiv1 [7:0]  
Y1_7  
0 – divider reset and stand-by  
1-to-1023 – divider value  
001h  
10-Bit Y1-Output-Divider Pdiv1:  
0b  
0b  
0b  
0b  
0b  
0b  
1b  
0b  
6
Y1_6  
5
Y1_5  
4
Y1_4  
0 – State0 (predefined by Y1_ST0)  
1 – State1 (predefined by Y1_ST1)  
Y1_x State Selection(7)  
3
Y1_3  
2
Y1_2  
1
Y1_1  
0
Y1_0  
Crystal Load Capacitor Selection(8)  
Reserved – do not write other than 0  
00h 0 pF  
01h 1 pF  
02h 2 pF  
Vctr  
Xin  
VCXO  
XO  
20pF  
20pF  
i.e.  
XCSEL = 10pF  
7:3  
XCSEL  
0Ah  
:14h-to-1Fh 20 pF  
05h  
06h  
Xout  
2:0  
7:1  
0b  
7-Bit Byte Count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes  
have to be read out to correctly finish the read cycle.  
BCOUNT  
EEWRITE  
20h  
0– no EEPROM write cycle  
(4)(9)  
0
0b  
Initiate EEPROM Write Cycle  
1 – start EEPROM write cycle (internal register are saved to the EEPROM)  
(1) Writing data beyond ‘20h’ may affect device function.  
(2) All data transferred with the MSB first.  
(3) Unless customer-specific setting.  
(4) During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is  
completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).  
(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.  
Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data can no  
longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM.  
(6) Selection of “control pins” is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are  
no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins  
(SDA/SCL), and the two slave receiver address bits are reset to A0=”0” and A1=“0”.  
(7) These are the bits of the Control Terminal Register (see Table 8). The user can predefine up to eight different control settings. These  
settings then can be selected by the external control pins, S0, S1, and S2.  
(8) The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors should be used only to  
finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20  
pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which  
always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see  
application report SCAA085.  
(9) The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The  
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The  
EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out  
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.  
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Table 9. Generic Configuration Register (continued)  
Offset(1)  
Bit(2)  
Acronym  
Default(3)  
Description  
07h-0Fh  
0h  
Unused address range  
Table 10. PLL1 Configuration Register  
OFFSET(1)  
Bit(2)  
Acronym  
Default(3)  
DESCRIPTION  
SSC1: PLL1 SSC Selection (Modulation Amount)(4)  
7:5  
4:2  
1:0  
7
SSC1_7 [2:0]  
SSC1_6 [2:0]  
SSC1_5 [2:1]  
SSC1_5 [0]  
SSC1_4 [2:0]  
SSC1_3 [2:0]  
SSC1_2 [2]  
SSC1_2 [1:0]  
SSC1_1 [2:0]  
SSC1_0 [2:0]  
FS1_7  
000b  
10h  
000b  
Down  
Center  
000 (off)  
000 (off)  
001 – 0.25%  
010 – 0.5%  
011 – 0.75%  
100 – 1.0%  
101 – 1.25%  
110 – 1.5%  
111 – 2.0%  
001 ± 0.25%  
010 ± 0.5%  
011 ± 0.75%  
100 ± 1.0%  
101 ± 1.25%  
110 ± 1.5%  
111 ± 2.0%  
000b  
6:4  
3:1  
0
000b  
000b  
11h  
12h  
000b  
7:6  
5:3  
2:0  
7
000b  
000b  
0b  
(4)  
FS1_x: PLL1 Frequency Selection  
6
FS1_6  
0b  
5
FS1_5  
0b  
4
FS1_4  
0b  
13h  
14h  
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)  
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)  
3
FS1_3  
0b  
2
FS1_2  
0b  
1
FS1_1  
0b  
0
FS1_0  
0b  
0 – PLL1  
7
6
MUX1  
M2  
1b  
1b  
PLL1 Multiplexer:  
1 – PLL1 Bypass (PLL1 is in power down)  
0 – Pdiv1  
1 – Pdiv2  
Output Y2 Multiplexer:  
Output Y3 Multiplexer:  
00 – Pdiv1-Divider  
01 – Pdiv2-Divider  
10 – Pdiv3-Divider  
11 – reserved  
5:4  
M3  
10b  
3:2  
1:0  
Y2Y3_ST1  
Y2Y3_ST0  
11b  
01b  
00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)  
01 – Y2/Y3 disabled to 3-State  
10–Y2/Y3 disabled to low  
Y2, Y3-State0/1definition:  
11 – Y2/Y3 enabled  
(4)  
7
6
5
4
3
2
1
0
Y2Y3_7  
Y2Y3_6  
Y2Y3_5  
Y2Y3_4  
Y2Y3_3  
Y2Y3_2  
Y2Y3_1  
Y2Y3_0  
0b  
0b  
0b  
0b  
0b  
0b  
1b  
0b  
Y2Y3_x Output State Selection  
15h  
0 – state0 (predefined by Y2Y3_ST0)  
1 – state1 (predefined by Y2Y3_ST1)  
(1) Writing data beyond 20h may adversely affect device function.  
(2) All data is transferred MSB-first.  
(3) Unless a custom setting is used  
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external  
control pins, S0, S1, and S2.  
16  
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Copyright © 2007, Texas Instruments Incorporated  
Product Folder Link(s): CDCE913 CDCEL913  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
Table 10. PLL1 Configuration Register (continued)  
OFFSET(1)  
Bit(2)  
Acronym  
Default(3)  
DESCRIPTION  
0 – down  
1 – center  
7
SSC1DC  
0b  
PLL1 SSC down/center selection:  
16h  
0 – reset and stand-by  
1-to-127 is divider value  
6:0  
7
Pdiv2  
01h  
0b  
7-Bit Y2-Output-Divider Pdiv2:  
Reserved – do not write others than 0  
7-Bit Y3-Output-Divider Pdiv3:  
17h  
0 – reset and stand-by  
1-to-127 is divider value  
6:0  
Pdiv3  
01h  
18h  
19h  
7:0  
7:4  
3:0  
7:3  
2:0  
7:5  
4:2  
PLL1_0N [11:4]  
PLL1_0N [3:0]  
PLL1_0R [8:5]  
PLL1_0R[4:0]  
PLL1_0Q [5:3]  
PLL1_0Q [2:0]  
PLL1_0P [2:0]  
004h  
000h  
PLL1_0: 30-Bit Multiplier/Divider value for frequency fVCO1_0  
(for more information, see paragraph PLL Multiplier/Divider Definition).  
1Ah  
10h  
010b  
1Bh  
00 – fVCO1_0 < 125 MHz  
01 – 125 MHz fVCO1_0 < 150 MHz  
10 – 150 MHz fVCO1_0 < 175 MHz  
1:0  
VCO1_0_RANGE  
00b  
fVCO1_0 range selection:  
11 – fVCO1_0 175 MHz  
1Ch  
1Dh  
1Eh  
7:0  
7:4  
3:0  
7:3  
2:0  
7:5  
4:2  
PLL1_1N [11:4]  
PLL1_1N [3:0]  
PLL1_1R [8:5]  
PLL1_1R[4:0]  
PLL1_1Q [5:3]  
PLL1_1Q [2:0]  
PLL1_1P [2:0]  
004h  
000h  
PLL1_1: 30-Bit Multiplier/Divider value for frequency fVCO1_1  
(for more information see paragraph PLL Multiplier/Divider Definition)  
10h  
1Fh  
010b  
00 – fVCO1_1 < 125 MHz  
01 – 125 MHz fVCO1_1 < 150 MHz  
10 – 150 MHz fVCO1_1 < 175 MHz  
1:0  
VCO1_1_RANGE  
00b  
fVCO1_1 range selection:  
11 – fVCO1_1 175 MHz  
Copyright © 2007, Texas Instruments Incorporated  
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17  
Product Folder Link(s): CDCE913 CDCEL913  
CDCE913  
CDCEL913  
www.ti.com  
SCAS849AJUNE 2007REVISED AUGUST 2007  
PLL Multiplier/Divider Definition  
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE913/CDCEL913 can be calculated:  
ƒ
IN  
N
M
ƒ
+
 
OUT  
Pdiv  
(1)  
where  
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output  
divider.  
The target VCO frequency (ƒVCO) of each PLL can be calculated:  
N
M
ƒ
+ ƒ  
 
VCO  
IN  
(2)  
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:  
N
N
ǒlog Ǔ[if P t 0 then P + 0]  
2 M  
P = 4 – int  
NȀ  
ǒ Ǔ  
M
Q = int  
R = N– M × Q  
where  
N= N × 2P;  
N M;  
100 MHz < ƒVCO > 200 MHz.  
Example:  
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;  
fOUT = 54 MHz  
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;  
fOUT = 74.25 MHz  
fVCO = 108 MHz  
fVCO = 148.50 MHz  
P = 4 – int(log24) = 4 – 2 = 2  
N’ = 4 × 22 = 16  
P = 4 – int(log25.5) = 4 – 2 = 2  
N’ = 11 × 22 = 44  
Q = int(16) = 16  
Q = int(22) = 22  
R = 16 – 16 = 0  
R = 44 – 44 = 0  
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.  
18  
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Product Folder Link(s): CDCE913 CDCEL913  
PACKAGE OPTION ADDENDUM  
www.ti.com  
13-Aug-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
CDCE913PW  
CDCE913PWR  
CDCEL913PW  
CDCEL913PWR  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PW  
14  
14  
14  
14  
90  
2000  
90  
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
PW  
PW  
PW  
2000  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
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Copyright © 2007, Texas Instruments Incorporated  
配单直通车
CDCE913PW产品参数
型号:CDCE913PW
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25
针数:14
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:1 week
风险等级:0.82
JESD-30 代码:R-PDSO-G14
JESD-609代码:e4
长度:5 mm
湿度敏感等级:1
端子数量:14
最高工作温度:85 °C
最低工作温度:-40 °C
最大输出时钟频率:230 MHz
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:1.8 V
主时钟/晶体标称频率:32 MHz
认证状态:Not Qualified
座面最大高度:1.2 mm
子类别:Clock Generators
最大供电电压:1.9 V
最小供电电压:1.7 V
标称供电电压:1.8 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1
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