CDCLVC1310RHBR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

当前位置：IC37首页_>C字母起始型号索引_>C字母起始型号索引第670页更新时间：2025-01-13 16:03:06

产品型号CDCLVC1310RHBR的概述

概述 CDCLVC1310RHBR是一款高性能的时钟分配器和倍增器，广泛应用于通讯、网络设备和高频信号处理系统。该芯片能够在低功耗的状态下，以极高的频率稳定性和低相位噪声输出时钟信号。它是由德州仪器（Texas Instruments）公司设计并制造的，其强大的性能使其在现代数字电路中扮演着重要角色。详细参数 CDCLVC1310RHBR的主要技术参数如下： 1. 工作电压: 3.3V 2. 输入频率范围: 10 MHz 至 200 MHz 3. 输出频率范围: 10 MHz 至 200 MHz 4. 最大输入电压范围: -0.5V 至 5.5V 5. 输出驱动能力: 15 pF 6. 功耗: 小于 200 mW 7. 相位噪声: -110 dBc/Hz (在10 kHz偏移) 8. 封装类型: HTQFP-32 9. 工作温度范围: -40°C 至 85°C 该芯片支持多种输入信号...

产品型号CDCLVC1310RHBR的Datasheet PDF文件预览

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

Ten-Output Low-Jitter Low-Power Clock Buffer

Check for Samples: CDCLVC1310

FEATURES

APPLICATIONS

•

High-Performance Crystal Buffer With Ultralow

Noise Floor of –169 dBc/Hz

•

Wireless and Wired Infrastructure

Networking and Data Communications

Medical Imaging

Additive Phase Noise/Jitter Performance Is

25 fs_RMS(Typ.)

Portable Test and Measurement

High-End A/V

Operates with 3.3-V/2.5-V Core and

3.3-V/2.5-V/1.8-V/1.5-V Output Supply

Device inputs consist of primary, secondary

and crystal inputs and can be selected

manually (through pins) using the input MUX.

The primary and secondary inputs can accept

LVPECL, LVDS, HCSL, SSTL or LVCMOS

signals and crystal input.

DESCRIPTION

The CDCLVC1310 is a highly versatile, low-jitter,

low-power clock fanout buffer which can distribute to

ten low-jitter LVCMOS clock outputs from one of

three inputs, whose primary and secondary inputs

can feature differential or single-ended signals and

crystal input. Such a buffer is intended for use in a

variety of mobile and wired infrastructure, data

communication, computing, low-power medical

imaging, and portable test and measurement

applications. When the input is an illegal level, the

output is at a defined state. The core can be set to

2.5 V or 3.3 V, and output can be set to 1.5 V, 1.8 V,

2.5 V or 3.3 V. The CDCLVC1310 can be easily

configured through pin programming. The overall

additive jitter performance is 25 fs_RMS(typ). The

CDCLVC1310 is packaged in a small 32-pin 5-mm ×

5-mm QFN package.

–

Crystal Frequencies Supported Are From

8 MHz to 50 MHz

–

Differential and Single-Ended Input

Frequencies Supported Are up to 200 MHz

•

10 Single-Ended LVCMOS Outputs. The

outputs can operate at 1.5-V, 1.8-V, 2.5-V or

3.3-V Power-Supply Voltage.

–

LVCMOS Outputs Operate up to 200 MHz

Output Skew Is 30 ps (typ)

Total Propagation Delay Is 2 ns (typ)

Synchronous and Glitch-Free Output

Enable Is Available

•

Offered in QFN-32 5-mm × 5-mm Package With

Industrial Temperature Range of –40°C to 85°C

Crystal Input Can Be Overdriven With

LVCMOS Signal up to 50 MHz

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

BLOCK DIAGRAM

IN_SEL0/

IN_SEL1

v_DD

Differential/

LVCMOS

OSC

XTAL

Input

Synch Control

CDCLVC1310

Output

Figure 1. High-Level Block Diagram of CDCLVC1310

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

PINOUT DIAGRAM

CDCLVC1310

RHB Package

(Top View)

32 31 30 29 28 27 26 25

VDDO

GND

Thermal Pad

VDDO

10 11 12 13 14 15 16

P0048-18

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

PIN FUNCTIONS

I/O

TYPE

DESCRIPTION

NAME

NO(s)

4, 9, 15,

16, 21,

25, 26,

GND

PWR

Analog Power supply ground

IN_SEL0,

IN_SEL1

30, 29

Digital

Analog

Input clock selection (pulldown of 150 kΩ)

LVCMOS output enable (pulldown of 150 kΩ)

Inverting differential primary reference input, internally biased to Vdd/2 (pullup/pulldown

of 150 kΩ)

PRI_INN

PRI_INP

SEC_INN

Analog Non-inverting differential/single-ended primary reference input (pulldown of 150 kΩ)

Inverting differential secondary reference input, internally biased to Vdd/2

(pullup/pulldown of 150 kΩ)

Analog

SEC_INP

VDD

Analog Non-inverting differential/single-ended secondary reference input (pulldown of 150 kΩ)

PWR

Analog Power supply pins

2, 6, 19,

VDDO

PWR

Analog I/O power supply pins

XIN

XOUT

Analog Crystal Oscillator Input or XTAL Bypass mode

Analog Crystal Oscillator Output

Analog LVCMOS output 0

Analog LVCMOS output 1

Analog LVCMOS output 2

Analog LVCMOS output 3

Analog LVCMOS output 4

Analog LVCMOS output 5

Analog LVCMOS output 6

Analog LVCMOS output 7

Analog LVCMOS output 8

Analog LVCMOS output 9

Table 1. Input Selection

IN_SEL1

IN_SEL0

INPUT CHOSEN

PRI_IN

SEC_IN

XTAL/overdrive⁽¹⁾

XTAL bypass⁽²⁾

(1) This mode can be used to overdrive the XTAL oscillator with an

LVCMOS input. For characteristics; see LVCMOS OUTPUT

CHARACTERISTICS.

(2) This mode is only XTAL bypass. For characteristics, see LVCMOS

OUTPUT CHARACTERISTICS.

Table 2. INPUT/OUTPUT OPERATION⁽¹⁾

INPUT STATE

OUTPUT STATE

PRI_INx, SEC_INx open

Logic LOW

PRI_INP/SEC_INP = HIGH,

PRI_INN/SEC_INN = LOW

Logic HIGH

PRI_INP/SEC_INP = LOW,

PRI_INN/SEC_INN = HIGH

Logic LOW

(1) Device must have switching edge to obtain output states.

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

Table 3. OE Function

High-impedance

Enabled

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

VDD, VDDO

Supply voltage range

Input voltage range

Output voltage range

Input current

–0.5 to 4.6

–0.5 to VDD + 0.5

–0.5 to VDDO + 0.5

±20

V_IN

V_OUT

I_IN

I_OUT

T_stg

T_J

Output current

±50

Storage temperature range

Junction temperature

–65 to 150

125

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

3.135

2.375

1.6

NOM

3.3

2.5

1.8

1.5

3.3

2.5

MAX

3.465

2.625

UNIT

VDDO

VDD

Output supply voltage

Core supply voltage

1.35

1.65

3.465

2.625

–24

3.135

2.375

I_OH

I_OL

T_A

High-level output current, LVCMOS

Low-level output current, LVCMOS

Ambient temperature

°C

–40

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

UNIT

THERMAL INFORMATION

CDCLVC1310

RHB

THERMAL METRIC⁽¹⁾

32 PINS

41.7

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

°C/W

θ_JCtop

θ_JB

34.1

14.4

ψ_JT

0.9

ψ_JB

14.4

θ_JCbot

6.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

INPUT CHARACTERISTICS

over recommended ranges of supply voltage (VDDO ≤ VDD), load and ambient temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC Characteristic (OE, IN_SEL0, IN_SEL1, PRI_IN, SEC_IN)

I_IH

Input high current

Input low current

Input edge rate

VDD = 3.465 V, V_IH= 3.465 V

VDD = 3.465 V, V_IL=0V

20%–80%

µA

I_IL

–40

ΔV/ΔT

150

V/ns

kΩ

R_Pullup/downPullup/down resistance

C_INInput capacitance

Single-Ended DC Characteristic (PRI_INP, SEC_INP)⁽¹⁾

VDD = 3.3 V ±5%

VDD = 2.5 V ±5%

VDD = 3.3 V ±5%

VDD = 2.5 V ±5%

1.6

VDD + 0.3

1.3

V_IH

V_IL

Input high voltage

Input low voltage

–0.3

0.9

Single-Ended DC Characteristic (OE, IN_SEL0, IN_SEL1)

V_IH

V_IL

Input high voltage

Input low voltage

0.7 × VDD

0.3 × VDD

Differential DC Characteristic (PRI_IN, SEC_IN)

V_I,DIFF

Differential input voltage swing⁽²⁾

0.15

0.5

1.3

VDD –

0.85

V_ICM

Input common-mode voltage⁽³⁾

AC Characteristic (PRI_IN, SEC_IN)

f_IN

Input frequency

Input duty cycle

200

MHz

idc

40%

60%

(1) PRI/SEC_INN biased to VDD/2

(2) V_ILshould not be less than –0.3 V

(3) Input common-mode voltage is defined as V_IH(see Figure 19).

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

CRYSTAL CHARACTERISTICS

over recommended ranges of supply voltage, load and ambient temperature (unless otherwise noted)

PARAMETER

Equivalent series resistance (ESR)

Maximum shunt capacitance

Drive level

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100

µW

CRYSTAL OSCILLATOR CHARACTERISTICS

over recommended ranges of supply voltage, load and ambient temperature (unless otherwise noted)

PARAMETER

Mode of oscillation

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fundamental

Frequency

MHz

Frequency in overdrive mode⁽¹⁾

Frequency in bypass mode⁽²⁾

On-chip load capacitance

(1) Input signal swing (max) = 2 V; input signal t_r/t_f(max) = 10 ns; functional, but ac parameters may not be met.

(2) Input signal swing (max) = V_DD; input signal t_r/t_f(max) = 10 ns; functional, but ac parameters may not be met.

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

LVCMOS OUTPUT CHARACTERISTICS

over recommended ranges of supply voltage (VDDO ≤ VDD), load (50 Ω to VDDO/2), and ambient temperature (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_OUT

200

MHz

VDDO = 3.135 V

2.5

1.8

VDDO = 2.375 V

VDDO = 1.6 V

VDDO = 1.35 V

VDDO = 3.135 V

VDDO = 2.375 V

VDDO = 1.6 V

VDDO = 1.35 V

VDDO = 3.3 V

VDDO = 2.5 V

VDDO = 1.8 V

VDDO = 1.5 V

20% to 80%

V_OH

Output high voltage

1.15

0.95

0.5

0.4

V_OL

Output low voltage

Output impedance

R_OUT

t_SLEW-RATEOutput rise/fall slew rate

V/ns

t_SK

Output skew

Part-to-part skew⁽¹⁾

t_SK,PP

t_DELAY

Propagation delay

Single-ended input, VDD = 3.3 V,

VDDO = 3.3 V

Single-ended input, VDD = 2.5 V/3.3

V, VDDO = 1.5 V/1.8 V/2.5 V, f_IN/OUT

= 125 MHz

t_RJIT

System-level additive jitter⁽²⁾

f_S, RMS

Differential input, VDD = 3.3 V,

VDDO = 3.3 V

Differential input, VDD = 2.5V/3.3V,

VDDO = 1.5V/1.8V/2.5V, f_IN/OUT

125 MHz

10-kHz offset⁽³⁾

100-kHz offset⁽³⁾

1-MHz offset⁽³⁾

10-MHz offset⁽³⁾

20-MHz offset⁽³⁾

10-kHz offset⁽⁴⁾

100-kHz offset⁽⁴⁾

1-MHz offset⁽⁴⁾

–145

–156

–163

–164

–145

–155

–160

–161

–162

Noise floor

dBc/Hz

10-MHz offset⁽⁴⁾

20-MHz offset⁽⁴⁾

f_IN/OUT= 125 MHz, idc = 50%⁽⁵⁾

odc

t_EN

Output duty cycle

45%

55%

Output enable/disable time

Cycle

MUX_ISOLAT

ION

MUX isolation⁽⁶⁾

125 MHz

(1) Part-to-part skew is calculated as the difference between the fastest and the slowest t_pdacross multiple devices.

(2) Integration range: 12 kHz–20 MHz; input source see Application Information

(3) Single-ended input, f_IN/OUT= 125 MHz, VDD = VDDO = 3.3 V

(4) Differential input, f_IN/OUT= 125 MHz, VDD = VDDO = 3.3 V

(5) Stable V_IH, V_IL, and V_CM

(6) See Figure 18.

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

PHASE NOISE WITH XTAL⁽¹⁾SELECTED

VDD = VDDO = 2.5 V/3.3V, f_XTAL= 25 MHz, T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IB = 12 kHz to 5 MHz, VDD = VDDO

= 3.3 V

Jrms

RMS phase jitter

ps rms

IB = 12 kHz to 5 MHz, VDD = VDDO

= 2.5 V

115

f_offset= 100 Hz, VDD = VDDO = 3.3

–92

–137

–163

f_offset= 1 kHz, VDD = VDDO = 3.3 V

f_offset= 10 kHz, VDD = VDDO = 3.3

f_offset= 100 kHz, VDD = VDDO = 3.3

–168

–169

f_offset= 1 MHz, VDD = VDDO = 3.3

f_offset= 5 MHz, VDD = VDDO = 3.3

Phase noise (see Figure 15)

dBc/Hz

f_offset= 100 Hz, VDD = VDDO = 2.5

–91

–136

–159

f_offset= 1 kHz, VDD = VDDO = 2.5 V

f_offset= 10 kHz, VDD = VDDO = 2.5

f_offset= 100 kHz, VDD = VDDO = 2.5

–164

–165

f_offset= 1 MHz, VDD = VDDO = 2.5

f_offset= 5 MHz, VDD = VDDO = 2.5

(1) Crystal specification: C_L= 18 pF; ESR = 35 Ω (max); C₀= 7 pF; drive level = 100 µW (max)

DEVICE CURRENT CONSUMPTION

over recommended ranges of supply voltage, load and ambient temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OVERALL PARAMETERS FOR ALL VERSIONS

OE = 0 V or V_DD

;

Ref. input (PRI/SEC) = 0 V or V_DD

I_O= 0 mA; V_DD/V_DDO= 3.3 V

;

I_DD

Static device current⁽¹⁾

OE = 0 V or V_DD

;

Ref. input (PRI/SEC) = 0 V or V_DD

I_O= 0 mA; V_DD/V_DDO= 2.5 V

I_DD,XTAL

Device current with XTAL input⁽¹⁾

VDDO = 3.465 V; f = 100 MHz

VDDO = 2.625 V; f = 100 MHz

VDDO = 2 V; f = 100 MHz

8.8

7.7

7.3

6.9

Power dissipation capacitance per

output⁽²⁾

C_PD

VDDO = 1.65 V; f = 100 MHz

(1) I_DDand I_DD,XTALis the current through V_DD; outputs on or in the high-impedance state; no load.

(2) This is the formula for the power dissipation calculation (see Power Consideration section)

I_DD,Total= I_DD+ I_DD,Cload+ I_DD,dyn[mA]

I_DD,dyn= C_PD× V_DDO× f × n [mA]

I_DD,Cload= C_load× V_DDO× f × n [mA]

n = Number of switching output pins

Product Folder Link(s): CDCLVC1310

Submit Documentation Feedback

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

TEST CONFIGURATIONS

Figure 2 through Figure 8 illustrate how the device should be set up for a variety of test configurations.

+ VDDO/2

LVCMOS

Z_O= 50 W

output

R=50 W from

measurement

equipment

– VDDO/2

Figure 2. LVCMOS Output DC Configuration; Test Load Circuit

VDD

R = 100 k W

R = 1 k W

PRI_IN

Z = 50 W

SEC_IN

R = 100 k W

R = 1 k W

C = 0.1 mF

Clock generator:

Z + R = 50 W

Figure 3. LVCMOS Input DC Configuration During Device Test

VDD

R = 125 W

Z = 50 W

PRI_IN

LVPECL

output

SEC_IN

Z = 50 W

R = 84 W

Figure 4. LVPECL Input Configuration During Device Test

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

VDD

Z = 50 W

PRI_IN

LVPECL

output

SEC_IN

Z = 50 W

R = 50 W

Figure 5. LVPECL Input Configuration During Device Test

VDD

R = 33 W

Z = 50 W

PRI_IN

HCSL

output

SEC_IN

Z = 50 W

R = 33 W

R = 50 W

Figure 6. HCSL Input Configuration During Device Test

VDD

Z = 50 W

PRI_IN

LVD

output

R = 100 W

SEC_IN

Z = 50 W

Figure 7. LVDS Input Configuration During Device Test

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

VDD

R = 120 W

Z = 60 W

PRI_IN

SSTL

output

SEC_IN

Z = 60 W

R = 120 W

Figure 8. SSTL Input Configuration During Device Test

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

APPLICATION INFORMATION

Typical Application Load

VDDO

R_S» 35 W, 30 W, 20 W, 10 W

(V_DDO= 3.3 V, 2.5 V, 1.8 V, 1.5 V)

LVC1310

output

LVCMOS

input

Z_O= 50 W

10 pF

Figure 9. LVCMOS Output DC Configuration: Typical Application Load

Parameter Measurement Information

80%

20%

V_OUT

t_R

t_F

Figure 10. LVCMOS Output Voltage and Rise/Fall Time

PRI_IN/SEC_IN

LVCMOS

PRI_IN/SEC_IN (N)

PRI_IN/SEC_IN (P)

Differential

t_PD

LVCMOS

t_SK

Figure 11. Differential and Single-Ended Output Skew and Propagation Delay

Crystal Oscillator Input

The crystal oscillator circuit is characterized with 18-pF parallel resonant crystals. C1 and C2 were chosen to

minimize the ppm error. R_OPTIONALcan be placed to limit the drive level of the oscillator circuit.

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

R_OPTIONAL

XIN

C₁

Crystal

XOUT

C₂

Figure 12. Crystal Reference Input

The input XIN can accept single-ended LVCMOS signals in two configurations. It is possible to overdrive the

oscillator stage or to use a pure LVCMOS input (see Table 1). If the oscillator stage is overdriven, the input must

be ac-coupled with a capacitor (see Figure 13). Otherwise, if the bypass mode is selected, a coupling capacitor

is not required.

NOTE

If overdrive or bypass mode is used, the device is functional, but the ac parameters may

not be met.

VDD

R₁= 100 W

XIN

Z = 50 W

R_INT

C = 0.1 mF

XOUT

R₂= 100 W

Clock Generator:

R_INT+ R = 50 W

Figure 13. Single-Ended Crystal Input

Phase Noise Performance

The CDCLVC1310 provides ultralow phase-noise outputs (noise floor = –170 dBc/Hz) if a crystal is attached to it.

Figure 14 shows the phase-noise plot of the CDCLVC1310 with a 25-MHz crystal at V_DD= V_DDO= 3.3 V and

room temperature.

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

Figure 14. Phase Noise Profile With 25-MHz Crystal at Nominal Conditions

System-Level Additive Jitter Measurement

For high-performance devices, phase-noise measurements are influenced by limitations of the equipment. The

noise floor of the equipment often exceeds the noise floor of the device. The real noise floor of the device is

probably lower (see LVCMOS Output Characteristics). Phase noise is influenced by the input source and the

measurement equipment. Additional measurements and information about system-level additive jitter and noise

floor are available in the applications report Phase Noise Performance of CDCLVC1310 (SCAA115).

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

Figure 15. Input Phase Noise (179.4 fs, Light Blue) and Output Phase Noise (180 fs, Dark Blue)

Output Enable

If OE is pulled to LOW (t1), the outputs are forced to the high-impedance state after the next falling edge of the

input signal (t2). The outputs remain in the high-impedance state as long as OE is LOW (see Figure 16).

X_INN

Differential Input

X_INP

SE Input

X_INP

Output Enable OE

Output Yx

t₁

t₂

Figure 16. OE: Disable Outputs

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

If the outputs are in the high-impedance state and OE is pulled to HIGH, all outputs are forced to LOW

asynchronously (t3). Within two clock cycles (maximum), the outputs start switching again (t4), after a falling

edge of the input signal (see Figure 17).

X_INP

Differential input

X_INN

X_INP

SE input

Output enable OE

Output Yx

t₃

t₄

Figure 17. OE: Enable Outputs

If the outputs are in the high-impedance state and the input is static (no clock signal), OE works fully

asynchronously. A transition of OE from LOW to HIGH forces the outputs to LOW. A transition from HIGH to

LOW does not force to the high-impedance state again. Therefore, a falling edge of the input signal is needed

(see Figure 16).

MUX Isolation

MUX isolation is defined as difference in output amplitude (dB) with an active or a static input signal.

Yx, if MUX selects active input signal

MUX isolation

Yx, if MUX selects static input signal

f_carrier

Frequency [MHz]

Figure 18. Output Spectrum of an Active and a Static Input Signal

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

Differential Input Level

VDD

X_INN

V_I,DIFF

V_ICM= V_IH

X_INP

GND

V_CM

NOTE: VCM can be calculated with: V_CM= V_DD– V_ICM– V_I,DIFF/2

Figure 19. Differential Input Level

Power Consideration

The following power consideration refers to the device-consumed power consumption only. The device power

consumption is the sum of static power and dynamic power. The dynamic power usage consists of two

components:

•

Power used by the device as it switches states

Power required to charge any output load

The output load can be capacitive-only or capacitive and resistive. The following formula can be used to calculate

the power consumption of the device:

P_Dev= P_stat+ P_dyn+ P_Cload(see Figure 20 and Figure 21)

P_stat= I_DD× V_DD

P_dyn+ P_Cload= (I_DD,dyn+ I_DD,Cload) × V_DDO

where:

I_DD,dyn= C_PD× V_DDO× f × n [mA] (see Figure 22)

I_DD,Cload= C_load× V_DDO× f × n [mA]

Example for power consumption of the CDCLVC1310: 10 outputs are switching, f = 100 MHz, V_DD= V_DDO= 3.3

V and assuming C_load= 2 pF per output:

P_Dev= 46.2 mW + 117.5 mW = 163.7 mW

P_stat= 14 mA × 3.3 V = 46.2 mW

P_dyn+ P_Cload= (29 mA + 6.6 mA) x 3.3V = 117.5 mW

I_DD,dyn= 8.8 pF × 3.3 V × 100 MHz × 10 = 29 mA

I_DD,Cload= 2 pF × 3.3 V x 100 MHz × 10 = 6.6 mA

NOTE

For dimensioning the power supply, the total power consumption must be considered. The

total power consumption is the sum of device power consumption and the power

consumption of the load.

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

VDD=VDDO=2.625V

Pstat + Pdyn + PCload2pF

Pstat + Pdyn + PCload8pF

80 100 120 140 160 180 200

f − Clock Frequency (MHz)

Figure 20. Device Power Consumption vs Clock

Frequency (VDD = VDDO = 3.465 V; Load 2 pF, 8

pF; per Output)

Figure 21. Device Power Consumption vs Clock

Frequency (VDD = VDDO = 2.625 V; Load 2 pF, 8

pF; per Output)

VDDO=3.465V

VDDO=2.625V

VDDO=2.0V

VDDO=1.65V

80 100 120 140 160 180 200

f − Clock Frequency (MHz)

Figure 22. Dynamic Supply Current vs Clock Frequency (per Output)

Thermal Management

Power consumption of the CDCLVC1310 can be high enough to require attention to thermal management. For

reliability and performance reasons, the die temperature should be limited to a maximum of 125°C. That is, as an

estimate, T_A(ambient temperature) plus device power consumption times θ_JAshould not exceed 125°C.

The device package has an exposed pad that provides the primary heat removal path as well as an electrical

grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal

landing pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of

the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

A recommended land and via pattern is shown in Figure 23.

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

www.ti.com

3.0 mm

(min)

0.3 mm

(typ)

0.7 mm

(typ)

Figure 23. Recommended PCB Layout for CDCLVC1310

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

CDCLVC1310

www.ti.com

SCAS917B –JULY 2011–REVISED FEBRUARY 2012

Power Supply Filtering

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

jitter/phase noise is very critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from power supply, where the bypass capacitors

provide the very low-impedance path for high-frequency noise and guard the power-supply system against

induced fluctuations. The bypass capacitors also provide instantaneous current surges as required by the device,

and should have low ESR. To use the bypass capacitors properly, they must be placed very close to the power

supply pins and must be laid out with short loops to minimize inductance. It is recommended to add as many

high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package. It is

recommended, but not required, to insert a ferrite bead between the board power supply and the chip power

supply to isolate the high-frequency switching noises generated by the clock driver, preventing them from leaking

into the board supply. Choosing an appropriate ferrite bead with very low dc resistance is important, because it is

imperative to provide adequate isolation between the board supply and the chip supply, and to maintain a

voltage at the supply pins that is greater than the minimum voltage required for proper operation.

VDD

Board

Supply

Chip

Supply

Ferrite Bead

6 xC

0.1 µF

1 µF

10 µF

Figure 24. Power-Supply Decoupling

Submit Documentation Feedback

Product Folder Link(s): CDCLVC1310

PACKAGE OPTION ADDENDUM

www.ti.com

8-Feb-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

CDCLVC1310RHBR

ACTIVE

QFN

RHB

3000

Green (RoHS

& no Sb/Br)

CU NIPDAUAGLevel-2-260C-1 YEAR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCLVC1310RHBR

QFN

RHB

3000

330.0

12.4

5.3

1.5

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

QFN RHB 32

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

CDCLVC1310RHBR

3000

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CDCLVC1310RHBR相关文章

Fatal error

/www/wwwroot/website_ic37/s.ic37.com/index.php

504

电子百科

产品导航

产品型号CDCLVC1310RHBR的概述

产品型号CDCLVC1310RHBR的Datasheet PDF文件预览

CDCLVC1310RHBR相关产品..

CDCLVC1310RHBR相关文章