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产品型号CDCP1803RTHR的概述

CDCP1803RTHR芯片概述 CDCP1803RTHR是一款由德州仪器（Texas Instruments）公司设计和生产的高性能时钟数据恢复器（CDR），其主要应用于数据通信和网络设备中，以确保数据传输的可靠性和稳定性。该芯片的设计旨在支持高速数据连接，并能够在多种数据速率下工作，从而满足现代通信系统中对高带宽和低延迟的需求。CDCP1803RTHR以其低功耗、高性能以及灵活性而受到广泛关注，尤其是在光纤传输和以太网应用场景中。 CDCP1803RTHR的详细参数 CDCP1803RTHR具有一系列重要的技术参数： 1. 工作电压：芯片的典型工作电压为3.3V，适用于各种电源环境，具备稳定的电源管理能力。 2. 功耗：在正常工作状态下，CDCP1803RTHR的功耗较低，适合需要长时间运行的应用场合。 3. 数据速率：支持的最大数据速率可达到3.125Gbps，能...

产品型号CDCP1803RTHR的Datasheet PDF文件预览

CDCP1803

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SCAS727F –NOVEMBER 2003–REVISED DECEMBER 2013

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

Check for Samples: CDCP1803

FEATURES

RGE PACKAGE

(TOP VIEW)

•

Distributes One Differential Clock Input to

Three LVPECL Differential Clock Outputs

•

Programmable Output Divider for Two LVPECL

Outputs

•

Low-Output Skew 15 ps (Typical)

V_CCRange 3 V–3.6 V

24 23 22 21 20 19

V_DDPECL

Signaling Rate Up to 800-MHz LVPECL

V_DD

Differential Input Stage for Wide Common-

Mode Range

(1)

V_SS

•

Provides VBB Bias Voltage Output for Single-

Ended Input Signals

V_DDPECL

VBB

V_DD

V_SS

•

Receiver Input Threshold ±75 mV

10 11 12

24-Terminal QFN Package (4 mm × 4 mm)

Accepts Any Differential Signaling:

LVDS, HSTL, CML, VML, SSTL-2, and

Single-Ended: LVTTL/LVCMOS

⁽¹⁾Thermal pad must be connected to V_SS

P0024-02

DESCRIPTION

RTH PACKAGE

(TOP VIEW)

The CDCP1803 clock driver distributes one pair of

differential clock inputs to three pairs of LVPECL

differential clock outputs Y[2:0] and Y[2:0] with

minimum skew for clock distribution. The CDCP1803

is specifically designed for driving 50-Ω transmission

lines.

V_DDPECL

The CDCP1803 has three control terminals, S0, S1,

and S2, to select different output mode settings; see

Table 1 for details. The CDCP1803 is characterized

for operation from –40°C to 85°C. For use in single-

ended driver applications, the CDCP1803 also

provides a VBB output terminal that can be directly

connected to the unused input as a common-mode

voltage reference.

V_DD

(1)

V_SS

V_DDPECL

VBB

V_DD

V_SS

⁽¹⁾Thermal pad must be connected to V_SS

P0025-02

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCP1803

SCAS727F –NOVEMBER 2003–REVISED DECEMBER 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

LVPECL

Div 1

Div 2

Div 4

Div 8

Div 16

Bias

Generator

VBB

− 1.3 V

max

< 1.5 mA)

Control

B0059-02

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TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

ENABLE: Enables or disables all outputs simultaneously.

(with 60-kΩ pullup)

EN = 1: outputs on according to S[2:0] settings

EN = 0: outputs Y[2:0] off (high impedance)

See Table 1 for details.

IN, IN

3, 4

I (differential)

Differential input clock. Input stage is sensitive and has a wide common-mode range.

Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS,

CML, HSTL). Because the input is high-impedance, it is recommended to terminate the

PCB transmission line before the input (e.g., with 100 Ω across input). Input can also be

driven by a single-ended signal if the complementary input is tied to VBB. A more-

advanced scheme for single-ended signals is given in the Application Information

section near the end of this document.

The inputs employ an ESD structure protecting the inputs in case of an input voltage

exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through these inputs

is possible and must be prevented by limiting the input voltage < V_DD

No connect. Leave this terminal open or tie to ground.

S[2:0]

24, 19, 18

Select mode of operation. Defines the output configuration of Y[2:0], see Table 1 for

(with 60-kΩ pullup) configuration.

VBB

Bias voltage output can be used to bias unused complementary input IN for single-

ended input signals.

The output voltage of VBB is V_DD– 1.3 V. When driving a load, the output current drive

is limited to about 1.5 mA.

V_DDPECL

V_DD[2:0]

2, 5

Supply

Supply voltage PECL input + internal logic

8, 11, 14,

17, 20, 23

PECL output supply voltage for output Y[2:0]. Each output can be disabled by pulling

the corresponding V_DDx to GND.

CAUTION: In this mode, no voltage from outside may be forced, because internal

diodes could be forced in forward direction. Thus, it is recommended to disconnect the

output if it is not being used.

V_SS

7, 13

Supply

Device ground

Y[2:0]

9, 15, 21

10, 16, 22

O (LVPECL)

LVPECL clock outputs. These outputs provide low-skew copies of IN or down-divided

copies of clock IN based on selected mode of operation S[2:0]. If an output is unused,

the output can simply be left open to save power and minimize noise impact to the

remaining outputs.

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CONTROL TERMINAL SETTINGS

The CDCP1803 has three control terminals (S0, S1, and S2) and an enable terminal (EN) to select different

output mode settings.

Setting for Mode 20:

EN = 1

S2 = 1

S1 = 0

S0 = 1

CDCP1803

= Open

= 0 Ω

= Open

S0084-02

Figure 1. Control Terminal Setting for Example

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Table 1. Selection Mode Table

LVPECL⁽¹⁾

MODE

Off (high-z)

÷ 1

Off (high-z)

÷ 1

V_DD/2

Off (high-z)

÷ 1

÷ 2

V_DD/2

÷ 1

V_DD/2

÷ 1

÷ 4

V_DD/2

÷ 1

÷ 8

÷ 1

Off (high-z)

÷ 2

÷ 1

V_DD/2

÷ 1

÷ 4

÷ 1

Rsv

V_DD/2

÷ 1

÷ 8

÷ 1

V_DD/2

÷ 1

Off (high-z)

÷ 1

÷ 2

V_DD/2

÷ 1

÷ 2

V_DD/2

÷ 1

÷ 2

V_DD/2

÷ 1

÷ 4

÷ 2

V_DD/2

÷ 1

÷ 8

÷ 2

V_DD/2

÷ 1

Off (high-z)

÷ 1

÷ 4

V_DD/2

÷ 1

÷ 4

÷ 1

÷ 2

÷ 4

V_DD/2

÷ 1

÷ 4

÷ 1

÷ 8

÷ 4

V_DD/2

÷ 1

Off (high-z)

÷ 1

÷ 8

V_DD/2

÷ 1

÷ 8

V_DD/2

÷ 1

÷ 2

÷ 8

÷ 1

÷ 4

÷ 8

V_DD/2

÷ 1

÷ 8

÷ 1

Off (high-z)

÷ 1

÷ 16

V_DD/2

÷ 1

÷ 16

V_DD/2

÷ 1

÷ 2

÷ 16

÷ 1

÷ 4

÷ 16

V_DD/2

÷ 1

÷ 8

÷ 16

Reserved

N/A

Reserved

Low

Reserved

Low

(1) The LVPECL outputs are open-emitter stages. Thus, if the unused LVPECL outputs Y0, Y1, or Y2 are left unconnected, then the current

consumption is minimized and noise impact to remaining outputs is neglectable. Also, each output can be individually disabled by

connecting the corresponding V_DDinput to GND.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)⁽¹⁾

V_DD

V_I

Supply voltage

–0.3 V to 3.8 V

Input voltage

–0.2 V to (V_DD+ 0.2 V)

Continuous

V_O

Output voltage

Differential short-circuit current, Yn, Yn, I_OSD

Electrostatic discharge (HBM 1.5 kΩ, 100 pF), ESD

Moisture level 24-terminal QFN package (solder reflow temperature of 235°C) MSL

Storage temperature

>2000 V

T_stg

T_J

–65°C to 150°C

125°C

Maximum junction temperature

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

3.6

UNIT

V_DD

T_A

Supply voltage

3.3

Operating free-air temperature

–40

°C

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

LVPECL INPUT IN, IN

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_clk

Input frequency

800

V_DD– 0.3

1300

MHz

V_CM

High-level input common mode

Input voltage swing between IN and IN

Input current

(1)

(2)

500

125

V_IN

1300

I_IN

V_I= V_DDor 0 V

±10

μA

kΩ

R_IN

C_I

Input impedance

300

Input capacitance at IN, IN

(1) Is required to maintain ac specifications

(2) Is required to maintain device functionality

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

LVPECL OUTPUT DRIVER Y[2:0], Y[2:0]

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_clk

Output frequency, see Figure 3.

High-level output voltage

Low-level output voltage

800

V_DD– 0.81

V_DD– 1.55

MHz

V_OH

V_OL

Termination with 50 Ω to V_DD– 2 V

V_DD– 1.18

V_DD– 1.98

Output voltage swing between Y and Y,

see Figure 3.

V_O

Termination with 50 Ω to V_DD– 2 V

500

I_OZL

I_OZH

t_r/t_f

V_DD= 3.6 V, V_O= 0 V

Output 3-state current

μA

V_DD= 3.6 V, V_O= V_DD– 0.8 V

20% to 80% of V_OUTPP, see Figure 7.

Rise and fall times

200

–50

350

Output skew between any LVPECL

output Y[2:0] and Y[2:0]

t_skpecl(o)

t_Duty

See Note A in Figure 6.

Crossing point-to-crossing point

distortion

Output duty-cycle distortion⁽¹⁾

t_sk(pp)

C_O

Part-to-part skew

Any Y, see Note B in Figure 6.

V_O= V_DDor GND

300

Ω

Output capacitance

Expected output load

LOAD

(1) For an 800-MHz signal, the 50-ps error would result in a duty cycle distortion of ±4% when driven by an ideal clock input signal.

LVPECL INPUT-TO-LVPECL OUTPUT PARAMETERS

PARAMETER

TEST CONDITIONS

MIN

320

TYP

MAX UNIT

t_pd(lh)

t_pd(hl)

t_sk(p)

Propagation delay, rising edge

Propagation delay, falling edge

LVPECL pulse skew

VOX to VOX

600

100

VOX to VOX

VOX to VOX, see Note C in Figure 6.

JITTER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

JITTER CHARACTERISTICS

12 kHz to 20 MHz,

f_out= 250 MHz to 800 MHz,

divide-by-1 mode

0.15

Additive phase jitter from input to

t_jitterLVPECL

ps rms

0.25

LVPECL output Y[2:0], see Figure 2.

50 kHz to 40 MHz,

f_out= 250 MHz to 800 MHz,

divide-by-1 mode

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ADDITIVE PHASE NOISE

LVPECL OUTPUT SWING

FREQUENCY OFFSET FROM CARRIER – LVPECL

FREQUENCY

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

−110

= 3.3 V

= 25°C

−115

−120

−125

−130

−135

−140

−145

−150

−155

−160

= 3.6 V

f = 622 MHz

÷1 Mode

= 3 V

= 3.3 V

= 25°C

Load = 50 Ω to V − 2 V

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

100

10k 100k

10M 100M

f − Frequency − GHz

f − Frequency Offset From Carrier − Hz

G002

G001

Figure 2.

Figure 3.

SUPPLY CURRENT ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

All outputs enabled and terminated with 50 Ω to

V_DD– 2 V on LVPECL outputs, f = 800 MHz for LVPECL

outputs, V_DD= 3.3 V

Full load

140

Supply current

I_DD

Outputs enabled, no output load, f = 800 MHz for LVPECL

outputs, V_DD= 3.6 V

No load

Supply current saving per LVPECL

output stage disabled, no load

f = 800 MHz for LVPECL output, V_DD= 3.3 V

All outputs in high-impedance state by control logic,

f = 0 Hz, V_DD= 3.6 V

I_DDZ

Supply current, 3-state

0.5

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SUPPLY CURRENT

FREQUENCY

150

145

140

135

130

= 3.3 V,

= 255C,

50 W to V −2 V for LVPECL

3 LVPECL Outputs(P1) Running

100

300

500

700

900

1100 1300 1500

f − Frequency − MHz

G003

Figure 4.

PACKAGE THERMAL RESISTANCE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4-layer JEDEC test board (JESD51-7),

airflow = 0 ft/min

R_θJA-1QFN-24 package thermal resistance⁽¹⁾

106.6

°C/W

4-layer JEDEC test board (JESD51-7) with four

thermal vias of 22-mil diameter each,

airflow = 0 ft/min

QFN-24 package thermal resistance

R_θJA-2

55.4

°C/W

with thermal vias in PCB⁽¹⁾

(1) It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good

heat sink.

Example:

Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:

T_Chassis= 85°C (temperature of the chassis)

P_effective= I_max× V_max= 90 mA × 3.6 V = 324 mW (max power consumption inside the package)

θT_Junction= θ_JA-2× P_effective= 55.45°C/W × 324 mW = 17.97°C

T_Junction= θT_Junction+ T_Chassis= 17.97°C + 85°C = 103°C (the maximum junction temperature of

T_die-max= 125°C is not violated)

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CONTROL INPUT CHARACTERISTICS

over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN TYP

MAX UNIT

t_su

t_h

Setup time, S0, S1, S2, and EN terminals before clock IN

Hold time, S0, S1, S2, and EN terminals after clock IN

Time between latching the EN low transition and when all

outputs are disabled (how much time is required until the

outputs turn off)

t_(disable)

Time between latching the EN low-to-high transition and when

outputs are enabled based on control settings (how much time

passes before the outputs carry valid signals)

t_(enable)

μs

Rpullup

V_IH(H)

V_IL(L)

I_IH

Internal pullup resistor on S[2:0] and EN input

Three-level input high, S0, S1, S2, and EN terminals⁽¹⁾

Three-level low, S0, S1, S2, and EN terminals

kΩ

0.9 V_DD

0.1 V_DD

–5

V_I= V_DD

μA

Input current, S0, S1, S2, and EN terminals

I_IL

V_I= GND

(1) Leaving this terminal floating automatically pulls the logic level high to V_DDthrough an internal pullup resistor of 60 kΩ.

BIAS VOLTAGE VBB

over operating free-air temperature range

PARAMETER

TEST CONDITIONS

V_DD= 3 V–3.6 V, I_BB= –0.2 mA

MIN

TYP

MAX UNIT

V_DD– 1.2

VBB

Output reference voltage

V_DD– 1.4

OUTPUT REFERENCE VOLTAGE (V_BB

)

LOAD

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

= 3.3 V

−5

I − Load − mA

G004

Figure 5.

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PARAMETER MEASUREMENT INFORMATION

pd(LH1)

pd(LH2)

NOTES: A. Output skew , t_sk(o₎, is calculated as the greater of:

− The difference between the fastest and the slowest t_pd(LH)n(n = 0…2)

− The difference between the fastest and the slowest t_pd(HL)n(n = 0…2)

B. Part-to-part skew , t_sk(pp), is calculated as the greater of:

− The difference between the fastest and the slowest t_pd(LH)n( (n = 0…2 for LVPECL across multiple devices

− The difference between the fastest and the slowest t_pd(HL)n( (n = 0…2 for LVPECL across multiple devices

C. Pulseskew , t_sk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (t_pd(HL)and the low-to-high

(t_pd(LH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = | t_pd(HL)− t_pd(LH) |. Pulse skew

sometimes referred to as pulse width distortion or duty cycle skew

T0067-02

Figure 6. Waveforms for Calculation of t_sk(o)and t_sk(pp)

80%

0 V

OUT(pp)

20%

|Yn*Yn|

T0058-02

Figure 7. LVPECL Differential Output Voltage and Rise/Fall Time

PCB DESIGN FOR THERMAL FUNCTIONALITY

It is recommended to take special care of the PCB design for good thermal flow from the QFN 24-terminal

package to the PCB.

Due to the three LVPECL outputs, the current consumption of the CDCP1803 is fixed.

JEDEC JESD51-7 specifies thermal conductivity for standard PCB boards.

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PARAMETER MEASUREMENT INFORMATION (continued)

Modeling the CDCP1803 with a standard 4-layer JEDEC board results in a 59.5°C maximum temperature with

_θJAof 106.62°C/W for 25°C ambient temperature.

When deploying four thermal vias (one per quadrant), the thermal flow improves significantly, yielding 42.9°C

maximum temperature with R_θJAof 55.4°C/W for 25°C ambient temperature.

To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications enabling all

four outputs at once.

Package Thermal Pad

(Underside)

Thermal Via

Dia 0.020 In.

Top Side

Island

Heat

Dissipation

VSS Copper Plane

M0029-01

Figure 8. Recommended Thermal Via Placement

See the Quad Flatpack No-Lead Logic Packages (SCBA017) and QFN/SON PCB Attachment (SLUA271)

application reports for further package-related information.

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APPLICATION INFORMATION

LVPECL RECEIVER INPUT TERMINATION

The input of the CDCP1803 has a high impedance and comes with a large common-mode voltage range.

For optimized noise performance, it is recommended to properly terminate the PCB trace (transmission line). If a

differential signal drives the CDCP1803, then a 100-Ω termination resistor is recommended to be placed as close

as possible across the input terminals. An even better approach is to install 2 × 50-Ω resistors, with the center

tap connected to a capacitor (C) to terminate odd-mode noise and make up for transmission line mismatches.

The VBB output can also be connected to the center tap to bias the input signal to (V_DD– 1.3 V) (see Figure 9).

CDCP1803

50 Ω

LVPECL

50 Ω

150 Ω

50 Ω

VBB

150 Ω

S0085-02

Figure 9. Recommended AC-Coupling LVPECL Receiver Input Termination

CDCP1803

130 Ω

50 Ω

LVPECL

83 Ω

130 Ω

83 Ω

50 Ω

S0086-02

Figure 10. Recommended DC-Coupling LVPECL Receiver Input Termination

The CDCP1803 can also be driven by single-ended signals. Typically, the input signal becomes connected to

one input, while the complementary input must be properly biased to the center voltage of the incoming input

signal. For LVCMOS signals, this would be V_CC/2, realized by a simple voltage divider (e.g., two 10-kΩ resistors).

The best option (especially if the dc offset of the input signal might vary) is to ac-couple the input signal and then

rebias the signal using the VBB reference output. See Figure 11.

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CDCP1803

CLK

VBB

NOTE: C − AC-coupling capacitor (e.g., 10 nF)

− Capacitor keeps voltage at IN constant (e.g., 10 nF)

− Load and correct duty cycle (e.g., 50 Ω)

VBB − Bias voltage output

S0087-02

Figure 11. Typical Application Setting for Single-Ended Input Signals Driving the CDCP1803

DEVICE BEHAVIOR DURING RESET AND CONTROL-TERMINAL SWITCHING

Output Behavior From Enabling the Device (EN = 0 → 1)

In disable mode (EN = 0), all output drivers are switched in high-Z mode. The S[2:0] control inputs are also

switched off. In the same mode, all flip-flops are reset. The typical current consumption is below 500 μA.

When the device is enabled again, it takes typically 1 μs for the settling of the reference voltage and currents.

During this time, the outputs Y[2:0] and Y[2:0] drive a high signal. After the settle time, the outputs go into the low

state. Due to the synchronization of each output driver signal with the input clock, the state of the waveforms

after enabling the device is as shown in Figure 12. The inverting input and output signal is not included. The Y:/1

waveform is the undivided output driver state.

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1 µs

Y:/1

Y:/2

Y:/4

High-Z

Undefined

Low

Signal State After the Device is Enabled (IN = Low)

1 µs

Undivided State is Valid After the First

Positive Transition of the Input Clock

Y:/1

Y:/2

Y:/4

High-Z

Undefined

Low

Undefined

Low

Undefined

Low

Signal State After the Device is Enabled (IN = High)

T0068-01

Figure 12. Waveforms

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Enabling a Single Output Stage

If a single output stage becomes enabled:

•

Y[2:0] is either low or high (undefined).

Y[2:0] is the inverted signal of Y[2:0].

With the first positive clock transition, the undivided output becomes the input clock state. The divided output

states are equal to the actual internal divider. The internal divider is not reset while enabling single output drivers.

Undivided State is Valid After the First

Positive Transition of the Input Clock

ENABLE Yx:

Disabled

Enabled

Yx:/1

High-Z

Undefined

Yx:/x

Undefined

Divider State

T0069-01

Figure 13. Signal State After an Output Driver Becomes Enabled While IN = 0

Undivided State is Valid After the First

Positive Transition of the Input Clock

ENABLE Yx:

Disabled

Enabled

Yx:/1

High-Z

Undefined

Yx:/x

Divider State

T0070-01

Figure 14. Signal State After an Output Driver Becomes Enabled While IN = 1

REVISION HISTORY

spacer

Changes from Revision E (January 2007) to Revision F

Page

•

Changed t_sk(pp)Part-to-part skew - included a MAX value of 300 ps .................................................................................... 7

Changed Note B in Figure 6 From: (n = 0…2 for LVPECL, n = 3 for LVCMOS) To: (n = 0…2 for LVPECLS) across ..... 11

Submit Documentation Feedback

Product Folder Links :CDCP1803

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jan-2017

PACKAGING INFORMATION

Orderable Device

CDCP1803RGER

CDCP1803RGERG4

CDCP1803RGET

CDCP1803RGETG4

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

VQFN

RGE

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

CDCP

1803

ACTIVE

RGE

3000

250

Green (RoHS

& no Sb/Br)

-40 to 85

CDCP

1803

Green (RoHS

& no Sb/Br)

-40 to 85

CDCP

1803

250

Green (RoHS

& no Sb/Br)

-40 to 85

CDCP

1803

CDCP1803RTHR

CDCP1803RTHT

OBSOLETE

VQFN

RTH

TBD

Call TI

-40 to 85

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jan-2017

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CDCP1803 :

Enhanced Product: CDCP1803-EP

•

NOTE: Qualified Version Definitions:

Enhanced Product - Supports Defense, Aerospace and Medical Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Dec-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCP1803RGER

CDCP1803RGET

VQFN

RGE

3000

250

330.0

12.4

4.3

1.5

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Dec-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCP1803RGER

CDCP1803RGET

VQFN

RGE

3000

250

340.5

338.1

20.6

Pack Materials-Page 2

IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES

Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,

reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are

developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you

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TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI

products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,

enhancements, improvements and other changes to its TI Resources.

You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your

applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications

(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You

represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)

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You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include

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modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CDCP1803RTHR相关文章

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CDCP1803RTHR产品参数

型号:	CDCP1803RTHR
Brand Name：	Texas Instruments
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	QFN
包装说明：	HVQCCN, LCC24,.16SQ,20
针数：	24
Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01
风险等级：	5.36
系列：	1803
输入调节：	DIFFERENTIAL
JESD-30 代码：	S-PQCC-N24
长度：	4 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1
反相输出次数：
端子数量：	24
实输出次数：	3
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC24,.16SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V
Prop。Delay @ Nom-Sup：	0.6 ns
传播延迟（tpd）：	0.6 ns
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.03 ns
座面最大高度：	0.9 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm
最小 fmax：	800 MHz
Base Number Matches：	1

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