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CDCVF2510A

www.ti.com ............................................................................................................................................... SCAS764C–MARCH 2004–REVISED FEBRUARY 2009

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH POWER DOWN MODE

1

FEATURES

APPLICATIONS

•

DRAM Applications

PLL Based Clock Distributors

Non-PLL Clock Buffer

•

Designed to Meet and Exceed PC133

SDRAM Registered DIMM Specification

Rev. 1.1

•

Spread Spectrum Clock Compatible

PW PACKAGE

(TOP VIEW)

Operating Frequency 20 MHz to 175 MHz

Static Phase Error Distribution at 66 MHz to

166 MHz is ±125 ps

AGND

V_CC

1Y0

1Y1

1Y2

GND

1Y3

CLK

AV_CC

1

2

3

4

5

6

7

8

9

24

23

•

Jitter (cyc–cyc) at 66 MHz to 166 MHz is

|70| ps

22 V_CC

1Y9

1Y8

GND

21

20

19

18

Advanced Deep Submicron Process Results in

More Than 40% Lower Power

Consumption vs Current Generation

PC133 Devices

17 1Y7

16 1Y6

15 1Y5

•

Auto Frequency Detection to Disable

Device (Power-Down Mode)

1Y4

V_CC10

•

Available in Plastic 24-Pin TSSOP

G

V_CC

FBIN

11

12

14

13

Distributes One Clock Input to One Bank of

10 Outputs

FBOUT

•

External Feedback (FBIN) Terminal is

Used to Synchronize the Outputs to the Clock

Input

•

25-Ω On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

DESCRIPTION

The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The

CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback

(FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

CDCVF2510A operates at a 3.3-V V_CCand also provides integrated series-damping resistors that make it ideal

for driving point-to-point loads.

One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to

50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the

G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are

disabled to the logic-low state. The device automically goes into power-down mode when no input signal

(< 1 MHz) is applied to CLK; the outputs go into a low state.

Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application of a

fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals.

The PLL can be bypassed by strapping AV_CCto ground to use as a simple clock buffer.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCVF2510A

SCAS764C–MARCH 2004–REVISED FEBRUARY 2009............................................................................................................................................... www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED

The CDCVF2510A is characterized for operation from 0°C to 85°C.

For application information see the application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL With Spread

Spectrum Clocking (SSC) (literature number SCAA039).

FUNCTION TABLE

INPUTS

OUTPUTS

PLL

AVDD

GND

G

L

CLK

1Y(0:9)

FBOUT

Signal (delayed)

CLK (in phase)

L

Signal

L

Bypassed / Off

GND

H

L

Signal

Signal (delayed)

Bypassed / Off

3.3 V (nom)

CLK > 1 MHz

CLK < 1 MHz

L

On

Off

H

X

CLK (in phase)

L

2

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FUNCTIONAL BLOCK DIAGRAM

11

G

3

1Y0

4

1Y1

5

1Y2

8

1Y3

9

1Y4

15

1Y5

16

1Y6

17

20

21

12

24

13

1Y7

1Y8

CLK

PLL

FBIN

1Y9

23

AV

CC

FBOUT

AVAILABLE OPTIONS

PACKAGE

T_A

SMALL OUTLINE (PW)

CDCVF2510APWR

CDCVF2510APW

0°C to 85°C

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Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

Clock input. CLK provides the clock signal to be distributed by the CDCVF2510A clock driver. CLK

is used to provide the reference signal to the integrated PLL that generates the clock output signals.

CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit

is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase

lock the feedback signal to its reference signal.

CLK

24

I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to

FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is

nominally zero phase error between CLK and FBIN.

FBIN

G

13

11

12

I

Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are

disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the

same frequency as CLK.

I

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as

CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has

an integrated 25-Ω series-damping resistor.

FBOUT

1Y (0:9)

AV_CC

O

3, 4, 5, 8, 9,

15, 16, 17, 20,

21

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via

the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.

Each output has an integrated 25-Ω series-damping resistor.

Analog power supply. AV_CCprovides the power reference for the analog circuitry. In addition, AV_CC

Power can be used to bypass the PLL. When AV_CCis strapped to ground, PLL is bypassed and CLK is

buffered directly to the device outputs.

23

AGND

V_CC

1

Ground Analog ground. AGND provides the ground reference for the analog circuitry.

2, 10, 14, 22

6, 7, 18, 19

Power Power supply

Ground Ground

GND

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

AV_CC

V_CC

V_I

Supply voltage range

AV_CC< V_CC+ 0.7 V

-0.5 V to 4.3 V

-0.5 V to 4.6 V

–0.5 V to V_CC+ 0.5 V

–50 mA

(2)

Input voltage range

(2)(3)

V_O

I_IK

Voltage range applied to any output in the high or low state

Input clamp current, (V_I< 0)

I_OK

I_O

Output clamp current, (V_O< 0 or V_O> V_CC

)

±50 mA

Continuous output current, (V_O= 0 to V_CC

)

±50 mA

Continuous current through each V_CCor GND

±100 mA

(4)

Z_θJA

Z_θJC

T_J

Junction-to-ambient package thermal impedance

114.5°C/W

(4)

Junction-to-case thermal impedance

25.7°C/W

Maximum allowable junction temperature

Storage temperature range

125°C

T_stg

–65°C to 150°C

(1) AV_CCmust not exceed V_CC+ 0.7 V.

(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) This value is limited to 4.6 V maximum.

(4) The package thermal impedance and junction-to-case thermal impedance are calculated in accordance with JESD51 (no air flow

condition) and JEDEC252P (high-k board).

4

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RECOMMENDED OPERATING CONDITIONS⁽¹⁾

MIN

3

MAX UNIT

V_CC, AV_CC

Supply voltage

3.6

V

V_IH

V_IL

V_I

High-level input voltage

Low-level input voltage

Input voltage

2

0.8

V_CC

–12

12

V

0

V

I_OH

I_OL

f_clk

High-level output current

Low-level output current,

Clock frequency⁽²⁾

Input clock duty cycle

Stabilization time

mA

MHz

20

175

60%

1

40%

ms

(1) Unused inputs must be held high or low to prevent them from floating.

(2) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be

obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for

propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not

apply for input modulation under SSC application.

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_I= –18 mA

V_CC, AV_CC

3 V

MIN

TYP⁽¹⁾

MAX UNIT

V_IK

Input clamp voltage

-1.2

V

I_OH= –100 µA

I_OH= –12 mA

I_OH= –6 mA

I_OL= 100 µA

I_OL= 12 mA

I_OL= 6 mA

MIN to MAX

3 V

V_CC–0.2

2.1

V_OH

High-level output voltage

Low-level output voltage

High-level output current

V

3 V

2.4

MIN to MAX

3 V

0.2

0.8

V_OL

V

3 V

0.55

V_O= 1 V

3 V

–28

30

I_OH

V_O= 1.65 V

V_O= 3.135 V

V_O= 1.95 V

V_O= 1.65 V

V_O= 0.4 V

3.3 V

3.6 V

3 V

–36

40

mA

-8

I_OL

Low-level output current

Input current

3.3 V

3.6 V

10

±5

I_I

V_I= V_CCor GND

µA

Supply current

(static, output not switching)

V_I= V_CCor GND, I_O= 0,

Outputs: low or high

(2)

I_CC

3.6 V, 0 V

40

One input at V_CC– 0.6 V,

Other inputs at V_CCor

GND

ΔI_CC

Change in supply current

3.3 V to 3.6 V

500

µA

C_i

Input capacitance

Output capacitance

V_I= V_CCor GND

V_O= V_CCor GND

3.3 V

2.5

2.8

pF

C_o

(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

(2) For dynamic I_CCvs Frequency, see Figure 9 and Figure 10.

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SWITCHING CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature, C_L= 25 pF (see Note ⁽¹⁾and Figure 1 and

Figure 2)⁽²⁾

V_CC, AV_CC= 3.3 V

FROM

(INPUT)

TO

(OUTPUT)

± 0.3 V

PARAMETER

UNIT

MIN TYP MAX

CLK↑ = 25 MHz to 65 MHz

CLK↑ = 66 MHz to 175 MHz

Any Y

–150

–125

150

125

100

50

Phase error time-static (normalized)

(see Figure 4 through Figure 7)

t_(φ)

FBIN↑

ps

t_sk(o)

Output skew time⁽³⁾

Any Y

ps

(4)

Phase error time-jitter

CLK = 66 MHz to 175 MHz

CLK = 25 MHz to 40 MHz

CLK = 41 MHz to 59 MHz

CLK = 60 MHz to 175 MHz

CLK↑ = 25 MHz to 65 MHz

CLK↑ = 66 MHz to 175 MHz

f_(CLK)> 60 MHz

Any Y or FBOUT

–50

500

200

125

1.5

Jitter_{(cycle-cycle)}(see Figure 8)

Dynamic phase offset⁽⁵⁾

Any Y or FBOUT

ps

ns

65

t_d(φ)

FBIN↑

0.4

Duty cycle

Rise time

Fall time

Any Y or FBOUT

45%

0.3

55%

1.1

t_r

t_f

V_O= 0.4 V to 2 V

ns/V

V_O= 2 V to 0.4 V

0.3

1.1

Low-to-high propagation delay time, bypass

mode

t_PLH

t_PHL

CLK

Any Y or FBOUT

1.8

3.9

ns

High-to-low propagation delay time, bypass

mode

(1) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

(2) These parameters are not production tested.

(3) The t_sk(o)specification is only valid for equal loading of all outputs.

(4) Calculated per PC DRAM SPEC (t_{phase error}, static - jitter_{(cycle-to-cycle)}).

(5) The parameter is assured by design but cannot be 100% production tested.

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

Input

50% V

CC

t

pd

From Output

Under Test

V

OH

2 V

0.4 V

2 V

Output

500 W

50% V

CC

0.4 V

25 pF

OL

t

r

t

f

LOAD CIRCUIT FOR OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NOTES: A. C includes probe and jig capacitance.

L

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.

O

r

f

C. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

6

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FBOUT

Any Y

t

sk(o)

Any Y

t

sk(o)

Figure 2. Skew Calculations

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CLK

FBIN

t

F

(

t

F

( )n+1

)n

n = N

1

∑

t

F

(

)n

t

F

(

(N is a large number of samples)

=

)

N

a) Static Phase Offset

CLK

FBIN

t

F

(

F

(

)

t

F

d(

t

F

d( )

)

b) Dynamic Phase Offset

Figure 3. Static and Dynmaic Phase Offset

8

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TYPICAL CHARACTERISTICS

STATIC PHASE ERROR

vs

LOAD CAPACITANCE

STATIC PHASE ERROR

vs

LOAD CAPACITANCE

600

400

600

400

V

= 3.3 V

V

= 3.3 V

CC

f = 100 MHz

f = 133 MHz

c

C

T = 25°C

A

c

C

T

A

= 25 pF || 500 Ω

(LY1−n)

= 25°C

See Notes A, B, and C

200

0

200

0

CLK to Y1−n

−200

CLK to FBOUT

−400

−600

−400

−600

3

8

13

18

23

28

33

38

3

8

13

18

23

28

33

38

C

(LF)

− Load Capacitance − pF

C

(LF)

− Load Capacitance − pF

Figure 4.

Figure 5.

STATIC PHASE ERROR

vs

SUPPLY VOLTAGE AT FBOUT

STATIC PHASE ERROR

vs

CLOCK FREQUENCY

0

−50

0

−50

V

= 3.3 V

f = 133 MHz

CC

c

C

T

= 25 pF || 500 Ω

C

= 25 pF || 500 Ω

= 12 pF || 500 Ω

= 25°C

(LY)

= 12 pF || 500 Ω

C

T

(LF)

= 25°C

A

−100

See Notes A, B, and C

−150

−200

−250

−150

−200

−250

CLK to FBOUT

−300

−350

−400

−300

−350

−400

50

75

100

125

150

175

200

3

3.1

3.2

3.3

3.4

3.5

3.6

f − Clock Frequency − MHz

c

V

CC

− Supply Voltage at FBOUT − V

Figure 6.

Figure 7.

A. Trace length FBOUT to FBIN = 5 mm, Z_O= 50Ω

B. C_(LY)= Lumped capacitive load Y_1-n

C. C_(LFx)= Lumped feedback capacitance at FBOUT = FBIN

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TYPICAL CHARACTERISTICS (continued)

JITTER

ANALOG SUPPLY CURRENT

vs

CLOCK FREQUENCY AT FBOUT

CLOCK FREQUENCY

140

120

100

25

V

C

= 3.3 V

CC

AV = V = 3.6 V

Bias = 0/3 V

CC

= 25 pF || 500 Ω

= 12 pF || 500 Ω

(LY)

(LF)

C

T

= 25 pF || 500 Ω

= 12 pF || 500 Ω

= 25°C

(LY)

(LF)

T

= 25°C

A

20

15

10

See Notes C and D

A

See Notes A and B

80

60

Cycle to Cycle

40

5

0

20

0

50

75

100

125

150

175

200

0

25

50

75 100 125 150

175 200

f − Clock Frequency at FBOUT − MHz

c

f − Clock Frequency − MHz

c

Figure 8.

Figure 9.

SUPPLY CURRENT

vs

CLOCK FREQUENCY

250

AV = V = 3.6 V

CC

Bias = 0/3 V

C

= 25 pF || 500 Ω

= 12 pF || 500 Ω

= 25°C

(LY)

(LF)

200

150

100

T

A

See Notes A and B

50

0

25

50

75 100 125 150

175 200

f − Clock Frequency − MHz

c

Figure 10.

A. Trace length FBOUT to FBIN = 5 mm, Z_O= 50Ω

B. C_(LY)= Lumped capacitive load Y_1-n

C. C_(LFx)= Lumped feedback capacitance at FBOUT = FBIN

D. C_(LFx)= Lumped feedback capacitance at FBOUT = FBIN

10

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Revision History

Table 1. Revision History

Date

Rev

Page

Section

Description

Added static phase error - 25 MHz to 65 MHz

Added jitter - 25 MHz to 65 MHz

04/11/05

B

6

Switching Characteristics

Added Dynamic Phase Offset specification

Revised into two figures

7

8

2

Figure 2

Figure 3

Added Figure 3 for a diagram of dynamic phase offset

Revised for clarity

2/09/09

C

Function Table

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PACKAGE OPTION ADDENDUM

www.ti.com

13-Jan-2009

PACKAGING INFORMATION

Orderable Device

CDCVF2510APW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

24

60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CDCVF2510APWG4

CDCVF2510APWR

CDCVF2510APWRG4

TSSOP

PW

60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCVF2510APWR

TSSOP

PW

24

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 24

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

CDCVF2510APWR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	CDCVF2510APWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	TSSOP
包装说明：	TSSOP-24
针数：	24
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	5.26
Is Samacsys：	N
系列：	2510
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4
长度：	7.8 mm
负载电容（CL）：	25 pF
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.012 A
湿度敏感等级：	1
功能数量：	1
反相输出次数：
端子数量：	24
实输出次数：	10
最高工作温度：	85 °C
最低工作温度：
输出特性：	SERIES-RESISTOR
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP24,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	3.3 V
Prop。Delay @ Nom-Sup：	3.9 ns
传播延迟（tpd）：	3.9 ns
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.1 ns
座面最大高度：	1.2 mm
子类别：	Clock Driver
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	OTHER
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
最小 fmax：	175 MHz
Base Number Matches：	1

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