CF42CH150J3000AT全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

FEATURES

•

±15-kV Human-Body Model (HBM) ESD

Protection on Card Side

•

Offered in 114-Ball LFBGA Package for

Space-Constrained Applications

•

Logic-Level Translation Between 1.8-V, 2.5-V,

3.3-V, and 5-V Supplies

Latch-Up Performance Exceeds 250 mA Per

JESD 17

•

Integrated Card-Detect Circuitry

ESD Performance

Integrated Pullup/Pulldown Resistors Save

Board Space and Cost

– ±15-kV HBM

– ±4-kV IEC61000-4-2, Contact Discharge

•

Matched Pinout With CompactFlash™ (CF)

Connector Pin Configurations to Optimize

PCB Layout

(Latch-Up Immune)

TARGET APPLICATIONS

•

GPS PDAs

PDA Phones

Industrial PDAs

High-End Digital Cameras

•

Input-Disable Feature Allows Floating Input

Conditions

I_offSupports Partial-Power-Down Mode

Operation

DESCRIPTION/ORDERING INFORMATION

The CF4320H is a CompactFlash™ (CF) interface device designed to provide a single-chip solution for CF card

interfaces. Separate V_CCrails for the system-bus side and the CF connector-bus side allow voltage-level shifting.

This is helpful for interfacing between a core chipset that may operate from 3.3 V down to 1.65 V, and CF cards

that operate from 3.3-V or 5-V supply voltages. All the input buffers feature the input-disable function, which

allows conditional floating input signals. The input, output, and I/O buffers on the CF connector side have been

defined to comply with CF+ and CF specification revisions 1.4 and 2.0.

TYPICAL APPLICATION

V_{CC_CF}

LDO

V_IN

EN

Card Detect

V_{CC_S}

V_{CC_CF}

Card-Detect

Circuitry

Data

CF+ Module

(GPS, WLAN, etc.)

Micro-Drive

Bus-

Address

Command

Status

Address

Command

Status

CF Controller

Transceiver

Circuitry

Memory Card

Host System

CF Connector

CF4320H

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CompactFlash is a trademark of Sandisk Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

CARD-DETECT CIRCUIT

The CF4320H has an integrated card-detect circuit that generates a LOW card-detect signal when a CF card is

plugged into the socket. This circuit is supplied by a separate power-supply pin, V_{CC_SD}, which operates from

1.65 V to 5.5 V. The card-detect signal can be used to control a voltage regulator, which may power the CF slot

and the CF side of the CF4320H. The inputs to this circuitry (CD1 and CD2) have internal pullup resistors to pull

them to a HIGH logic state if there is no card in the CF slot. V_{CC_SD}is particularly helpful when the core

processor operates at a low V_CC, but the regulator needs a higher control-signal voltage.

CARD-DETECT SIGNALS

INPUTS

OUTPUT

SCD

CD1

L

CD2

L

H

L

H

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

Tape and reel

ORDERABLE PART NUMBER

CF4320HGKFR

CF4320HZKFR

TOP-SIDE MARKING

CF4320

LFBGA – GKF

LFBGA – ZKF

–40°C to 85°C

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

BUS-TRANSCEIVER CIRCUIT

Command and Status Bits

Most CF controllers are embedded in processors or microcontrollers and use GPIOs to send command signals

and receive status signals from the card to manage operation. The CF interface consists of eight control signals

and six status signals. The CF standard requires that each of these signals have a 100-kΩ pullup resistor. The

CF4320H includes an internal 100-kΩ pullup resistor on the input of each of these signals, which saves board

real estate and lowers overall system cost

COMMAND LINE BUFFERS⁽¹⁾

(BVD1, BVD2, INPACK, OE, IORD, IOWR,

READY, REG, CE1, CE2, WAIT, WE, WP)

INPUTS

OUTPUT

MASTER_EN

BUF_EN

INPUT

L

H

L

H

L

H

X

Z, Command line buffer inputs can float.

Z, low-power mode

H

(1) X = H or L

RESET⁽¹⁾

INPUTS

OUTPUT

RESET

MASTER_EN

SRESET

L

H

L

H

L

H

X

Z, low-power mode

(1) X = H or L

2

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

Data Bits

The CF4320H has 16 data lines organized as two groups of 8 bits each. The ENL signal controls the lower 8

bits (D07–D00), while the ENH signal controls the upper 8 bits (D15–D08).

LOWER 8-BIT DATA BUS TRANSCEIVERS⁽¹⁾

(D07–D00, SD07–SD00)

INPUTS

OPERATION

MASTER_EN

ENL

L

DIR (S/CF)

L

H

L

SD data to D bus

D data to SD bus

L

H

X

Isolation. D07–D00 and SD07–SD00 inputs can float.

Isolation, low-power mode

H

X

(1) X = H or L

UPPER 8-BIT DATA BUS TRANSCEIVERS⁽¹⁾

(D15–D08, SD15–SD08)

INPUTS

OPERATION

MASTER_EN

ENH

L

DIR (S/CF)

L

H

L

SD data to D bus

D data to SD bus

L

H

X

Isolation. D15–D08 and SD15–SD08 inputs can float.

Isolation, low-power mode

H

X

(1) X = H or L

Address Bits

The CF4320H has 11 unidirectional address bits flowing from the system to the CF card.

ADDRESS BUS BUFFERS⁽¹⁾

INPUTS

OUTPUT

A

MASTER_EN BUF_EN

SA

H

L

H

L

H

X

Z, SA inputs can float.

Z, low-power mode

H

X

(1) X = H or L

3

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

Direction Signal Bit

The DIR(S/CF) input controls the data direction between the system bus and the CF card. The CF4320H has

circuitry to generate a DIR_OUT signal using the SOE and SIORD signals. DIR(S/CF) and DIR_OUT are placed

adjacent to each other, which is convenient for connecting DIR(S/CF) and DIR_OUT, if DIR_OUT is used. This

saves an additional signal from the system controller to control the data direction. When either SOE or SIORD is

low, the data direction is from the CF card side to the system side (DIR_OUT = L).

DIR_OUT⁽¹⁾

INPUTS

MASTER_EN

OUTPUT

DIR_OUT

BUF_EN

SOE

L

SIORD

L

H

L

H

L

H

L

H

X

H

X

L

X

Z, low-power mode

(1) X = H or L

4

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

BOARD-OPTIMIZED PIN CONFIGURATION

GKF OR ZKF PACKAGE

(TOP VIEW)

1

2

3

4

5

6

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

TERMINAL ASSIGNMENTS

1

2

3

4

SD14

5

SD12

6

A

B

C

D

E

F

D12

D13

D14

D15

CE2

OE

D04

D05

D03

SD11

SD09

SD07

SD05

SD03

SD01

SCE1

ENH

D11

SD13

SD10

D06

SD15

V_{CC_CF}

GND

SINPACK

V_{CC_S}

GND

SD08

D07

SD06

CE1

SD04

A10

V_{CC_CF}

GND

V_{CC_S}

GND

SD02

G

H

J

A09

A08

A07

A06

A04

A03

A02

A01

A00

D00

D01

D02

WP

IORD

IOWR

WE

SD00

V_{CC_CF}

GND

V_{CC_S}

GND

ENL

MASTER_EN

SOE

BUF_EN

SIORD

SIOWR

SRESET

SREG

SBVD1

SWP

K

L

READY

RESET

WAIT

INPACK

REG

BVD2

BVD1

D08

A05

SCE2

GND

SWE

M

N

P

R

T

V_{CC_CF}

GND

V_{CC_S}

GND

SREADY

SWAIT

SBVD2

SA10

V_{CC_CF}

V_{CC_SD}

CD1

GND

V_{CC_S}

DIR(S/CF)

DIR_OUT

SA00

SA08

SA09

U

V

W

SA06

SA07

D09

CD2

SA04

SA05

D10

SCD

SA01

SA02

SA03

5

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

TERMINAL FUNCTIONS

TERMINAL

REFERENCED

DESCRIPTION

I/O⁽¹⁾

TO

NO.

A1

B1

C1

D1

E1

F1

G1

H1

J1

NAME

D12

Data bit 12 connected to card

V_{CC_CF}

V_{CC_S}

I/O

O

D13

Data bit 13 connected to card

D14

Data bit 14 connected to card

D15

Data bit 15 connected to card

CE2

OE

Card enable connected to card

Output enable connected to card

Address bit 9 connected to card

O

A09

O

A08

Address bit 8 connected to card

O

A07

Address bit 7 connected to card

O

K1

L1

A06

Address bit 6 connected to card

O

A04

Address bit 4 connected to card

O

M1

N1

P1

R1

T1

U1

V1

W1

A2

B2

C2

D2

E2

F2

G2

H2

J2

A03

Address bit 3 connected to card

O

A02

Address bit 2 connected to card

O

A01

Address bit 1 connected to card

O

A00

Address bit 0 connected to card

O

D00

Data bit 0 connected to card

I/O

I

D01

Data bit 1 connected to card

D02

Data bit 2 connected to card

WP

Write protect connected to card. Pulled up to V_{CC_CF}through 100 kΩ.

Data bit 4 connected to card

D04

I/O

O

D05

Data bit 5 connected to card

D06

Data bit 6 connected to card

D07

Data bit 7 connected to card

CE1

A10

Card enable connected to card

Address bit 10 connected to card

I/O read connected to card

O

IORD

IOWR

WE

O

I/O write connected to card

O

Write enable connected to card

O

K2

L2

READY

RESET

WAIT

INPACK

REG

BVD2

BVD1

D08

Ready connected to card. Pulled up to V_{CC_CF}through 100 kΩ.

Reset connected to card

I

O

M2

N2

P2

R2

T2

U2

V2

W2

A3

B3

C3

D3

E3

F3

G3

Wait connected to card. Pulled up to V_{CC_CF}through 100 kΩ.

Input acknowledge connected to card. Pulled up to V_{CC_CF}through 100 kΩ.

Register connected to card

I

O

BVD2 connected to card. Pulled up to V_{CC_CF}through 100 kΩ.

BVD1 connected to card. Pulled up to V_{CC_CF}through 100 kΩ.

Data bit 8 connected to card

I

I/O

Power

D09

Data bit 9 connected to card

D10

Data bit 10 connected to card

D03

Data bit 3 connected to card

D11

Data bit 11 connected to card

SD15

V_{CC_CF}

GND

V_{CC_CF}

GND

Data bit 15 connected to controller

Card-side supply voltage. V_{CC_CF}powers all card-side inputs, outputs, and I/Os.

Ground

Card-side supply voltage. V_{CC_CF}powers all card-side inputs, outputs, and I/Os.

Ground

Power

(1) I = input, O = output, I/O = input/output

6

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

TERMINAL FUNCTIONS (continued)

TERMINAL

REFERENCED

DESCRIPTION

I/O⁽¹⁾

TO

NO.

H3

J3

NAME

V_{CC_CF}

GND

Card-side supply voltage. V_{CC_CF}powers all card-side inputs, outputs, and I/Os.

Ground

Power

K3

L3

A05

Address bit 5 connected to card

V_{CC_CF}

O

GND

Ground

M3

N3

P3

R3

T3

U3

V3

W3

A4

B4

C4

V_{CC_CF}

GND

Card-side supply voltage. V_{CC_CF}powers all card-side inputs, outputs, and I/Os.

Ground

Power

V_{CC_CF}

V_{CC_SD}

CD1

Card-side supply voltage. V_{CC_CF}powers all card-side inputs, outputs, and I/Os.

Card-detect supply voltage. V_{CC_SD}powers the card-detect circuitry.

Card detect connected to card. Pulled up to V_{CC_CF}through 100 kΩ.

Card detect connected to controller

Power

I

V_{CC_SD}

V_{CC_S}

CD2

I

SCD

O

SD14

SD13

SINPACK

Data bit 14 connected to controller

I/O

Data bit 13 connected to controller

V_{CC_S}

I/O

Input acknowledge connected to controller

V_{CC_S}

I/O

Controller-side supply voltage. V_{CC_S}powers all controller-side inputs, outputs,

and I/Os.

D4

E4

F4

G4

H4

V_{CC_S}

GND

Power

Ground

Controller-side supply voltage. V_{CC_S}powers all controller-side inputs, outputs,

and I/Os.

V_{CC_S}

GND

Ground

Controller-side supply voltage. V_{CC_S}powers all controller-side inputs, outputs,

and I/Os.

V_{CC_S}

Power

I

J4

K4

L4

GND

SCE2

GND

Ground

Card enable connected to controller

Ground

V_{CC_S}

Controller-side supply voltage. V_{CC_S}powers all controller-side inputs, outputs,

and I/Os.

M4

V_{CC_S}

Power

N4

P4

GND

Ground

Controller-side supply voltage. V_{CC_S}powers all controller-side inputs, outputs,

and I/Os.

R4

V_{CC_S}

Power

T4

U4

V4

W4

A5

B5

C5

D5

E5

F5

G5

H5

J5

DIR(S/CF)

DIR_OUT

SAO0

Direction controls flow of data from system to CF and vice-versa

Data direction generated by CF4320H. Can be connected to DIR(S/CF).

Address bit 0 connected to controller

V_{CC_S}

I

O

I

SAO1

Address bit 1 connected to controller

I

SD12

Data bit 12 connected to controller

I/O

I

SD10

Data bit 10 connected to controller

SD08

Data bit 8 connected to controller

SD06

Data bit 6 connected to controller

SD04

Data bit 4 connected to controller

SD02

Data bit 2 connected to controller

SD00

Data bit 0 connected to controller

ENL

Enable for data bits 0–7. Pulled up to V_{CC_S}through 100 kΩ.

Enable for all transceivers and buffers except the card-detect circuitry

Output enable connected to controller

MASTER_EN

SOE

I

K5

L5

I

SWE

Write enable connected to controller

I

M5

SREADY

Ready connected to controller

O

7

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

TERMINAL FUNCTIONS (continued)

TERMINAL

REFERENCED

DESCRIPTION

I/O⁽¹⁾

TO

NO.

N5

P5

R5

T5

U5

V5

W5

A6

B6

C6

D6

E6

F6

G6

H6

J6

NAME

SWAIT

SBVD2

SA10

Wait connected to controller

V_{CC_S}

O

BVD2 connected to controller

O

Address bit 10 connected to controller

Address bit 8 connected to controller

Address bit 6 connected to controller

Address bit 4 connected to controller

Address bit 2 connected to controller

Data bit 11 connected to controller

Data bit 9 connected to controller

I

SA08

I

SA06

I

SA04

I

SA02

I

SD11

SD09

SD07

SD05

SD03

SD01

SCE1

ENH

I/O

Data bit 7 connected to controller

I/O

Data bit 5 connected to controller

I/O

Data bit 3 connected to controller

I/O

Data bit 1 connected to controller

I/O

Card enable connected to controller

Enable for data bits 8–15. Pulled up to V_{CC_S}through 100 kΩ.

Enable for address and control/status lines. Pulled up to V_{CC_S}through 100 kΩ.

I/O read connected to controller

I

BUF_EN

SIORD

SIOWR

SRESET

SREG

SBVD1

SWP

I

K6

L6

I

I/O write connected to controller

I

M6

N6

P6

R6

T6

U6

V6

W6

Reset connected to controller

I

Register connected to controller

I

BVD1 connected to controller

O

I

Write protect connected to controller

Address bit 9 connected to controller

Address bit 7 connected to controller

Address bit 5 connected to controller

Address bit 3 connected to controller

SA09

SA07

I

SA05

I

SA03

I

8

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

LOGIC DIAGRAM

V

CC_SD

V

CC_SD

R INT

CD1

CD2

V

CC_SD

SCD

R INT

V

CC_CF

V

CC_S

SIORD

SOE

−INT

DIR_OUT

DIR(S/CF)

−INT

V

CC_S

R INT

ENL

MASTER_EN

8

D07−D00

SD07−SD00

To 7 Other Channels

V

CC_S

R INT

ENH

8

D15−D08

SD15−SD08

To 7 Other Channels

RESET

SRESET

V

CC_S

R INT

BUF_EN

11

A10−A00

SA10−SA00

2

SIORD

SOE

−INT

SCE1, SCE2, SIORD,

SIOWR, SOE, SREG,

SWE

7

CE1, CE2, IORD,

IOWR, OE, REG, WE

V

CC_CF

R INT

6

SBVD1, SBVD2, SINPACK,

SREADY, SWAIT, SWP

BVD1, BVD2, INPACK,

READY, WAIT, WP

NOTE: R INT ≥ 100 kΩ

9

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

R1

1

3

VIN

ON/OFF

VCC_SYS

5

4

VCC_CF

BYPASS

VOUT

C1

C2

LP2985

U1

VCC_CF

0.01uF

4.7uF

C3

0.1uF

3D

3F

3T

4D

4F

4H

4M

4R

VCC_S

VCC_CF

SCD

3H

3M

3P

3R

3W

3U

3V

U2

CD1

VCC_S

1

5J

GND

CD2

MASTER_EN

BUF_EN

DIR(S/CF)

DIR_OUT

EN_L

MASTER_EN

26

CD1

D03

D11

6J

CD1

D03

BUF_EN

2

4T

4U

5H

6H

5G

6F

5F

6E

5E

6D

5D

6C

5C

6B

5B

6A

5A

4B

4A

3C

6M

4V

4W

5W

6W

5V

6V

5U

6U

5T

6T

5R

6G

4K

6K

6L

5K

6N

5L

6P

5P

4C

5M

5N

6R

4E

4G

4L

4N

4P

27

D11

D04

3

D04

D12

D05

D13

D06

D14

D07

D15

CE1

CE2

A10

VS1

OE

EN_L

28

D12

D05

EN_H

SD00

EN_H

4

D00

1T

1U

1V

3A

2A

2B

2C

2D

2U

2V

2W

3B

1A

1B

1C

1D

2L

1R

1P

1N

1M

1L

3K

1K

1J

D00

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

RESET

ADD_0

ADD_1

ADD_2

ADD_3

ADD_4

ADD_5

ADD_6

ADD_7

ADD_8

ADD_9

ADD_10

CE1

29

D01

D13

D06

D01

SD01

5

D02

SD02

30

D03

D14

D07

D03

SD03

6

D04

SD04

31

D05

D15

CE1

D05

SD05

7

D06

SD06

32

D07

CE2

A10

D07

SD07

8

D08

SD08

33

D09

VS1

OE

D09

SD09

9

D10

SD10

34

10

35

11

36

12

37

13

38

14

39

15

40

16

41

17

42

18

43

19

44

20

45

21

46

22

47

23

48

24

49

25

50

IORD

A09

IOWR

A08

WE

D11

IORD

A09

IOWR

A08

WE

A07

READY

VCC

A06

CSEL

A05

VS2

A04

RESET

A03

WAIT

A02

INPACK

A01

REG

A00

BVD2

D00

BVD1

D01

D08

D02

D09

WP

D10

CD2

GND

D11

SD11

D12

SD12

D13

SD13

D14

SD14

D15

SD15

A07

READY

RESET

A00

RESET

A00

SRESET

SA00

A01

SA01

A02

SA02

A06

A03

SA03

CSEL

A05

A04

SA04

A05

SA05

VS2

A04

A06

SA06

A07

SA07

RESET

A03

A08

1H

1G

2F

2E

1E

2G

2H

1F

2P

2J

A08

SA08

A09

SA09

WAIT

A02

A10

SA10

CE1

CE2

IORD

IOWR

OE

CE1

CE2

IORD

IOWR

OE

SCE1

SCE2

SIORD

SIOWR

SOE

INPACK

A01

CE2

IORD

REG

A00

IOWR

OE

BVD2

D00

REG

WE

REG

WE

SREG

SWE

REG

WE

BVD1

D01

BVD1

BVD2

INPACK

READY

WAIT

WP

2T

2R

2N

2K

2M

1W

3E

3G

3J

BVD1

BVD2

INPACK

READY

WAIT

WP

SBVD1

SBVD2

SINPACK

SREADY

SWAIT

SWP

BVD1

BVD2

D08

INPACK

READY

WAIT

D02

D09

WP

D10

GND

CD2

GND

CF_PROCESSOR

GND

3L

3N

GND

J1

67155-CF CONNECTOR

CF4320H

10

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

V_{CC_S}

–0.5

4.6

Supply voltage range

Input voltage range

V

V_{CC_CF}

V_{CC_SD}

–0.5

6.5

SD, SA⁽²⁾

D, A

–0.5

4.6

6.5

I/O ports

SCE1, SCE2, SIORD,

SIOWR, SOE, SREG, SWE

–0.5

4.6

V

V_I

Input ports

BVD1, BVD2, READY,

INPACK, WAIT, WP

6.5

DIR(S/CF), MASTER_EN,

ENL, ENH

Control ports

4.6

Voltage range applied to any output

in the high-impedance or power-off

state⁽²⁾

System port

CF port

–0.5

V_O

V

6.5

System port

CF port

V_I< 0

–0.5

V_{CC_S}+ 0.5

Voltage range applied to any output

in the high or low state⁽²⁾⁽³⁾

V

–0.5 V_{CC_CF}+ 0.5

I_IK

I_OK

I_O

Input clamp current

–50

mA

Output clamp current

Continuous output current

V_O< 0

±50

Continuous current through each V_{CC_S}, V_{CC_CF}, V_{CC_SD}, or GND

Package thermal impedance⁽⁴⁾

±100

θ_JA

36 °C/W

150 °C

T_stg

Storage temperature range

–65

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) This value is limited to 6.5 V maximum.

(4) The package thermal impedance is calculated in accordance with JESD 51-7.

11

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

Recommended Operating Conditions^(1)(2)(3)

V_CCI

V_CCO

MIN

1.65

3

MAX UNIT

V_{CC_SD}Card-detect supply voltage

V_{CC_S}System-side supply voltage

5.5

V_{CC_CF}

5.5

V

V_{CC_CF}CF-side supply voltage

High-level input

voltage

Card-detect inputs

(CD1, CD2)

V_IH

1.65 V to 5.5 V

V

_{CC_SD}× 0.65

V

Card-detect inputs

(CD1, CD2)

V_IL

V_IH

Low-level input voltage

V

_{CC_SD}× 0.35

1.65 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

1.65 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

1.65 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

1.65 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

3 V to 3.6 V

V

_{CC_S}× 0.65

High-level input

voltage

System port

(SD, SA, SRESET)

1.7

2

V

_{CC_S}× 0.35

System port

(SD, SA, SRESET)

V_IL

V_IH

V_IL

Low-level input voltage

0.7

0.8

V

_{CC_S}× 0.65

Control inputs

(DIR, MASTER_EN,

ENL, ENH, BUF_EN)

High-level input

voltage

1.7

2

V

_{CC_S}× 0.35

Control inputs

Low-level input voltage (DIR, MASTER_EN,

ENL, ENH, BUF_EN)

0.7

0.8

2

High-level input

CF port (D, A)

voltage

V_IH

V_IL

V

4.5 V to 5.5 V

3 V to 3.6 V

V

_{CC_CF}× 0.7

0.8

Low-level input voltage CF port (D, A)

4.5 V to 5.5 V

V

_{CC_CF}× 0.3

Card-detect output voltage

System-side output voltage

CF-side output voltage

0

V_{CC_SD}

V_{CC_S}

V_{CC_CF}

–2

V_O

V

1.65 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

4.5 V to 5.5 V

1.65 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

4.5 V to 5.5 V

1.65 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

1.65 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

3 V to 3.6 V

–4

High-level

I_OH

Card detect

output current

mA

–8

–12

2

4

Low-level

I_OL

Card detect

output current

mA

8

12

2

High-level

I_OH

System port

output current

6

mA

12

2

Low-level

I_OL

System port

output current

6

12

High-level

CF port

I_OH

mA

output current

4.5 V to 5.5 V

3 V to 3.6 V

16

12

Low-level

CF port

I_OL

output current

4.5 V to 5.5 V

16

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) All unused data inputs of the device must be held at V_CCIor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

12

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

Recommended Operating Conditions (continued)

V_CCI

V_CCO

MIN

MAX UNIT

1.65 V to 2.7 V

>20

∆t/∆v

Input transition rise or fall rate

Operating free-air temperature

2.7 V to 3.6 V

4.5 V to 5.5 V

>20

85

ns/V

T_A

–40

°C

Electrical Characteristics

over recommended operating free-air temperature range (CF card-detect logic) (unless otherwise noted)

T_A= 25°C

–40°C to 85°C

PARAMETER

TEST CONDITIONS

V_{CC_SD}

UNIT

MIN TYP MAX

MIN MAX

I_OH= –100 µA

I_OH= –2 mA

I_OH= –4 mA

I_OH= –6 mA

I_OH= –8 mA

I_OH= –12 mA

I_OL= 100 µA

I_OL= 2 mA

1.65 V to 5.5 V

1.65 V

2.3 V

V_{CC_SD}– 0.1

V_{CC_SD}– 0.2

1.2

2

1.2

2

V_OH

V_I= V_IH

V

2.7 V

2.3

2.4

3.8

2.3

2.4

3.8

3 V

4.5 V

1.65 V to 5.5 V

1.65 V

2.3 V

0.1

0.2

0.3

0.4

0.5

±1

I_OL= 4 mA

0.2

V_OL

V_I= V_IL

V

I_OL= 6 mA

2.7 V

0.3

I_OL= 8 mA

3 V

0.4

I_OL= 12 mA

4.5 V

0.5

V_I= V_{CC_SD}

±0.5

I_I

1.65 V to 5.5 V

µA

V_I= 0 V

–55

–60

60

I_off

V_Ior V_O= 0 to 5.5 V

CD1 = GND, CD2 = GND

0 V

55

µA

kΩ

R_INT

1.65 V to 5.5 V

150 300

100 300

CD1 and CD2 = V_{CC_SD}

I_{O_SD}= 0

,

0.5

1

I_{CC_SD}

5.5 V

µA

CD1 or CD2 = GND,

CD2 or CD1 = V_{CC_SD}

I_{O_SD}= 0

,

10

C_i

CD1 or CD2 V_I= V_{CC_SD}or GND

9

pF

13

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

Electrical Characteristics⁽¹⁾⁽²⁾

over recommended operating free-air temperature range (unless otherwise noted)

T_A= 25°C

–40°C to 85°C

PARAMETER

TEST CONDITIONS

V_{CC_S}

V_{CC_CF}

UNIT

MIN

TYP MAX

0.95

MIN

0.6

MAX

1.4

1.8

2

1.65 V

2.3 V

2.7 V

3 V

SOE, SCE1,

SCE2, SIORD,

SIOWR, SWE,

SREG

1.32

0.9

V_T+

V_T–

∆V_T

3 V to 5.5 V

V

1.49

1

1.67

1.2

2.2

0.8

1.15

1.32

1.5

0.7

0.9

2.2

1.65 V

2.3 V

2.7 V

3 V

0.66

0.19

0.39

0.49

0.59

0.1

SOE, SCE1,

SCE2, SIORD,

SIOWR, SWE,

SREG

0.87

3 V to 5.5 V

0.98

1.08

1.65 V

2.3 V

2.7 V

3 V

0.31

SOE, SCE1,

SCE2, SIORD,

SIOWR, SWE,

SREG

0.46

0.25

0.3

0.52

0.61

0.4

BVD1, BVD2,

READY,

INPACK, WAIT

3 V

4.5 V

3 V

1.67

1.3

1.65 V

to 3.6 V

V_T+

V

2.44

1.11

1.9

0.6

3.1

1.5

BVD1, BVD2,

READY,

INPACK, WAIT,

WP

1.65 V

to 3.6 V

V_T–

4.5 V

1.43

1

2

BVD1, BVD2,

∆V_TREADY,

INPACK, WAIT

3 V

0.58

1.02

0.35

0.6

1

1.65 V

to 3.6 V

4.5 V

1.5

1.65 V

2.3 V

2.7 V

3 V

1

1.37

1.54

1.72

0.34

0.63

0.75

0.88

0.67

0.76

0.8

0.6

1.1

1.4

1.8

2

BUF_EN, ENH,

ENL,

MASTER_EN

V_T+

3 V to 5.5 V

V

1.1

1.3

2.2

1

1.65 V

2.3 V

2.7 V

3 V

0.15

0.2

BUF_EN, ENH,

ENL,

MASTER_EN

1.2

1.32

1.5

1.1

1.2

1.3

1.4

V_T–

0.4

1.65 V

2.3 V

2.7 V

3 V

0.08

0.2

BUF_EN, ENH,

∆V_TENL,

MASTER_EN

0.26

0.3

0.86

1.65 V

to 3.6 V

V_{CC_S}

– 0.1

V_{CC_S}

– 0.2

I_OH= –100 µA

I_OH= –2 mA

I_OH= –4 mA

I_OH= –6 mA

I_OH= –12 mA

1.65 V

2.3 V

2.7 V

3 V

1.2

2

1.2

2

V_{OH_S}

V_I= V_IH

3 V to 5.5 V

V

2.3

2.4

2.3

2.4

1.65 V

to 3.6 V

I_OL= 100 µA

0.1

0.2

I_OL= 2 mA

I_OL= 4 mA

I_OL= 6 mA

I_OL= 12 mA

1.65 V

2.3 V

2.7 V

3 V

0.2

0.3

0.5

0.2

0.3

0.5

V_{OL_S}

V_I= V_IL

3 V to 5.5 V

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

14

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

Electrical Characteristics⁽¹⁾⁽²⁾(continued)

over recommended operating free-air temperature range (unless otherwise noted)

T_A= 25°C

–40°C to 85°C

PARAMETER

TEST CONDITIONS

V_{CC_S}

V_{CC_CF}

UNIT

MIN

TYP MAX

MIN

MAX

3 V to

5.5 V

V_{CC_CF}

– 0.1

V_{CC_CF}

– 0.2

I_OH= –100 µA

1.65 V

to 3.6 V

V_{OH_CF}

V_I= V_IH

V

I_OH= 12 mA

I_OH= 16 mA

3 V

2.4

3.8

2.4

3.8

5.5 V

3 V to

5.5 V

I_OL= 100 µA

0.1

0.2

1.65 V

to 3.6 V

V_{OL_CF}

V_I= V_IL

V

I_OL= 12 mA

I_OL= 16 mA

3 V

0.5

5.5 V

Inputs without

pullup resistor

3.6 V to

5.5 V

(3)

V_I= GND to V_CCI

±0.5

±1

1.65 V

to 3.6 V

I_I

µA

(3)

V_I= V_CCI

±0.5

±1

Inputs with

pullup resistor

3 V to

5.5 V

V_I= 0 V

55

60

0 to

5.5 V

S port

0 V

±0.5

±1

I_off

V_Ior V_O= 0 to 5.5 V

µA

0 to

3.6 V

CF port

0 V

5.5 V

0 V

S or CF output

ports

MASTER_EN = V_IH

V_O= V_CCOor

GND,

(4)

I_OZ

3.6 V

MASTER_EN =

don't care

V_I= V_CCIor GND

CF outputs

Inputs

(SD15–SD00,

SA10–SA00,

SCE1, SCE2,

SIORD, SIOWR,

SOE, SREG,

SWE)

I_O= 0,

ENL = V_{CC_S}

ENH = V_{CC_S}

BUF_EN = V_{CC_S}

,

V_I= V_{CC_S}or

GND

1.5

3

,

DIR(S/CF) = V_{CC_S}

1.65 V 3.6 V to

to 3.6 V 5.5 V

I_{CC_S}

µA

ENL = ENH =

BUF_EN = V_{CC_S}

1.5

36

3

I_O= 0,

Control inputs

(ENL, ENH,

BUF_EN)

DIR(S/CF) = V_{CC_S}

All other inputs =

V_{CC_S}or GND

,

One of ENL,

ENH, BUF_EN =

GND,

36

Others = V_{CC_S}

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) V_CCI= V_{CC_S}for DIR(S/CF), ENL, ENH, SD15–SD00, SA10–SA00, MASTER_EN, SRESET, SCE1, SCE2, SIORD, SIOWR, SOE,

SREG, SWE, BUF_EN

V_CCI= V_{CC_CF}for D15–D00, BVD1, BVD2, INPACK, READY, WAIT, WP

(4) For I/O ports, the parameter I_OZincludes the input leakage current.

15

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

T_A= 25°C

–40°C to 85°C

PARAMETER

TEST CONDITIONS

V_{CC_S}V_{CC_CF}

UNIT

MIN TYP MAX

MIN

MAX

I_O= 0,

DIR(S/CF) = GND,

Input

(D15–D00)

V_I= V_{CC_CF}

or GND

BVD1, BVD2, INPACK,

READY, WAIT, WP =

V_{CC_CF}

1.5

60

3

Inputs

(BVD1, BVD2,

I_{CC_CF}INPACK,

BVD1 = BVD2 = I_O= 0,

INPACK =

DIR(S/CF) = GND,

1.65 V

to 3.6 V 5.5 V

3 V to

3

µA

READY WAIT =

WP = V_{CC_CF}

D15–D00 = V_{CC_CF}or

GND

READY, WAIT,

WP)

One of BVD1,

DVD2, INPACK,

READY, WAIT,

WP = GND, All

others = V_{CC_CF}

I_O= 0,

DIR(S/CF) = GND,

D15–D00 = V_{CC_CF}or

GND

60

1.65 V

to 3.6 V 5.5 V

3 V to

R_INT

150 300

3

300

kΩ

Control inputs

SAxx, SOE,

SCE1, SCE2,

SIORD,

SIOWR, SREG,

SWE

3

9

C_i

V_I= 3.3 V or GND

3.3 V

pF

Axx, BVD1,

BVD2, READY,

INPACK, WAIT,

WP

S I/O ports

7

C_io

V_O= 3.3 V or GND

pF

CF I/O ports

12

16

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

Switching Characteristics

over recommended operating free-air temperature range (CD1, CD2) (see Figure 1)

T_A= 25°C

–40°C to 85°C

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

V_{CC_SD}

UNIT

MIN

3.1

2.7

2.4

2

TYP

7.1

4.6

4

MAX

13.5

7.1

MIN

1.8

1.6

1.2

1

MAX

1.8 V ± 0.15 V

2.5 V ± 0.2 V

2.7 V

15.5

9.1

6.8

5.5

t_pd

CD1 or CD2

SCD

5.7

ns

3.3 V ± 0.3 V

5 V ± 0.5 V

3.4

2.6

5.1

1.7

3.6

Switching Characteristics

over recommended operating free-air temperature range (BVD1, BVD2, INPACK, READY, WAIT, WP) (see Figure 1)

–40°C to

85°C

T_A= 25°C

FROM

(INPUT)

TO

(OUTPUT)

TEST

CONDITIONS

PARAMETER

V_{CC_S}

V_{CC_CF}

UNIT

MIN TYP MAX MIN MAX

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.1

2.9

2.7

2.5

2.3

6

5.6

4.6

4.2

4

10.2

9.6

6.5

5.8

5.6

4.9

2.4 12.9

2.2 13.9

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.9

1.7

1.6

1.5

10

8.6

8.8

7

MASTER_EN =

BUF_EN = V_IL

t_pd

CF input

MASTER_EN

BUF_EN

S output

ns

3.6

3.3 V ± 0.3 V 11.1 18.9 30.7

9.2 35.5

35.6

6.9 22.6

22.6

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

11.1 19.3 30.9

9.9 12.9 17.4

9.9 13.1 17.4

9.5 11.2 13.4

9.5 11.3 13.5

6.8 13.7 23.9

8

t_en

t_dis

t_en

t_dis

BUF_EN = V_IL

ns

7

6.3 18.3

6.3 18.2

6

25.1

5.4 23.3

14.5

6.1 13.4

22

4.9

4.6

5

8.6 13.3

8.5 13.6

8.1 12.2

4

BUF_EN = V_IL

3.9 14.5

4.2 13.2

3.6 18.2

7.6 35.5

8.7 35.6

6.6 22.6

6.1 18.3

6.1 18.2

5.9 24.2

4.8 22.8

3.6 14.5

3.6 14.2

3.8 12.3

3.3 12.4

4.5

8

12.2

8.7 17.7 33.2

10.7 18..3 29.3

9.6 12.4 16.6

9.6 12.6 16.7

MASTER_EN =

V_IL

9.2 10.9

13

6.9 12.9 22.3

5.4 12.4 20.5

4.4

4.2

4.6

4.1

8

12.7

MASTER_EN =

V_IL

BUF_EN

7.9 12.8

7.7 11.7

7.6 11.7

17

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

Switching Characteristics

over recommended operating free-air temperature range (data bus I/Os) (see Figure 1)

–40°C to

85°C

T_A= 25°C

FROM

(INPUT)

TO

(OUTPUT)

TEST

CONDITIONS

PARAMETER

V_{CC_S}

V_{CC_CF}

UNIT

MIN TYP MAX MIN

MAX

13.7

13.9

10

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

4.2

3.7

3.8

3.3

3.5

3

7.2 11.8

6.4 10.7

3

2.7

2.4

2.1

2.2

1.8

2.6

2.4

1.9

1.7

1.5

1.4

9.4

8

1.8 V ±

0.15 V

5.7

4.9

5.1

4.3

5.7

5.4

4.3

3.8

3.7

3.3

8

6.8

6.9

5.7

9.8

9.6

6.2

5.4

5.2

4.5

2.5 V ±

0.2 V

D

SD

12.4

8.8

3.3 V ±

0.3 V

7

MASTER_EN =

ENL = ENH = V_IL

t_pd

ns

3.4

3.1

2.8

2.6

2.5

2.2

11.1

9.6

1.8 V ±

0.15 V

8.2

2.5 V ±

0.2 V

SD

D

7

7.2

3.3 V ±

0.3 V

6

3.3 V ± 0.3 V 13.7 18.2 24.4

5.5 V ± 0.5 V 13.7 17.9 29.9

3.3 V ± 0.3 V 12.3 15.1 18.8

5.5 V ± 0.5 V 12.3 14.8 17.6

27.9

31

1.8 V ±

0.15 V

7.9

8

23

2.5 V ±

0.2 V

D

21.8

21.4

20.3

36.3

36.2

22.6

18.3

18.2

20.2

17.8

16.4

13.8

15

3.3 V ± 0.3 V 11.6

14 17.1

7.3

7.4

9.4

9.5

7.2

7.1

6.4

7.3

6.3

6.4

5.4

5.9

4.8

6

3.3 V ±

0.3 V

5.5 V ± 0.5 V 11.6 13.7 15.9

3.3 V ± 0.3 V 11.6 19.6 31.8

t_en

MASTER_EN

ENL = ENH = V_IL

ns

1.8 V ±

0.15 V

5.5 V ± 0.5 V 11.7 20.1

3.3 V ± 0.3 V 10.3 13.4

32

18

2.5 V ±

0.2 V

SD

5.5 V ± 0.5 V 10.3 13.6 18.1

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

9.8 11.6

9.8 11.7

14

3.3 V ±

0.3 V

8.6 12.8 18.1

7.6 11.5 16.4

7.8 10.8 14.7

1.8 V ±

0.15 V

2.5 V ±

0.2 V

D

6.7

7.2

6.1

9.4 12.6

9.9 13.4

8.6 11.4

3.3 V ±

0.3 V

12.5

24.2

22.8

14.5

14.2

12

t_dis

MASTER_EN

ENL = ENH = V_IL

ns

6.9 12.9 21.7

6.1 12.6 20.8

1.8 V ±

0.15 V

5.3

4.1

3.9

4

4.9

4.7

5

7.9 11.8

7.8 11.7

2.5 V ±

0.2 V

SD

7.1

7

9.8

3.3 V ±

0.3 V

4.7

3.8

18.2

18

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

Switching Characteristics (continued)

over recommended operating free-air temperature range (data bus I/Os) (see Figure 1)

–40°C to

85°C

T_A= 25°C

FROM

(INPUT)

TO

(OUTPUT)

TEST

CONDITIONS

PARAMETER

V_{CC_S}

V_{CC_CF}

UNIT

MIN TYP MAX MIN

MAX

27.2

27.8

22.8

21.6

21.4

20.3

35.5

35.6

22.6

18.3

18.2

20.2

16.6

16.4

13.1

15

3.3 V ± 0.3 V

9.4 17.6 23.4

8.3

7.7

7.9

8

1.8 V ±

0.15 V

5.5 V ± 0.5 V 13.5 17.4 22.6

3.3 V ± 0.3 V 12.3 15 18.5

5.5 V ± 0.5 V 12.3 14.7 17.4

2.5 V ±

0.2 V

D

SD

D

3.3 V ± 0.3 V 11.7 14.1

5.5 V ± 0.5 V 11.6 13.7

17

16

7.3

7.4

9.1

6.8

6.2

6.3

7.2

6.3

6.2

5.4

5.9

5.2

5.7

5

3.3 V ±

0.3 V

t_en

ENL or ENH

MASTER_EN = V_IL

ns

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

9.5 18.7 30.5

9.6 19.1 30.5

1.8 V ±

0.15 V

10

13 17.4

2.5 V ±

0.2 V

10 13.2 17.4

9.6 11.3 13.6

9.6 11.4 13.6

8.5 12.1 16.8

3.3 V ±

0.3 V

1.8 V ±

0.15 V

7.7 10.8

15

7.6 10.4 13.8

2.5 V ±

0.2 V

6.9

7.3

6.5

9.1 11.9

9.7 12.9

3.3 V ±

0.3 V

8.4

12

11

20

19

12

t_dis

ENL or ENH

MASTER_EN = V_IL

ns

24.2

22.8

14.5

14.2

12

1.8 V ±

0.15 V

5.7 11.8

4.6

4.4

4.9

4.3

7.4 11.1

7.3 11.1

3.8

3.7

4

2.5 V ±

0.2 V

SD

6.8

6.7

9.3

9.2

3.3 V ±

0.3 V

3.5

18.2

19

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

Switching Characteristics

over recommended operating free-air temperature range (SA10–SA00, SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE)

(see Figure 1)

–40°C to

85°C

T_A= 25°C

FROM

(INPUT)

TO

TEST

PARAMETER

V_{CC_S}

V_{CC_CF}

UNIT

(OUTPUT) CONDITIONS

MIN TYP MAX MIN MAX

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.4

3

6.1

5.8

4.5

4.1

3.9

3.5

5.7

5.4

4.3

3.9

3.7

3.3

9.8

9.7

6.7

6

2.5 10.4

2.4 10.2

1.8 V ±

0.15 V

MASTER_EN

2.6

2.4

2.2

2

1.8

1.7

1.4

1.3

8.4

6.8

7

CF output

= BUF_EN =

(control)

V_IL

2.5 V ±

0.2 V

5.8

5

3.3 V ±

0.3 V

5.8

t_pd

S input

ns

3.4

3.3

2.9

2.7

2.6

2.3

8.7

8.2

6.2

5.4

5.2

4.4

2.8 10.3

1.8 V ±

0.15 V

2.8

1.9

1.7

1.5

9.7

8.4

6.8

7

MASTER_EN

CF output

= BUF_EN =

(A pins)

V_IL

2.5 V ±

0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

5.8

10.8 17.9 24.8

10.8 17.5 26.2

9.4 14.2 19.4

9.4 14.1 19.3

8.7 13.1 17.8

7.9 29.7

8.1 30.2

6.4 23.3

6.6 23.1

5.8 21.4

CF output

(control)

t_en

t_dis

t_en

t_dis

t_en

MASTER_EN

BUF_EN

BUF_EN = V_IL2.5 V ± 0.2 V

3.3 V ± 0.3 V

ns

8.7

13 17.5

6

21.2

7.3 13.8 22.5

6.8 12.1 19.7

6.1 11.8 19.2

6.2 25.8

5.9 26.3

4.9 20.2

4.6 19.8

4.6 19.1

1.8 V ± 0.15 V

CF output

(control)

BUF_EN = V_IL2.5 V ± 0.2 V

3.3 V ± 0.3 V

5.9

5.6

5.4

10 16.3

11 18.3

9.2 15.5

3.9

18

12.9 17.5 23.7

13.3 17.8 24.4

11.7 14.4 17.9

11.8 14.3 17.1

11 13.3 16.2

11.1 13.2 15.3

8.9 13.6 19.7

7.6 11.8 17.1

7.7 29.7

9.4 30.2

7.5 23.3

7.7 23.1

6.9 21.4

6.5 21.2

7.5 25.8

6.6 26.3

6.6 20.1

1.8 V ± 0.15 V

CF output

(A pins)

MASTER_EN

2.5 V ± 0.2 V

= V_IL

3.3 V ± 0.3 V

1.8 V ± 0.15 V

8

11.6

16

CF output

(A pins)

MASTER_EN

2.5 V ± 0.2 V

= V_IL

BUF_EN

6.7

9.7 13.2

5

6

19.8

18.2

18

7.7 10.6 14.7

6.1 8.9 11.9

3.3 V ± 0.3 V

1.8 V ± 0.15 V

4.9

12.3 16.4 21.9

12.6 16.7 22.6

7.7 27.2

8.6 29.1

7.1 21.7

7.3 21.5

6.7 19.5

6.5 19.6

11.2 13.8

17

CF output

(A pins)

MASTER_EN

2.5 V ± 0.2 V

= V_IL

BUF_EN

11.4 13.7 16.3

10.7 12.9 15.6

10.8 12.8 14.8

3.3 V ± 0.3 V

20

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

Switching Characteristics (continued)

over recommended operating free-air temperature range (SA10–SA00, SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE)

(see Figure 1)

–40°C to

85°C

T_A= 25°C

FROM

(INPUT)

TO

TEST

PARAMETER

V_{CC_S}

V_{CC_CF}

UNIT

(OUTPUT) CONDITIONS

MIN TYP MAX MIN MAX

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

8.4 13.9 21.2

7.6 12.3 18.5

7.7 12.3 18.2

6.7 10.6 15.3

7.2 11.5 16.4

7.2 23.2

6.6 23.7

6.4 19.8

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

CF output

(A pins)

MASTER_EN

= V_IL

t_dis

BUF_EN

ns

5

5.9

4.9

18.4

18

6.4

12.5 16.6 22.3

12.8 17 23.1

11.4 14.1 17.5

11.6 14 16.9

10.9 13.2 16

10 14.3

17

8.7 27.2

8.8 29.1

7.3 21.7

7.4 21.5

MASTER_EN

= V_IL

t_en

t_dis

t_en

t_dis

t_pd

CF output

ns

6.8

20

11 13.1 15.3

8.6 13.9 21.5

7.7 12.1 19.8

7.9 12.3 18.5

6.6 10.4 17.1

7.4 11.7 17.5

6.5 19.6

7.4 23.2

6.6 23.7

6.5 19.8

MASTER_EN

= V_IL

BUF_EN

CF output

5

18.4

6.1 18.9

4.9 17

6.1

9.7 16.2

6.1 14.2 29.6

4.9 32.8

4.9 33.2

3.4 19.3

2.7 14.4

2.6 14.4

4.2 32.6

4.8 32.6

1.5 19.3

1.7 19.3

1.4 14.4

1.5 14.4

6

4.8

4.2

5.4

3.9

4.4

4.3

5

14.2

30

8.8 15.4

8.8 15.5

6.9 11.1

10 16.6

9.9 16.1

6.5 10.5

6.6 10.4

6.7 10.3

6.7 10.1

9.3 15.7

MASTER_EN

DIR_OUT BUF_EN = V_IL2.5 V ± 0.2 V

3.3 V ± 0.3 V

1.8 V ± 0.15 V

DIR_OUT BUF_EN = V_IL2.5 V ± 0.2 V

3.3 V ± 0.3 V

4

17.9

11

1.8 V ± 0.15 V

5

3.9

3.3

6

8.5

6.2

2.8

2.2

SIORD or

SOE

DIR_OUT BUF_EN = V_IL2.5 V ± 0.2 V

3.3 V ± 0.3 V

11

4.7

8.2

8.9 19.5 35.9

8.9 19.5 35.8

6.8 11.9 19.1

6.8 11.9 19.2

7.1 39.2

1.8 V ± 0.15 V

7

5

39.3

22.8

BUF_EN

DIR_OUT BUF_EN = V_IL2.5 V ± 0.2 V

3.3 V ± 0.3 V

4.9 22.8

15.8

3.9 15.9

5.8

9

13.3

4

21

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

SCES655–APRIL 2006

www.ti.com

Operating Characteristics

V_CCSand V_{CC_CF}= 3.3 V, T_A= 25°C

PARAMETER

TEST CONDITIONS

TYP UNIT

Outputs

enabled

1.93

System-port input,

CF-port output

Outputs

disabled

0.04

pF

Power dissipation capacitance

per transceiver

C_pdS

C_L= 0,

f = 10 MHz

Outputs

enabled

14.35

CF-port input,

system-port output

Outputs

disabled

0.04

Outputs

enabled

22.85

System-port input,

CF-port output

Outputs

disabled

0.04

pF

Power dissipation capacitance

per transceiver

C_pdCF

C_L= 0,

f = 10 MHz

Outputs

enabled

4.66

CF-port input,

system-port output

Outputs

disabled

3.65

22

Submit Documentation Feedback

CF4320H

CompactFlash™ BUS-INTERFACE CHIP

WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY

www.ti.com

SCES655–APRIL 2006

PARAMETER MEASUREMENT INFORMATION

V

LOAD

S1

Open

R

L

From Output

Under Test

TEST

S1

GND

t

Open

V

LOAD

GND

pd

/t

C

t

L

PLZ PZL

R

L

(see Note A)

PHZ PZH

LOAD CIRCUIT

INPUT

V

CC

V

M

V

LOAD

C

L

R

L

V

∆

V

I

t /t

r f

1.8 V ± 0.15 V

2.5 ± 0.2 V

2.7 V

V

2.7 V

V

/2

2 × V

6 V

2 kΩ

0.15 V

0.3 V

0.5 V

≤2 ns

≤2.5 ns

15 pF

CC

V

CC

1.5 V

3.3 V ± 0.3 V

5.5 V ± 0.5 V

t

w

V

I

V

I

V

M

V

M

Input

Timing

Input

V

M

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

t

su

t

h

V

I

Output

Control

(low-level

enabling)

Data

Input

V

I

V

M

V

M

V

M

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PLZ

PZL

Output

Waveform 1

S1 at V

LOAD

(see Note B)

V

/2

LOAD

V

I

V

M

Input

V

M

V

M

V + V

∆

OL

0 V

OL

t

PZH

PHZ

t

PHL

PLH

Output

Waveform 2

S1 at GND

V

OH

V

OH

V

OH

− V

∆

V

M

Output

V

M

V

M

0 V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A. C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.

O

D. The outputs are measured one at a time, with one transition per measurement.

E.

F.

G.

t

and t

are the same as t

.

dis

.

PLZ

PZL

PLH

PHZ

are the same as t

PZH

en

are the same as t .

PHL pd

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

23

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

28-Mar-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

CF4320HGKFR

CF4320HZKFR

ACTIVE

LFBGA

GKF

114

1000

TBD

SNPB

Level-3-220C-168 HR

Level-3-250C-168 HR

ZKF

1000 Green (RoHS &

no Sb/Br)

SNAGCU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	CF4320HGKFR
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	BGA
包装说明：	PLASTIC, LFBGA-114
针数：	114
Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	5.58
Is Samacsys：	N
接口集成电路类型：	INTERFACE CIRCUIT
JESD-30 代码：	R-PBGA-B114
JESD-609代码：	e0
长度：	16 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	114
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	235
认证状态：	Not Qualified
座面最大高度：	1.4 mm
最大供电电压：	5.5 V
最小供电电压：	1.65 V
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL
端子节距：	0.8 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.5 mm
Base Number Matches：	1

电子百科

产品导航

产品型号CF4320的Datasheet PDF文件预览

CF42CH150J3000AT相关产品

CF42CH150J3000AT相关文章

IC37:专业IC行业平台