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产品型号CLC007BMX的概述

CLC007BMX芯片的概述 CLC007BMX是一款由LTC(Linear Technology Corporation)推出的高性能运算放大器。该芯片以其极低的失真和高增益带宽特性而广泛应用于各种模拟信号处理的场合。CLC007BMX的设计是为了解决现代电子设备在信号放大、滤波和转换等领域对高性能组件的需求。该芯片针对高频、低噪声和高线性度等方面进行了优化,是许多音频处理、信号调理和测量系统中不可或缺的组成部分。 CLC007BMX的详细参数 CLC007BMX的主要参数如下: - 电源电压范围:提供单电源或双电源供电,单电源供电范围为4.5V至15V,双电源供电范围为±2.25V至±7.5V。 - 增益带宽积:典型值为25MHz,确保了在高频率信号下的优良性能。 - 增益:可实现非反相增益,最大增益可达75dB,适应多样化的信号放大需求。 - 输入偏置电流:典型值为1nA,低偏置...

产品型号CLC007BMX的Datasheet PDF文件预览

CLC007  
www.ti.com  
SNLS016E JULY 1998REVISED APRIL 2013  
CLC007 Serial Digital Cable Driver with Dual Complementary Outputs  
Check for Samples: CLC007  
1
FEATURES  
DESCRIPTION  
The Texas Instruments Comlinear CLC007 is a  
monolithic, high-speed cable driver designed for the  
SMPTE 259M serial digital video data transmission  
standard. The CLC007 drives 75transmission lines  
(Belden 8281 or equivalent) at data rates up to 400  
Mbps. Controlled output rise and fall times (750 ps  
typical) minimize transition-induced jitter. The output  
voltage swing, typically 1.65V, set by an accurate,  
low-drift internal bandgap reference, delivers an 800  
mV swing to back-matched and terminated 75Ω  
cable.  
2
No External Pull-Down Resistors  
Differential Input and Output  
Low Power Dissipation  
Single +5V or 5.2V Supply  
Replaces GS9007 in Most Applications  
APPLICATIONS  
Digital Routers and Distribution Amplifiers  
Coaxial Cable Driver for Digital Transmission  
Line  
The CLC007’s class AB output stage consumes less  
power than other designs, 195 mW with all outputs  
terminated, and requires no external bias resistors.  
The differential inputs accept a wide range of digital  
signals from 200 mVP-P to ECL levels within the  
specified common-mode limits. All this make the  
CLC007 an excellent general purpose high speed  
driver for digital applications.  
Twisted Pair Driver  
Digital Distribution Amplifiers  
SMPTE, Sonet/SDH, and ATM Compatible  
Driver  
Buffer Applications  
KEY SPECIFICATION  
The CLC007 is powered from a single +5V or 5.2V  
supply and comes in an 8-pin SOIC package.  
650 ps Rise and Fall Times  
Data Rates to 400 Mbps  
2 Sets of Complimentary Outputs  
200 mV Differential Input  
Low Residual Jitter (25 pspp)  
270 Mbps Eye Pattern  
Connection Diagram  
Q0  
Q0  
Q1  
Q1  
1
2
3
4
8
7
6
5
V
CC  
V
IN+  
V
IN-  
V
EE  
0
1
2
3
4
5
6
TIME (1 ns/Div)  
Figure 2. 8-Pin SOIC  
See D Package  
Figure 1.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1998–2013, Texas Instruments Incorporated  
CLC007  
SNLS016E JULY 1998REVISED APRIL 2013  
www.ti.com  
Typical Application  
V
CC  
75W Coax  
75W Coax  
75W Coax  
75W Coax  
0.1 mF  
0.1 mF  
0.1 mF  
0.1 mF  
75W  
75W  
75W  
75W  
80.6W  
80.6W  
75W  
75W  
75W  
75W  
8
7
1
V
+
IN+  
2
3
CLC007  
6
-
V
IN-  
4
5
133W  
133W  
V
EE  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
(1)(2)  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage  
6V  
30 mA  
Output Current  
Maximum Junction Temperature  
Storage Temperature Range  
Lead Temperature (Soldering 10 Second)  
ESD Rating (Human body Model)  
Package Thermal Resistance  
+125°C  
65°C to +150°C  
+300°C  
1000V  
θJA 8–pin SOIC  
θJC 8–pin SOIC  
MTTF  
+160°C  
+105°C/W  
254 Mhr  
Reliability Information  
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that  
the devices should be operated at these limits. The table of ELECTRICAL CHARACTERISTICS specifies conditions of device operation.  
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and  
specifications.  
RECOMMENDED OPERATING CONDITIONS  
Supply Voltage (VCC – VEE  
)
+4.5V to +5.5V  
2
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Copyright © 1998–2013, Texas Instruments Incorporated  
Product Folder Links: CLC007  
CLC007  
www.ti.com  
SNLS016E JULY 1998REVISED APRIL 2013  
ELECTRICAL CHARACTERISTICS  
(VCC = 0V, VEE = 5V; unless otherwise specified).  
Min/Max  
0°C  
to+70°C  
Min/Max  
40°C to  
+85°C  
Min/Max  
+25°C  
Parameter  
Conditions  
Typ +25°C  
Units  
STATIC PERFORMANCE  
Supply Current, Loaded  
Supply Current, Unloaded  
Output HIGH Voltage (VOH  
(1)  
(2)  
(2)  
(2)  
See  
See  
See  
See  
39  
34  
28/45  
2.0/1.4  
3.6/3.0  
30  
26/47  
2.0/1.4  
3.6/3.0  
50  
26/47  
2.0/1.4  
3.6/3.0  
50  
mA  
mA  
V
)
1.7  
3.3  
10  
Output Low Voltage (VOL  
Input Bias Current  
Output Swing  
)
V
μA  
V
(2)  
See  
1.65  
0.7  
2.6  
200  
26  
1.55/1.75  
0.8  
1.53/1.77  
0.8  
1.51/1.79  
0.8  
Common Mode Input Range Upper Limit  
Common Mode Input Range Lower Limit  
Minimum Differential Input Swing  
V
2.5  
2.5  
2.5  
V
200  
200  
200  
mV  
dB  
(2)  
Power Supply Rejection Ratio  
20  
20  
20  
AC PERFORMANCE  
Output Rise and Fall Time  
Overshoot  
(1)(2)(3)  
See  
650  
5
425/955  
400/1100  
400/1100  
ps  
%
Propagation Delay  
1.0  
50  
25  
ns  
Duty Cycle Distortion  
Residual Jitter  
ps  
pspp  
MISCELLANEOUS PERFORMANCE  
Input Capacitance  
1.0  
10  
6
pF  
Output Resistance  
Output Inductance  
nH  
(1) Measured with both outputs driving 150, AC coupled at 270 Mbps.  
(2) Spec is 100% tested at +25°C  
(3) Measured between the 20% and 80% levels of the waveform.  
Copyright © 1998–2013, Texas Instruments Incorporated  
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SNLS016E JULY 1998REVISED APRIL 2013  
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OPERATION  
Input Interfacing  
The CLC007 has high impedance, emitter-follower buffered, differential inputs. Single-ended signals may also be  
input. Transmission lines supplying input signals must be properly terminated close to the CLC007. Either A.C. or  
D.C. coupling as in Figure 4 or Figure 5 may be used. Figure 4, Figure 6, and Figure 7 show how Thevenin-  
equivalent resistor networks are used to provide input termination and biasing. The input D.C. common-mode  
voltage range is 0.8V to 2.5V below the positive power supply (VCC). Input signals plus bias should be kept within  
the specified common-mode range. For an 800 mVP-P input signal, typical input bias levels range from 1.2V to  
2.1V below the positive supply.  
Load Type  
Resistor to VCC (R1)  
Resistor to VEE (R2)  
ECL, 50, 5V, VT=2V  
ECL, 50, 5.2V, VT=2V  
ECL, 75, 5V, VT=2V  
ECL, 75, 5.2V, VT=2V  
82.5Ω  
80.6Ω  
124Ω  
121Ω  
75.0Ω  
110Ω  
3240Ω  
124Ω  
133Ω  
187Ω  
196Ω  
154Ω  
232Ω  
6810Ω  
800 mVP-P, 50, 5V, VT=1.6V  
800 mVP-P, 75, 5V, VT=1.6V  
800 mVP-P, 2.2 K, 5V, VT=1.6V  
V
CC  
V
V
IN-  
IN+  
To next  
stage  
V
EE  
Figure 3. Input Stage  
V
V
CC  
CC  
ECL Output  
R1  
0.1 mF  
R1  
Z
0
8
7
6
1
CLC007  
4
+
2
3
V
V
TT  
TT  
-
0.1 mF  
R2  
Z
0
5
R2  
V
EE  
V
EE  
Figure 4. AC Coupled Input  
4
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Copyright © 1998–2013, Texas Instruments Incorporated  
Product Folder Links: CLC007  
 
CLC007  
www.ti.com  
SNLS016E JULY 1998REVISED APRIL 2013  
V
CC  
ECL Output  
Z
0
8
7
6
1
CLC007  
4
+
2
3
-
Z
0
5
= Z  
= Z  
0
0
V
V
EE  
TT  
Figure 5. DC Coupled Input  
V
CC  
R6  
75W  
C1  
0.1 mF  
J3  
J4  
J5  
J6  
R5  
R4  
75W  
75W  
8
R7  
75W  
C2  
0.1 mF  
7
6
4
+
3
2
CLC007  
R8  
75W  
C3  
0.1 mF  
J2  
-
V
1
IN+  
5
R3  
R1  
154W  
154W  
R9  
75W  
C4  
0.1 mF  
V
EE  
Figure 6. Single Ended 50ECL Input  
Copyright © 1998–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
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CLC007  
SNLS016E JULY 1998REVISED APRIL 2013  
www.ti.com  
V
CC  
R6  
75W  
C1  
0.1 mF  
J3  
J4  
J5  
J6  
R5  
R4  
75W  
75W  
8
R7  
75W  
C2  
0.1 mF  
7
6
4
J1  
+
V
3
2
IN-  
CLC007  
R8  
75W  
C3  
0.1 mF  
J2  
-
V
1
IN+  
5
R3  
R1  
154W  
154W  
R9  
75W  
C4  
0.1 mF  
V
EE  
Figure 7. Differential 50ECL Input  
Output Interfacing  
The CLC007’s class AB output stage, Figure 8, requires no standing current in the output transistors and  
therefore requires no biasing or pull-down resistors. Advantages of this arrangement are lower power dissipation  
and fewer external components. The output may be either D.C. or A.C. coupled to the load. A bandgap voltage  
reference sets output voltage levels which are compatible with F100K and 10K ECL when correctly terminated.  
The outputs do not have the same output voltage temperature coefficient as 10K. Therefore, noise margins will  
be reduced over the full temperature range when driving 10K ECL. Noise margins will not be affected when  
interfacing to F100K since F100K is fully voltage and temperature compensated.  
V
CC  
V
EE  
V
CC  
V
EE  
Figure 8. Output Stage  
6
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Copyright © 1998–2013, Texas Instruments Incorporated  
Product Folder Links: CLC007  
 
CLC007  
www.ti.com  
SNLS016E JULY 1998REVISED APRIL 2013  
V
CC  
for 75W input:  
R1 = R3 = 232W  
R4 = R5 = 110W  
R6  
75W  
75W Coax  
J3  
J4  
J5  
J6  
R5  
75W  
R4  
75W  
75W  
75W  
75W  
75W  
8
R7  
75W  
7
6
1
J1  
75W Coax  
75W Coax  
75W Coax  
+
V
2
3
IN+  
CLC007  
R8  
75W  
J2  
-
V
IN-  
4
5
R3  
154W  
R1  
154W  
R9  
75W  
R
= 50W  
IN  
V
= V - 1.62V  
CC  
BIAS  
V
EE  
V
- V = +5V  
EE  
CC  
Figure 9. Differential Input DC Coupled Output  
Copyright © 1998–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
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Product Folder Links: CLC007  
CLC007  
SNLS016E JULY 1998REVISED APRIL 2013  
www.ti.com  
Output Rise And Fall Times  
Output load capacitance can significantly affect output rise and fall times. The effect of load capacitance, stray or  
otherwise, may be reduced by placing the output back-match resistor close to the output pin and by minimizing  
all interconnecting trace lengths. Figure 10 shows the effect on risetime of parallel load capacitance across a  
150load.  
50  
40  
30  
20  
10  
0
500  
1000  
1500  
2000  
2500  
3000  
RISE TIME (ps)  
Figure 10. Rise Time vs CL  
PCB Layout Recommendations  
Printed circuit board layout affects the performance of the CLC007. The following guidelines will aid in achieving  
satisfactory device performance.  
Use a ground plane or power/ground plane sandwich design for optimum performance.  
Bypass device power with a 0.01 µF monolithic ceramic capacitor in parallel with a 6.8 µF tantalum  
electrolytic capacitor located no more than 0.1” (2.5 mm) from the device power pins.  
Provide short, symmetrical ground return paths for:  
Inputs,  
Supply bypass capacitors and  
The output load.  
Provide short, grounded guard traces located  
Under the centerline of the package,  
0.1” (2.5 mm) from the package pins  
On both top and bottom of the board with connecting vias.  
8
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Copyright © 1998–2013, Texas Instruments Incorporated  
Product Folder Links: CLC007  
 
 
CLC007  
www.ti.com  
SNLS016E JULY 1998REVISED APRIL 2013  
REVISION HISTORY  
Changes from Revision D (April 2013) to Revision E  
Page  
Changed layout of National Data Sheet to TI format ............................................................................................................ 8  
Copyright © 1998–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Links: CLC007  
PACKAGE OPTION ADDENDUM  
www.ti.com  
12-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
CLC007BM  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
D
8
8
8
8
95  
TBD  
Call TI  
CU SN  
Call TI  
CU SN  
Call TI  
CLC00  
7BM>D  
CLC007BM/NOPB  
CLC007BMX  
ACTIVE  
ACTIVE  
ACTIVE  
D
D
D
95  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Call TI  
-40 to 85  
CLC00  
7BM>D  
2500  
2500  
TBD  
-40 to 85  
CLC00  
7BM>D  
CLC007BMX/NOPB  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
-40 to 85  
CLC00  
7BM>D  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
12-Apr-2013  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
24-Apr-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CLC007BMX  
SOIC  
SOIC  
D
D
8
8
2500  
2500  
330.0  
330.0  
12.4  
12.4  
6.5  
6.5  
5.4  
5.4  
2.0  
2.0  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
CLC007BMX/NOPB  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
24-Apr-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CLC007BMX  
SOIC  
SOIC  
D
D
8
8
2500  
2500  
349.0  
349.0  
337.0  
337.0  
45.0  
45.0  
CLC007BMX/NOPB  
Pack Materials-Page 2  
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配单直通车
CLC007BMX产品参数
型号:CLC007BMX
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:SOIC
包装说明:SOP,
针数:8
Reach Compliance Code:not_compliant
风险等级:5.74
其他特性:CAN ALSO OPERATE WITH -5.2V SUPPLY
差分输出:YES
驱动器位数:1
输入特性:DIFFERENTIAL
接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSE
JESD-30 代码:R-PDSO-G8
JESD-609代码:e0
长度:4.9 mm
湿度敏感等级:1
标称负供电电压:-5 V
功能数量:1
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):235
最大接收延迟:
座面最大高度:1.75 mm
最大供电电压:5.5 V
最小供电电压:4.5 V
标称供电电压:5 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm
Base Number Matches:1
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