CP2104-F03-GMR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号CP2104-F03-GMR的概述

CP2104-F03-GMR芯片概述 CP2104-F03-GMR是一款由Silicon Labs（硅实验室）生产的USB转串行桥接器。这款芯片是一个高性能的一体化USB接口解决方案，广泛应用于需要USB连接的微控制器（MCU）和其他设备。CP2104提供了完整的USB功能，支持各种波特率设置，使得开发者能够轻松地将传统的串行接口设备与现有的USB架构连接。该芯片以其灵活性、易用性和综合性能，尤其是在快速原型开发及产品设计中，得到了极大的关注。详细参数 CP2104-F03-GMR的主要技术参数如下： - 最大数据传输速率：最高可达1 Mbps - 工作电压范围：2.7V至5.25V - 动态电流消耗：一般为8mA（不包括USB主机供电） - 静态电流消耗：小于1μA（低功耗模式） - 温度范围：工作温度范围为-40°C至+85°C - 封装类型：32-TQFN - 总引脚数：32个...

产品型号CP2104-F03-GMR的Datasheet PDF文件预览

August 22, 2012

CP2104 Errata

Hardware Errata Status Summary

Status

Affected Revisions

Errata #

Title

Impact

Minor

Major

Fixed Revision

USB D+/D- Driver Impedance

UART, GPIO, Suspend Signals

Driven Low After Power Cycling

Revision E

Revision F

Revision A–E

Revision F

Impact Definition: Each erratum is marked with an impact, as defined below:



Minor—Workaround exists.

Major—Errata that do not conform to the data sheet or standard.

Information—The device behavior is not ideal but acceptable. Typically, the data sheet will be

changed to match the device behavior.

Errata Details

H1. USB D+/D- Driver Impedance

Description: The output impedance of the drivers on the USB D+ and D- data lines is nominally 28 

but, in some cases, may be as low as 26 . The minimum USB specification for full-speed devices on

the D+ and D- data lines is 28 .

Impact: This may impact systems that need to be submitted for USB compliance testing. The

specification for USB compliance is a system-level parameter, not a chip-level parameter. In most

systems, the lower impedance of the device will not be a factor. A typical PCB will add 2-3  to the

effective driver impedance and bring the system level impedance within specifications.

Workaround: For systems that require USB certification, it is recommended to add some series

impedance (between 5 and 8 Ohms, ¼ watt or higher) to D+ and D- in the PCB design.

H2. UART, GPIO, Suspend Signals Driven Low after Power Cycling

Description: The UART, GPIO, and suspend signals will be driven low for approximately 40

microseconds after power cycling the device and then return to the configured reset state.

Impact: This may impact systems in which the CP2104 is connected to devices that are powered from a

separate supply and turned on before the CP2104 receives power through the 5 V regulator or through

VDD and VIO pins. The drop of the CP2104 signals may be seen as invalid data by the connected

devices.

Workaround: In systems that are affected by this drop, the CP2104 should be powered through the 5 V

regulator or through the VDD and VIO pins from the same supply used by devices that are connected to

the UART, GPIO, and suspend signals of the CP2104.

400 West Cesar Chavez, Austin, TX 78701 (512) 416-8500 FAX (512) 416-9669 www.silabs.com

CP2104ER082212

Data Sheet Errata Status Summary

The Documentation Errata is applicable to the following document:



CP2104 Data Sheet Revision 1.0

Errata #

Title

Impact

Data Sheet

ROM Programming Voltage

Minor

Issue Exists

Impact Definition: Each erratum is marked with an impact, as defined below:



Minor—Workaround exists.

Major—Errata that do not conform to the data sheet or standard.

Information—The device behavior is not ideal but acceptable. Typically, the data sheet will be

changed to match the device behavior.

Errata Details

D1. ROM Programming Voltage

Description: The data sheet incorrectly indicates that VDD must remain at 3.3 V or higher to

successfully write to the configuration ROM. Instead, the voltage on the VIO pin must remain at 3.3 V or

higher when writing to the configuration ROM.

Impact: For systems that connect VDD and VIO together, there is no impact. For systems that have a

separate voltage source for VIO and are configuring the ROM in-system, VIO must remain at 3.3 V while

programming is in progress.

Resolution: This note will be fixed in the Revision 1.1 of the CP2104 Data Sheet.

400 West Cesar Chavez, Austin, TX 78701 (512) 416-8500 FAX (512) 416-9669 www.silabs.com

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Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included

information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted

hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of

Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal

injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass

destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,

EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,

Gecko®, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon

Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand

names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

http://www.silabs.com

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CP2104-F03-GMR产品参数

型号:	CP2104-F03-GMR
是否Rohs认证：	符合
生命周期：	Not Recommended
Reach Compliance Code：	compliant
HTS代码：	8542.31.00.01
风险等级：	7.91
JESD-30 代码：	S-PQCC-N24
JESD-609代码：	e3
湿度敏感等级：	1
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCN
封装等效代码：	LCC24,.16SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER
电源：	3.3 V
认证状态：	Not Qualified
子类别：	Bus Controllers
最大压摆率：	18.728 mA
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
Base Number Matches：	1

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