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  • CS4340-KSZ图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • CS4340-KSZ 现货库存
  • 数量5580 
  • 厂家 
  • 封装 
  • 批号16+ 
  • 价格及优,真实库存,全新原装正品!!
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  • CS4340-KSZ图
  • 集好芯城

     该会员已使用本站13年以上
  • CS4340-KSZ
  • 数量20457 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号最新批次 
  • 原装原厂 现货现卖
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  • 0755-83239307 QQ:3008092965QQ:3008092965
  • CS4340-KSZ图
  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • CS4340-KSZ
  • 数量5800 
  • 厂家CIRRUS 
  • 封装 
  • 批号2024+ 
  • 全新原装现货,杜绝假货。
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  • CS4340-KSZ图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • CS4340-KSZ
  • 数量19800 
  • 厂家CRYSTRL 
  • 封装SOP-16 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
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  • 0755-82865294 QQ:198857245
  • CS4340-KSZ图
  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • CS4340-KSZ
  • 数量48015 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
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  • CS4340-KSZ图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CS4340-KSZ
  • 数量10000 
  • 厂家 
  • 封装SOP16 
  • 批号2024+ 
  • 原装正品,假一罚十
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  • CS4340-KSZ图
  • 深圳市宇集芯电子有限公司

     该会员已使用本站6年以上
  • CS4340-KSZ
  • 数量99000 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号24+ 
  • 一级代理进口原装现货、假一罚十价格合理
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  • CS4340-KSZ图
  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • CS4340-KSZ
  • 数量8000 
  • 厂家 
  • 封装N/A 
  • 批号2024 
  • 上海原装现货库存,欢迎查询!
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  • 15821228847 QQ:2719079875QQ:2300949663
  • CS4340-KSZR图
  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • CS4340-KSZR
  • 数量26976 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号2018+ 
  • ★★代理原装现货,特价热卖!★★
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  • 0755-25165869 QQ:2752732883QQ:240616963
  • CS4340-KSZ图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CS4340-KSZ
  • 数量22 
  • 厂家CIRRUS 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
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  • 0755-82546830 QQ:3007977934QQ:3007947087
  • CS4340-KSZNARVC图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • CS4340-KSZNARVC
  • 数量5000 
  • 厂家 
  • 封装SOP 
  • 批号16+ 
  • 百分百原装正品,现货库存
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  • 010-62106431 QQ:857273081QQ:1594462451
  • CS4340-KSZ图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CS4340-KSZ
  • 数量21777 
  • 厂家CRYSTAL 
  • 封装SOP3.916P 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
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  • CS4340-KSZ图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CS4340-KSZ
  • 数量13500 
  • 厂家CIRRUS LOGIC 
  • 封装48 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
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  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • CS4340-KSZ图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • CS4340-KSZ
  • 数量2500 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
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  • CS4340-KSZ图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • CS4340-KSZ
  • 数量85000 
  • 厂家CIRRUS 
  • 封装 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
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  • 0755-23605827 QQ:2881495753
  • CS4340-KSZR图
  • 深圳市双微电子科技有限公司

     该会员已使用本站10年以上
  • CS4340-KSZR
  • 数量17596 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号20+ 
  • 询货请加QQ 全新原装 现货库存
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  • CS4340-KSZ图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • CS4340-KSZ
  • 数量11530 
  • 厂家CIRRUS 
  • 封装SOP-8 
  • 批号23+ 
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  • CS4340-KSZ图
  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • CS4340-KSZ
  • 数量5300 
  • 厂家CIRRUS 
  • 封装SOP-16 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
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  • CS4340-KSZ图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • CS4340-KSZ
  • 数量4500 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号25+ 
  • 全新原装公司现货销售
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  • CS4340-KSZ图
  • 深圳市银鑫达科技有限公司

     该会员已使用本站10年以上
  • CS4340-KSZ
  • 数量
  • 厂家28800 
  • 封装一定原装货 
  • 批号Cirrus代理 
  • SOP-16
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  • 0755-82802007 QQ:1229556666QQ:164547788
  • CS4340-KSZ图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • CS4340-KSZ
  • 数量30000 
  • 厂家CRYSTAL 
  • 封装SOP16 
  • 批号24+ 
  • ★★专业IC现货,诚信经营,市场最优价★★
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  • 0755-83222787 QQ:1950791264QQ:2216987084
  • CS4340-KSZR图
  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • CS4340-KSZR
  • 数量8560 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号17+ 
  • 受权代理!全新原装现货特价热卖!
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  • 0755-83238902 QQ:1258645397QQ:876098337
  • CS4340-KSZ图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • CS4340-KSZ
  • 数量16200 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号23+ 
  • 全新原装正品现货低价
  • QQ:2885348339QQ:2885348339 复制
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  • CS4340-KSZ图
  • 深圳市中杰盛科技有限公司

     该会员已使用本站14年以上
  • CS4340-KSZ
  • 数量12000 
  • 厂家Cirrus Logic 
  • 封装原厂原装 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
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  • 0755-22968359 QQ:409801605
  • CS4340-KSZ图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • CS4340-KSZ
  • 数量16000 
  • 厂家CIRRUS 
  • 封装SOP 
  • 批号24+ 
  • 【原装优势★★★绝对有货】 
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  • 0755-22929859 QQ:2643490444
  • CS4340-KSZ图
  • 深圳市恒意法科技有限公司

     该会员已使用本站17年以上
  • CS4340-KSZ
  • 数量9437 
  • 厂家Cirrus Logic Inc. 
  • 封装16-SOIC(0.154,3.90mm 宽) 
  • 批号21+ 
  • 正规渠道/品质保证/原装正品现货
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  • 0755-83247729 QQ:2881514372
  • CS4340-KSZ图
  • 北京力通科信电子有限公司

     该会员已使用本站10年以上
  • CS4340-KSZ
  • 数量20000 
  • 厂家CIRRUS 
  • 封装 
  • 批号07+ 
  • 北京深圳原装现货热卖特价
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  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
  • CS4340-KSZ
  • 数量10000 
  • 厂家CS4340-KS 
  • 封装原装正品 
  • 批号▊ NEW ▊ 
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  • CS4340-KSZ图
  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
  • CS4340-KSZ
  • 数量20000 
  • 厂家CIRRUS 
  • 封装SOP 
  • 批号23+ 
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  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • CS4340-KSZ
  • 数量50000 
  • 厂家CIRRUS 
  • 封装SOP16 
  • 批号24+ 
  • 公司原装现货可含税!假一罚十!
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  • CS4340-KSZ图
  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
  • CS4340-KSZ
  • 数量16680 
  • 厂家CRYSTAL 
  • 封装SOP-16 
  • 批号16+ 
  • 假一赔十★全新原装现货★★特价供应★工厂客户可放款
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产品型号CS4340-KSZ的概述

CS4340-KSZ芯片概述 CS4340-KSZ是一款高性能的数字音频解码器,广泛应用于音频应用领域。其设计旨在满足高保真音频和多媒体系统的需求,尤其适用于音响设备、移动设备以及其它需要数字音频处理的产品。该芯片在声音的解析度、动态范围和噪声控制等方面表现出色,成为音频工程师和设计师青睐的选择。 芯片详细参数 CS4340-KSZ的技术参数涵盖了多于20个关键性指标,包括但不限于: 1. 音频分辨率:支持最高24位音频数据。 2. 采样频率:支持从32kHz到192kHz的广泛采样频率。 3. 总谐波失真(THD):在1kHz下,典型值为0.0025%。 4. 动态范围:具有出色的动态范围,通常超过100dB。 5. 通道数:支持立体声输出(双通道)。 6. 功率供给:工作电压范围为1.8V至5V。 CS4340-KSZ的电源管理设计旨在优化功耗,适合于便携式和低功耗应用,同时提供必...

产品型号CS4340-KSZ的Datasheet PDF文件预览

CS4340  
24-Bit, 96 kHz Stereo D/A Converter for Audio  
ital-to-analog conversion, digital de-emphasis and  
switched capacitor analog filtering. The advantages of this  
architecture include: ideal differential linearity, no distor-  
tion mechanisms due to resistor matching errors, no  
linearity drift over time and temperature and a high toler-  
ance to clock jitter.  
Features  
! 101 dB Dynamic Range  
! -91 dB THD+N  
! +3.0 V or +5.0 V Power Supply  
! Low Clock Jitter Sensitivity  
! Filtered Line-level Outputs  
! On-chip Digital De-emphasis for 32, 44.1 and  
48 kHz  
! 33 mW with 3V Supply  
! Popguard Technology for Control of Clicks  
The CS4340 accepts data at audio sample rates from  
4 kHz to 100 kHz, consumes very little power, and oper-  
ates over a wide power supply range. The features of the  
CS4340 are ideal for DVD players, CD players, set-top box  
and automotive systems.  
®
and Pops  
! Lead-free Packaging Available  
Description  
ORDERING INFORMATION  
CS4340-DSZ 16-pin SOIC, Lead Free, -40 to 85 °C  
CS4340-KS 16-pin SOIC  
CS4340-KSZ 16-pin SOIC, Lead Free, -10 to 70 °C  
CS4340-CZZ 16-pin TSSOP, Lead Free, -10 to 70 °C  
-10 to 70 °C  
The CS4340 is a complete stereo digital-to-analog system  
CDB4340  
Evaluation Board  
including digital interpolation, fourth-order delta-sigma dig-  
I
SCLK/DEM1  
DEM0  
MUTEC  
RST  
External  
Mute Control  
De-emphasis  
Interpolation  
Analog Filter  
Analog Filter  
AOUTL  
AOUTR  
DAC  
∆Σ  
∆Σ  
Filter  
Serial  
Input  
Interface  
LRCK  
Interpolation  
Filter  
DAC  
SDATA  
DIF0 DIF1  
MCLK  
Copyright © Cirrus Logic, Inc. 2005  
JULY '05  
DS297F3  
1
www.cirrus.com  
(All Rights Reserved)  
CS4340  
TABLE OF CONTENTS  
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4  
SPECIFIED OPERATING CONDITIONS .............................................................................................. 4  
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4  
ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ)....................................................................... 5  
ANALOG CHARACTERISTICS (CS4340-DSZ) .................................................................................... 7  
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 8  
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 11  
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK ..................................................... 12  
DC ELECTRICAL CHARACTERISTICS.............................................................................................. 13  
DIGITAL INPUT CHARACTERISTICS ................................................................................................ 13  
DIGITAL INTERFACE SPECIFICATIONS........................................................................................... 13  
2. PIN DESCRIPTION .............................................................................................................................. 14  
3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 15  
4. APPLICATIONS ................................................................................................................................... 16  
4.1 Sample Rate Range/Operational Mode ........................................................................................ 16  
4.2 System Clocking ........................................................................................................................... 16  
4.2.1 Internal Serial Clock Mode ............................................................................................... 16  
4.2.2 External Serial Clock Mode .............................................................................................. 17  
4.3 Digital Interface Format ................................................................................................................. 17  
4.4 De-Emphasis ................................................................................................................................ 18  
4.5 Power-up Sequence .................................................................................................................... 19  
®
4.6 Popguard Transient Control ........................................................................................................ 19  
4.6.1 Power-up .......................................................................................................................... 19  
4.6.2 Power-down ..................................................................................................................... 19  
4.6.3 Discharge Time ................................................................................................................ 19  
4.7 Mute Control ................................................................................................................................. 20  
4.8 Grounding and Power Supply Arrangements ............................................................................... 20  
Contacting Cirrus Logic Support  
For all product questions and inquiries contact a Cirrus Logic Sales Representative.  
To find one nearest you go to www.cirrus.com  
IMPORTANT NOTICE  
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject  
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant  
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale  
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus  
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third  
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,  
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-  
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks  
or service marks of their respective owners.  
2
DS297F3  
CS4340  
5. PARAMETER DEFINITIONS ................................................................................................................21  
6. REFERENCES ......................................................................................................................................22  
7. PACKAGE DIMENSIONS ....................................................................................................................23  
7.1 SOIC ..............................................................................................................................................23  
7.2 TSSOP ..........................................................................................................................................24  
8. PACKAGE THERMAL RESISTANCE .................................................................................................25  
LIST OF FIGURES  
Figure 1. Output Test Load ...........................................................................................................................6  
Figure 2. Maximum Loading..........................................................................................................................6  
Figure 3. Single-Speed Stopband Rejection.................................................................................................9  
Figure 4. Single-Speed Transition Band .......................................................................................................9  
Figure 5. Single-Speed Transition Band (Detail)...........................................................................................9  
Figure 6. Single-Speed Passband Ripple .....................................................................................................9  
Figure 7. Double-Speed Stopband Rejection................................................................................................9  
Figure 8. Double-Speed Transition Band......................................................................................................9  
Figure 9. Double-Speed Transition Band (Detail) .......................................................................................10  
Figure 10. Double-Speed Passband Ripple................................................................................................10  
Figure 11. Serial Input Timing (External SCLK)..........................................................................................11  
Figure 12. Internal Serial Mode Input Timing..............................................................................................12  
Figure 13. Internal Serial Clock Generation................................................................................................12  
Figure 14. Typical Connection Diagram......................................................................................................15  
2
Figure 15. CS4340 Format 0 - I S up to 24-Bit Data ..................................................................................17  
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data ...................................................................17  
Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data.........................................................................18  
Figure 18. CS4340 Format 3 - Right Justified, 16-Bit Data.........................................................................18  
Figure 19. De-Emphasis Curve...................................................................................................................18  
LIST OF TABLES  
Table 1.CS4340 Speed Modes...................................................................................................................16  
Table 2.Single-Speed Mode Standard Frequencies ...................................................................................16  
Table 3.Double-Speed Mode Standard Frequencies..................................................................................16  
Table 4.Internal SCLK/LRCK Ratio.............................................................................................................17  
Table 5.Digital Interface Format - DIF1 and DIF0.......................................................................................17  
Table 6.De-Emphasis Control.....................................................................................................................18  
DS297F3  
3
CS4340  
1. CHARACTERISTICS AND SPECIFICATIONS  
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.  
Typical performance characteristics are derived from measurements taken at T = 25°C.)  
A
SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.)  
Parameters  
Symbol  
Min  
Nom  
Max  
Units  
DC Power Supply  
Nominal 3.3V  
Nominal 5.0V  
VA  
VA  
2.7  
4.75  
3.3  
5.0  
3.6  
5.5  
V
V
Specified Operating Temperature  
(Power Applied)  
-KS/KSZ/CZZ  
-DSZ  
T
-10  
-40  
-
+70  
+85  
°C  
°C  
A
T
A
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation  
beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these  
extremes.)  
Parameters  
Symbol  
Min  
-0.3  
-
Max  
6.0  
Units  
V
DC Power Supply  
Input Current  
VA  
(Note 1)  
I
±10  
mA  
V
in  
Digital Input Voltage  
V
-0.3  
-55  
-65  
VA+0.4  
125  
IND  
Ambient Operating Temperature (power applied)  
Storage Temperature  
T
°C  
A
T
150  
°C  
stg  
Notes: 1. Any pin except supplies.  
4
DS297F3  
CS4340  
ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ) (Test conditions (unless otherwise  
specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load  
R = 10 k, C = 10 pF (see Figure 1).)  
L
L
VA = 5.0 V  
Typ  
VA = 3.0 V  
Typ  
Parameter  
Min  
Max Min  
Max  
Unit  
Single-Speed Mode  
Fs = 48 kHz  
Dynamic Range  
18 to 24-Bit  
(Note 2)  
unweighted  
A-Weighted  
unweighted  
A-Weighted  
93  
96  
-
98  
101  
92  
-
-
-
-
89  
92  
-
94  
97  
92  
95  
-
-
-
-
dB  
dB  
dB  
dB  
16-Bit  
-
95  
-
Total Harmonic Distortion + Noise  
18 to 24-Bit  
(Note 2)  
0 dB  
-20 dB  
-60 dB  
0 dB  
-
-
-
-
-
-
-91  
-78  
-38  
-90  
-72  
-32  
-86  
-
-
-
-
-
-
-94  
-74  
-34  
-91  
-72  
-32  
-89  
dB  
dB  
dB  
dB  
dB  
dB  
-
-
-
-
-
-
-
-
-
-
16-Bit  
-20 dB  
-60 dB  
Double-Speed Mode  
Fs = 96 kHz  
Dynamic Range  
18 to 24-Bit  
(Note 2)  
unweighted  
A-Weighted  
unweighted  
A-Weighted  
93  
96  
-
98  
101  
92  
-
-
-
-
89  
92  
-
94  
97  
92  
95  
-
-
-
-
dB  
dB  
dB  
dB  
16-Bit  
-
95  
-
Total Harmonic Distortion + Noise  
18 to 24-Bit  
(Note 2)  
0 dB  
-20 dB  
-60 dB  
0 dB  
-
-
-
-
-
-
-91  
-78  
-38  
-90  
-72  
-32  
-86  
-
-
-
-
-
-
-94  
-74  
-34  
-91  
-72  
-32  
-89  
dB  
dB  
dB  
dB  
dB  
dB  
-
-
-
-
-
-
-
-
-
-
16-Bit  
-20 dB  
-60 dB  
DS297F3  
5
CS4340  
ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ) (Continued)  
Parameters  
Dynamic Performance for All Modes  
Interchannel Isolation (1 kHz)  
DC Accuracy  
Symbol  
Min  
Typ  
Max  
Units  
-
102  
-
dB  
Interchannel Gain Mismatch  
Gain Drift  
-
-
0.1  
-
-
dB  
±100  
ppm/°C  
Analog Output Characteristics and Specifications  
Full Scale Output Voltage  
0.6•VA 0.7•VA 0.8•VA  
Vpp  
kΩ  
pF  
Output Impedance  
-
-
-
100  
3
-
-
-
Minimum AC-Load Resistance  
Maximum Load Capacitance  
(Note 3)  
(Note 3)  
R
L
C
100  
L
Notes: 2. One-half LSB of triangular PDF dither is added to data.  
3. Refer to Figure 2.  
.
125  
100  
3.3 µF  
+
V
AOUTx  
out  
75  
50  
R
C
L
L
Safe Operating  
Region  
AGND  
25  
2.5  
5
10  
15  
20  
3
Resistive Load -- R (k )  
L
Figure 1. Output Test Load  
Figure 2. Maximum Loading  
6
DS297F3  
CS4340  
ANALOG CHARACTERISTICS (CS4340-DSZ) (Test conditions (unless otherwise specified):  
Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load  
R = 10 k, C = 10 pF (see Figure 1).)  
L
L
VA = 5.0 V  
Typ  
VA = 3.0 V  
Typ  
Parameter  
Min  
Max Min  
Max  
Unit  
Single-Speed Mode  
Fs = 48 kHz  
Dynamic Range  
18 to 24-Bit  
(Note 2)  
unweighted  
A-Weighted  
unweighted  
A-Weighted  
93  
96  
-
98  
101  
92  
-
-
-
-
89  
92  
-
94  
97  
92  
95  
-
-
-
-
dB  
dB  
dB  
dB  
16-Bit  
-
95  
-
Total Harmonic Distortion + Noise  
18 to 24-Bit  
(Note 2)  
0 dB  
-20 dB  
-60 dB  
0 dB  
-
-
-
-
-
-
-91  
-78  
-38  
-90  
-72  
-32  
-86  
-
-
-
-
-
-
-94  
-74  
-34  
-91  
-72  
-32  
-87  
dB  
dB  
dB  
dB  
dB  
dB  
-
-
-
-
-
-
-
-
-
-
16-Bit  
-20 dB  
-60 dB  
Double-Speed Mode  
Fs = 96 kHz  
Dynamic Range  
18 to 24-Bit  
(Note 2)  
unweighted  
A-Weighted  
unweighted  
A-Weighted  
93  
96  
-
98  
101  
92  
-
-
-
-
89  
92  
-
94  
97  
92  
95  
-
-
-
-
dB  
dB  
dB  
dB  
16-Bit  
-
95  
-
Total Harmonic Distortion + Noise  
18 to 24-Bit  
(Note 2)  
0 dB  
-20 dB  
-60 dB  
0 dB  
-
-
-
-
-
-
-91  
-78  
-38  
-90  
-72  
-32  
-86  
-
-
-
-
-
-
-94  
-74  
-34  
-91  
-72  
-32  
-87  
dB  
dB  
dB  
dB  
dB  
dB  
-
-
-
-
-
-
-
-
-
-
16-Bit  
-20 dB  
-60 dB  
DS297F3  
7
CS4340  
ANALOG CHARACTERISTICS (CS4340-DSZ) (Continued)  
Parameters  
Dynamic Performance for All Modes  
Interchannel Isolation (1 kHz)  
DC Accuracy  
Symbol  
Min  
Typ  
Max  
Units  
-
102  
-
dB  
Interchannel Gain Mismatch  
Gain Drift  
-
-
0.1  
-
-
dB  
±100  
ppm/°C  
Analog Output Characteristics and Specifications  
Full Scale Output Voltage  
0.6•VA 0.7•VA 0.8•VA  
Vpp  
kΩ  
pF  
Output Impedance  
-
-
-
100  
3
-
-
-
Minimum AC-Load Resistance  
Maximum Load Capacitance  
(Note 3)  
(Note 3)  
R
L
C
100  
L
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The  
filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be  
referenced to the desired sample rate by multiplying the given characteristic by Fs.)  
Parameter  
Single-Speed Mode - (4 kHz to 50 kHz sample rates)  
Passband  
Min  
Typ  
Max  
Unit  
to -0.05 dB corner  
0
0
-
-
0.4535  
0.4998  
Fs  
Fs  
to -3 dB corner  
Frequency Response 10 Hz to 20 kHz  
StopBand  
-0.02  
-
+0.08  
dB  
Fs  
dB  
s
0.5465  
-
-
-
-
-
StopBand Attenuation  
Group Delay  
(Note 4)  
50  
-
-
9/Fs  
±0.36/Fs  
-
Passband Group Delay Deviation  
0 - 20 kHz  
-
s
De-emphasis Error (Relative to 1 kHz)  
(Note 5)  
Fs = 44.1 kHz  
-
+0.05/-0.14 dB  
Double-Speed Mode - (50 kHz to 100 kHz sample rates)  
Passband  
to -0.1 dB corner  
to -3 dB corner  
0
0
-
-
0.4621  
0.4982  
Fs  
Fs  
Frequency Response 10 Hz to 20 kHz  
StopBand  
-0.06  
0.577  
55  
-
+0.2  
dB  
Fs  
dB  
s
-
-
-
-
-
StopBand Attenuation  
Group Delay  
(Note 4)  
-
4/Fs  
Passband Group Delay Deviation  
0 - 40 kHz  
0 - 20 kHz  
-
-
±1.39/Fs  
±0.23/Fs  
-
-
s
s
Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.  
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.  
5. De-emphasis is only available in Single-Speed Mode.  
8
DS297F3  
CS4340  
Figure 3. Single-Speed Stopband Rejection  
Figure 4. Single-Speed Transition Band  
Figure 5. Single-Speed Transition Band (Detail)  
Figure 6. Single-Speed Passband Ripple  
Figure 7. Double-Speed Stopband Rejection  
DS297F3  
Figure 8. Double-Speed Transition Band  
9
CS4340  
Figure 9. Double-Speed Transition Band (Detail)  
Figure 10. Double-Speed Passband Ripple  
10  
DS297F3  
CS4340  
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE  
Parameters  
Symbol  
Min  
1.024  
45  
Max  
25.6  
55  
Units  
MHz  
%
MCLK Frequency  
MCLK Duty Cycle  
Input Sample Rate  
Single-Speed Mode  
Double-Speed Mode  
Fs  
Fs  
4
50  
50  
100  
kHz  
kHz  
LRCK Duty Cycle  
40  
20  
20  
60  
-
%
ns  
ns  
SCLK Pulse Width Low  
SCLK Pulse Width High  
SCLK Frequency  
t
sclkl  
t
-
sclkh  
Single-Speed Mode  
Double-Speed Mode  
-
-
128xFs  
64xFs  
Hz  
Hz  
SCLK rising to LRCK edge delay  
SCLK rising to LRCK edge setup time  
SDIN valid to SCLK rising setup time  
SCLK rising to SDIN hold time  
t
20  
20  
20  
20  
-
-
-
-
ns  
ns  
ns  
ns  
slrd  
t
slrs  
t
sdlrs  
t
sdh  
LRCK  
t
t
sclkh  
slrs  
t
slrd  
t
sclkl  
SCLK  
t
t
sdh  
sdlrs  
SDATA  
Figure 11. Serial Input Timing (External SCLK)  
DS297F3  
11  
CS4340  
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK  
Parameters  
Symbol  
Min  
1.024  
45  
Typ  
Max  
25.6  
55  
Units  
MHz  
%
MCLK Frequency  
MCLK Duty Cycle  
Input Sample Rate  
-
-
Single-Speed Mode  
Double-Speed Mode  
Fs  
Fs  
4
50  
-
-
50  
100  
kHz  
kHz  
(Note 6)  
LRCK Duty Cycle  
SCLK Period  
%
s
(Note 7)  
t
1
-
-
sclkw  
----------------  
SCLK  
SCLK rising to LRCK edge  
tsclkw  
-------------  
2
t
-
-
-
-
-
s
sclkr  
SDATA valid to SCLK rising setup time  
SCLK rising to SDATA hold time  
t
-
-
-
ns  
ns  
ns  
1
sdlrs  
--------------------- + 10  
(512)Fs  
t
1
sdh  
sdh  
--------------------- + 15  
MCLK / LRCK = 512, 256 or 128  
(512)Fs  
SCLK rising to SDATA hold time  
t
1
--------------------- + 15  
MCLK / LRCK = 384 or 192  
(384)Fs  
Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.  
7. See section 4.2.1 for derived internal frequencies.  
LRCK  
t
sclkr  
SDATA  
t
sclkw  
t
t
sdh  
sdlrs  
*INTERNAL SCLK  
Figure 12. Internal Serial Mode Input Timing  
*The SCLK pulses shown are internal to the CS4340.  
LRCK  
MCLK  
N
2
N
1
*INTERNAL SCLK  
SDATA  
Figure 13. Internal Serial Clock Generation  
* The SCLK pulses shown are internal to the CS4340. N equals MCLK divided by SCLK  
12  
DS297F3  
CS4340  
DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)  
Parameters  
Symbol  
Min  
Typ  
Max  
Units  
Normal Operation (Note 8)  
Power Supply Current  
Power Dissipation  
VA = 5.0 V  
VA = 3.0 V  
I
I
-
-
15  
11  
18  
14  
mA  
mA  
A
A
VA = 5.0 V  
VA = 3.0 V  
-
-
75  
33  
90  
42  
mW  
mW  
Power-down Mode (Note 9)  
Power Supply Current  
VA = 5.0 V  
VA = 3.0 V  
I
-
-
60  
30  
-
-
µA  
µA  
A
Power Dissipation  
VA = 5.0 V  
VA = 3.0 V  
-
-
0.3  
0.09  
-
-
mW  
mW  
All Modes of Operation  
Power Supply Rejection Ratio (Note 10)  
1 kHz PSRR  
60 Hz  
-
-
60  
40  
-
-
dB  
dB  
V Nominal Voltage  
-
-
-
0.45•VA  
250  
0.01  
-
-
-
V
kΩ  
mA  
Q
Output Impedance  
Maximum allowable DC current source/sink  
Filt+ Nominal Voltage  
-
-
-
VA  
250  
0.01  
-
-
-
V
kΩ  
mA  
Output Impedance  
Maximum allowable DC current source/sink  
MUTEC Low-Level Output Voltage  
MUTEC High-Level Output Voltage  
Maximum MUTEC Drive Current  
-
-
-
0
VA  
3
-
-
-
V
V
mA  
Notes: 8. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for  
each speed mode, and open outputs, unless otherwise specified.  
9. Power Down Mode is defined as RST = LO with all clocks and data lines held static.  
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 14. Increasing the  
capacitance will also increase the PSRR.  
DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)  
Parameters  
Symbol  
Min  
Typ  
Max  
±10  
-
Units  
µA  
Input Leakage Current  
Input Capacitance  
I
-
-
-
in  
8
pF  
DIGITAL INTERFACE SPECIFICATIONS (AGND = 0 V; all voltages with respect to AGND.)  
Parameters  
3.3 V Logic (3.0 V to 3.6 V DC Supply)  
High-Level Input Voltage  
Symbol  
Min  
Max  
Units  
-
V
2.0  
-
V
V
IH  
Low-Level Input Voltage  
V
0.8  
IL  
5.0 V Logic (4.75 V to 5.25 V DC Supply)  
High-Level Input Voltage  
V
2.0  
-
-
V
V
IH  
Low-Level Input Voltage  
V
0.8  
IL  
DS297F3  
13  
CS4340  
2. PIN DESCRIPTION  
RST  
SDATA  
SCLK/DEM1  
LRCK  
MUTEC  
AOUTL  
VA  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
AGND  
AOUTR  
REF_GND  
VQ  
MCLK  
DIF1  
DIF0  
DEM0  
FILT+  
Pin Name  
RST  
#
Pin Description  
Reset (Input) - Powers down device.  
1
2
3
SDATA  
SCLK  
Serial Audio Data (Input) - Input for two’s complement serial audio data.  
Serial Clock (Input) -Serial clock for the serial audio interface.  
DEM1  
DEM0  
De-emphasis Control (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter  
response for 44.1 kHz sample rate.  
3
8
LRCK  
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the  
serial audio data line.  
4
MCLK  
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.  
5
DIF1  
DIF0  
Digital Interface Format (Input) - Defines the required relationship between the Left Right  
Clock, Serial Clock and Serial Audio Data.  
6
7
FILT+  
Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir-  
cuits.  
9
VQ  
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.  
Reference Ground (Input) - Ground reference for the internal sampling circuits.  
10  
11  
REF_GND  
AOUTR  
AOUTL  
Analog Outputs (Output) - The full scale analog output level is specified in the Analog Charac-  
teristics table.  
12  
15  
AGND  
VA  
Analog Ground (Input)  
13  
14 Power (Input) - Positive power for the analog, digital and serial audio interface sections.  
Mute Control (Output) - Control signal for an optional mute circuit.  
MUTEC  
16  
14  
DS297F3  
CS4340  
3. TYPICAL CONNECTION DIAGRAM  
+3.0 V to +5.0 V  
+
0.1 µF  
14  
1 µF  
VA  
2
SDATA  
3.3 µF  
560  
Left  
Audio  
Output  
Serial Audio  
Data  
Processor  
3
4
15  
16  
SCLK/DEM1  
LRCK  
AOUTL  
+
C
R
10 k  
L
CS4340  
OPTIONAL  
MUTE  
CIRCUIT  
MUTEC  
FILT+  
VQ  
5
MCLK  
External Clock  
9
+
10  
0.1 µF 1 µF  
.1 µF  
1 µF  
+
11  
12  
6
7
8
1
DIF1  
DIF0  
DEM0  
RST  
REF_GND  
AOUTR  
3.3 µF  
560  
Mode  
Configuration  
Right  
Audio  
Output  
+
10 kΩ  
C
R
L
AGND  
13  
RL + 560  
C =  
4πFSRL 560  
Figure 14. Typical Connection Diagram  
DS297F3  
15  
CS4340  
4. APPLICATIONS  
4.1 Sample Rate Range/Operational Mode  
The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock ratio (see  
section 4.2). Sample rates outside the specified range for each mode are not supported.  
Input Sample Rate (Fs)  
4 kHz - 50 kHz  
MODE  
Single-Speed Mode  
50 kHz - 100 kHz  
Double-Speed Mode  
Table 1. CS4340 Speed Modes  
4.2 System Clocking  
The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device also requires  
external generation of the serial clock (SCLK) if the internal serial clock is not used. The LRCK, defined also as the  
input sample rate Fs, must be synchronously derived from MCLK according to specified ratios. The specified ratios  
of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated  
in Tables 2 and 3.  
Sample Rate  
(kHz)  
MCLK (MHz)  
384x  
256x  
512x  
32  
44.1  
48  
8.1920  
11.2896  
12.2880  
12.2880  
16.9344  
18.4320  
16.3840  
22.5792  
24.5760  
Table 2. Single-Speed Mode Standard Frequencies  
Sample Rate  
(kHz)  
MCLK (MHz)  
128x  
192x  
64  
88.2  
96  
8.1920  
11.2896  
12.2880  
12.2880  
16.9344  
18.4320  
Table 3. Double-Speed Mode Standard Frequencies  
4.2.1 Internal Serial Clock Mode  
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin  
for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and synchronous with MCLK  
and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon the MCLK/LRCK ratio and the Digital  
Interface Format selection (see Table 4).  
16  
DS297F3  
CS4340  
The internal serial clock is utilized when additional de-emphasis control is required. Operation in the Internal  
Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External  
SCLK mode is recommended for system clocking applications.  
Digital Interface Format Selection  
Internal  
Input  
I2S up to 24  
Bits  
Left Justified 24 Right Justified  
Right Justified SCLK/LRCK  
MCLK/LRCK  
Ratio  
Bits  
24 Bits  
16 Bits  
Ratio  
X
X
-
-
-
X
X
-
32  
512, 256, 128  
384, 192  
X
X
X
48  
X
64  
512, 256, 128  
Table 4. Internal SCLK/LRCK Ratio  
4.2.2 External Serial Clock Mode  
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the  
SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low  
to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.  
4.3 Digital Interface Format  
The device will accept audio samples in several digital interface formats as illustrated in Table 5. The desired format  
is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between LRCK, SCLK and  
SDIN, see Figures 15 through 18.  
DIF1 DIF0  
DESCRIPTION  
I2S, up to 24-bit data  
Left Justified, up to 24-bit data  
Right Justified, 24-bit Data  
Right Justified, 16-bit Data  
FORMAT  
FIGURE  
15  
0
0
1
1
0
1
0
1
0
1
2
3
16  
17  
18  
Table 5. Digital Interface Format - DIF1 and DIF0  
Left Channel  
Right Channel  
LRCK  
SCLK  
LSB  
MSB  
MSB  
LSB  
+5 +4 +3 +2 +1  
SDIN  
+5 +4 +3 +2 +1  
-1 -2 -3 -4 -5  
-1 -2 -3 -4  
2
Figure 15. CS4340 Format 0 - I S up to 24-Bit Data  
Left Channel  
Right Channel  
LRCK  
SCLK  
LSB  
MSB  
LSB  
SDIN  
+5 +4 +3 +2 +1  
MSB  
+5 +4 +3 +2 +1  
-1 -2 -3 -4 -5  
-1 -2 -3 -4  
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data  
DS297F3  
17  
CS4340  
Right Channel  
LRCK  
SCLK  
Left Channel  
SDIN  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
23 22 21 20 19 18  
23 22 21 20 19 18  
Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data  
32 clocks  
Right Channel  
LRCK  
SCLK  
Left Channel  
SDIN  
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10  
15 14 13 12 11 10  
Figure 18. CS4340 Format 3 - Right Justified, 16-Bit Data  
32 clocks  
4.4 De-Emphasis  
The device includes on-chip digital de-emphasis. Figure 19 shows the de-emphasis curve for Fs equal to 44.1 kHz.  
The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.  
Pin 8 is available for de-emphasis control and selects the 44.1 kHz de-emphasis filter. If the Internal Serial Clock is  
used, pin 3 is also available for additional de-emphasis control and, in combination with pin 8, selects either the 32,  
44.1, or 48 kHz de-emphasis filter. Please see Table 6 for the desired de-emphasis control.  
Gain  
dB  
External SCLK  
Internal SCLK  
DEM1 DEM0 Description  
T1=50 µs  
DEM0 Description  
0dB  
0
0
1
1
0
1
0
1
Disabled  
44.1 kHz  
48 kHz  
0
1
Disabled  
44.1 kHz  
T2 = 15 µs  
Frequency  
-10dB  
32 kHz  
Table 6. De-Emphasis Control  
F1  
3.183 kHz  
F2  
10.61 kHz  
Figure 19. De-Emphasis Curve  
18  
DS297F3  
CS4340  
4.5  
Power-up Sequence  
Reliable power-up can be accomplished by keeping the device in reset until the power supply and configuration pins  
are stable, and the clocks are locked to the appropriate frequencies discussed in section 4.2. It is also recommended  
that reset be enabled if the analog supply drops below the minimum specified operating voltage to prevent power  
glitch related issues.  
®
4.6 Popguard Transient Control  
®
The CS4340 uses Popguard technology to minimize the effects of output transients during power-up and power-  
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes  
the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC  
when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-  
blocking capacitors.  
4.6.1 Power-up  
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Fol-  
lowing a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent volt-  
age. Approximately 10,000 LRCK cycles later, the outputs reach V and audio output begins. This gradual  
Q
voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, min-  
imizing the power-up transient.  
4.6.2 Power-down  
To prevent transients at power-down, the device must first enter its power-down state by enabling RST. When  
this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR.  
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-  
charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for  
the next power-on.  
4.6.3 Discharge Time  
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors  
have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur  
when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-  
down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the  
minimum power-down time will be approximately 0.4 seconds.  
DS297F3  
19  
CS4340  
4.7 Mute Control  
The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The  
pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and  
right channels. A single sample of non-zero data on either channel will cause the Mute Control pin to go low. This  
pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in  
any single-ended single supply system.  
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in  
extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle  
channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340 data sheet  
for a suggested mute circuit.  
4.8 Grounding and Power Supply Arrangements  
As with any high resolution converter, the CS4340 requires careful attention to power supply and grounding arrange-  
ments if its potential performance is to be realized. Figure 14 shows the recommended power arrangements, with  
VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND  
& AGND should be connected to the analog ground plane.  
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the  
closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC.  
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling  
into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to mini-  
mize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on  
the same layer as the DAC. The CDB4340 evaluation board demonstrates the optimum layout and power supply  
arrangements.  
20  
DS297F3  
CS4340  
5. PARAMETER DEFINITIONS  
Total Harmonic Distortion + Noise (THD+N)  
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's  
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in  
decibels.  
Dynamic Range  
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the  
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth  
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement  
to full scale. This technique ensures that the distortion components are below the noise level and do not  
effect the measurement. This measurement technique has been accepted by the Audio Engineering  
Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.  
Interchannel Isolation  
A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s  
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in  
decibels.  
Interchannel Gain Mismatch  
The gain difference between left and right channels. Units in decibels.  
Gain Error  
The deviation from the nominal full scale analog output for a full scale digital input.  
Gain Drift  
The change in gain value with temperature. Units in ppm/°C.  
DS297F3  
21  
CS4340  
6. REFERENCES  
1) CDB4340 Evaluation Board Datasheet  
22  
DS297F3  
CS4340  
7. PACKAGE DIMENSIONS  
7.1 SOIC  
16L SOIC (150 MIL BODY) PACKAGE DRAWING  
E
H
1
b
c
D
SEATING  
PLANE  
A
L
e
A1  
INCHES  
NOM  
0.064  
0.006  
0.016  
0.008  
0.390  
0.154  
0.050  
0.236  
0.025  
4°  
MILLIMETERS  
NOM  
1.63  
DIM  
MIN  
MAX  
0.069  
0.010  
0.020  
0.010  
0.394  
0.157  
0.060  
0.244  
0.050  
8°  
MIN  
1.35  
0.10  
0.33  
0.19  
9.80  
3.80  
1.02  
5.80  
0.40  
0°  
MAX  
1.75  
0.25  
0.51  
0.25  
10.00  
4.00  
1.52  
6.20  
1.27  
8°  
A
A1  
b
C
D
E
e
H
L
0.053  
0.004  
0.013  
0.0075  
0.386  
0.150  
0.040  
0.228  
0.016  
0°  
0.15  
0.41  
0.20  
9.91  
3.90  
1.27  
6.0  
0.64  
4°  
JEDEC #: MS-012  
Controling Dimension is Millimeters  
DS297F3  
23  
CS4340  
7.2 TSSOP  
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING  
N
D
E11  
A2  
A
E
A1  
b2  
e
L
END VIEW  
SEATING  
PLANE  
SIDE VIEW  
1
2 3  
TOP VIEW  
NOTE  
INCHES  
NOM  
--  
0.004  
0.0354  
0.0096  
0.1969  
0.2519  
0.1732  
0.026 BSC  
0.024  
MILLIMETERS  
DIM  
A
A1  
A2  
b
D
E
E1  
e
MIN  
MAX  
0.043  
0.006  
0.037  
0.012  
0.201  
0.256  
0.177  
--  
MIN  
--  
NOM  
--  
--  
MAX  
--  
0.002  
0.03346  
0.00748  
0.193  
0.248  
0.169  
--  
1.10  
0.15  
0.95  
0.30  
5.10  
6.50  
4.50  
--  
0.05  
0.85  
0.19  
4.90  
6.30  
4.30  
--  
0.90  
0.245  
5.00  
6.40  
4.40  
0.065 BSC  
0.60  
4°  
2,3  
1
1
L
0.020  
0°  
0.028  
8°  
0.50  
0°  
0.70  
8°  
4°  
JEDEC #: MO-153  
Controlling Dimension is Millimeters  
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold  
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per  
side.  
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be  
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not  
reduce dimension “b” by more than 0.07 mm at least material condition.  
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.  
24  
DS297F3  
CS4340  
8. PACKAGE THERMAL RESISTANCE  
Package  
Symbol  
Min  
Typ  
Max  
Units  
SOIC  
TSSOP  
(for multi-layer boards)  
(for multi-layer boards)  
θ
θ
-
-
74  
89  
-
-
°C/Watt  
°C/Watt  
JA  
JA  
DS297F3  
25  
配单直通车
CS4340-KSZ产品参数
型号:CS4340-KSZ
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Obsolete
零件包装代码:SOIC
包装说明:SOP, SOP16,.25
针数:16
Reach Compliance Code:compliant
风险等级:5.69
Is Samacsys:N
最大模拟输出电压:2.88 V
最小模拟输出电压:1.62 V
转换器类型:D/A CONVERTER
输入位码:2'S COMPLEMENT
输入格式:SERIAL
JESD-30 代码:R-PDSO-G16
JESD-609代码:e3
长度:9.91 mm
湿度敏感等级:3
位数:24
功能数量:1
端子数量:16
最高工作温度:70 °C
最低工作温度:-10 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP16,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260
电源:3.3/5 V
认证状态:Not Qualified
座面最大高度:1.75 mm
子类别:Other Converters
最大压摆率:18 mA
标称供电电压:3 V
表面贴装:YES
技术:BIPOLAR
温度等级:COMMERCIAL
端子面层:MATTE TIN
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:40
宽度:3.9 mm
Base Number Matches:1
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