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CS4351

192 kHz Stereo DAC with 2 Vrms Line Out

Features

Description

! Multi-Bit Delta-Sigma Modulator

! 24-Bit Conversion

The CS4351 is a complete stereo digital-to-analog sys-

tem including digital interpolation, fifth-order multi-bit

delta-sigma digital-to-analog conversion, digital de-em-

phasis, volume control, channel mixing, analog filtering,

and on-chip 2 Vrms line-level driver. The advantages of

this architecture include ideal differential linearity, no

distortion mechanisms due to resistor matching errors,

no linearity drift over time and temperature, high toler-

ance to clock jitter, and a minimal set of external

components.

! Up to 192 kHz Sample Rates

! 112 dB Dynamic Range

! -100 dB THD+N

! +3.3 V, +9 to 12 V, and VL Power Supplies

! 2 Vrms Output into 5 kΩ AC Load

! Digital Volume Control with Soft Ramp

The CS4351 is available in a 20-pin TSSOP package in

both Commercial (-10°C - +70°C) and Automotive

grades (-40°C to +85°C). The CDB4351 Customer

Demonstration board is also available for device evalu-

ation and implementation suggestions. Please see

“Ordering Information” on page 37 for complete details.

–

119 dB Attenuation

1/2 dB Step Size

Zero Crossing Click-Free Transitions

! ATAPI Mixing

These features are ideal for cost-sensitive, 2-channel

audio systems including DVD players, A/V receivers,

set-top boxes, digital TVs and VCRs, mini-component

systems, and mixing consoles.

! Low Clock Jitter Sensitivity

! Popguard^®Technology for Control of Clicks

and Pops

9 V to 12 V

8V to 3.3V

3.3 V

dware or I²C/ SPI

Cont r ol Dat a

Register/Hardware

Configuration

Reset

Multibit

∆Σ Modulator

Amp

+

Interpolation

Fi l t er wi t h

Volume Control

2 Vrms Line Level

DAC

Left Channel Outpu

Filter

PCM

Serial

erial Audio Input

Interface

Interpolation

Fi l t er wi t h

Volume Control

2 Vrms Line Level

Right Channel

Output

Amp

+

Filter

Multibit

∆Σ Modulator

DAC

Auto Speed Mode

Detect

Ext er nal

Mute

Cont r ol

Left and Right

Mute Controls

Internal Voltage

Reference

DECEMBER '05

DS566F1

http://www.cirrus.com

CS4351

TABLE OF CONTENTS

1. PIN DESCRIPTION ............................................................................................................................... 5

2. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6

SPECIFIED OPERATING CONDITIONS.............................................................................................. 6

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6

DAC ANALOG CHARACTERISTICS .................................................................................................... 7

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ....................................... 8

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ....................................... 9

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ...................................................... 10

®

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT........................................... 11

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT......................................... 12

DIGITAL CHARACTERISTICS............................................................................................................ 13

POWER AND THERMAL CHARACTERISTICS ................................................................................. 13

3. TYPICAL CONNECTION DIAGRAM .................................................................................................. 14

4. APPLICATIONS .................................................................................................................................. 15

4.1 Sample Rate Range/Operational Mode Detect ............................................................................ 15

4.1.1 Auto-Detect Enabled ........................................................................................................ 15

4.1.2 Auto-Detect Disabled ....................................................................................................... 15

4.2 System Clocking ........................................................................................................................... 15

4.3 Digital Interface Format ................................................................................................................ 16

4.3.1 Stand-Alone Mode ........................................................................................................... 16

4.3.2 Control Port Mode ........................................................................................................... 16

4.4 De-Emphasis Control ................................................................................................................... 17

4.4.1 Stand-Alone Mode ........................................................................................................... 18

4.4.2 Control Port Mode ............................................................................................................ 18

4.5 Recommended Power-Up Sequence ........................................................................................... 18

4.5.1 Stand-Alone Mode ........................................................................................................... 18

4.5.2 Control Port Mode ............................................................................................................ 18

®

4.6 Popguard Transient Control ....................................................................................................... 18

4.6.1 Power-Up ......................................................................................................................... 18

4.6.2 Power-Down .................................................................................................................... 19

4.6.3 Discharge Time ................................................................................................................ 19

4.7 Mute Control ................................................................................................................................. 19

4.8 Grounding and Power Supply Arrangements ............................................................................... 19

4.8.1 Capacitor Placement ........................................................................................................ 19

4.9 Control Port Interface ................................................................................................................... 20

4.9.1 MAP Auto Increment ........................................................................................................ 20

4.9.2 I²C Mode .......................................................................................................................... 20

4.9.3 SPI Mode ......................................................................................................................... 21

4.10 Memory Address Pointer (MAP) ................................................................................................. 22

4.10.1 INCR (Auto Map Increment Enable) .............................................................................. 22

4.10.2 MAP (Memory Address Pointer) .................................................................................... 22

5. REGISTER QUICK REFERENCE ....................................................................................................... 23

6. REGISTER DESCRIPTION ................................................................................................................. 24

6.1 Chip ID - Register 01h .................................................................................................................. 24

6.2 Mode Control 1 - Register 02h ..................................................................................................... 24

6.2.1 Digital Interface Format (DIF2:0) Bits 6-4 ........................................................................ 24

6.2.2 De-Emphasis Control (DEM1:0) Bits 3-2. ........................................................................ 24

6.2.3 Functional Mode (FM) Bits 1-0 ......................................................................................... 25

6.3 Volume Mixing and Inversion Control - Register 03h ................................................................... 25

6.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ............................................... 25

6.3.2 Invert Signal Polarity (Invert_A) Bit 6 ............................................................................... 25

6.3.3 Invert Signal Polarity (Invert_B) Bit 5 ............................................................................... 25

2

DS566F1

CS4351

6.3.4 ATAPI Channel Mixing and Muting (ATAPI3:0) Bits 3-0 .................................................. 26

6.4 Mute Control - Register 04h ........................................................................................................ 27

6.4.1 Auto-Mute (AMUTE) Bit 7 ................................................................................................ 27

6.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 ...................................................................... 27

6.4.3 A Channel Mute (MUTE_A) Bit 4

B Channel Mute (MUTE_B) Bit 3 .................................................................................... 27

6.5 Channel A Volume Control - Register 05h

Channel B Volume Control - Register 06h ................................................................................ 27

6.5.1 Digital Volume Control (VOL7:0) Bits 7-0 ........................................................................ 28

6.6 Ramp and Filter Control - Register 07h ........................................................................................ 28

6.6.1 Soft Ramp and Zero Cross Control (SZC1:0) Bits 7-6 ..................................................... 28

6.6.2 Soft Volume Ramp-Up After Error (RMP_UP) Bit 5 ......................................................... 29

6.6.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4 ....................................... 29

6.6.4 Interpolation Filter Select (FILT_SEL) Bit 2 ..................................................................... 29

6.7 Misc Control - Register 08h .......................................................................................................... 29

6.7.1 Power Down (PDN) Bit 7 ................................................................................................. 30

6.7.2 Control Port Enable (CPEN) Bit 6 .................................................................................... 30

6.7.3 Freeze Controls (Freeze) Bit 5 ......................................................................................... 30

7. DIGITAL FILTER RESPONSE PLOTS ............................................................................................. 31

8. PARAMETER DEFINITIONS ............................................................................................................... 35

9. PACKAGE DIMENSIONS .................................................................................................................. 36

10. ORDERING INFORMATION ............................................................................................................. 37

11. REVISION HISTORY ......................................................................................................................... 37

LIST OF FIGURES

Figure 1. Serial Input Timing..................................................................................................................... 10

Figure 2. Control Port Timing - I²C Format................................................................................................ 11

Figure 3. Control Port Timing - SPI Format (Write)................................................................................... 12

Figure 4. Typical Connection Diagram...................................................................................................... 14

Figure 5. Left-Justified up to 24-Bit Data................................................................................................... 17

Figure 6. I²S, up to 24-Bit Data ................................................................................................................. 17

Figure 7. Right-Justified Data.................................................................................................................... 17

Figure 8. De-Emphasis Curve................................................................................................................... 17

Figure 9. Control Port Timing, I²C Mode ................................................................................................... 21

Figure 10.Control Port Timing, SPI mode .................................................................................................. 22

Figure 11.De-Emphasis Curve................................................................................................................... 24

Figure 12.ATAPI Block Diagram ................................................................................................................ 26

Figure 13.Single-Speed (fast) Stopband Rejection.................................................................................... 31

Figure 14.Single-Speed (fast) Transition Band.......................................................................................... 31

Figure 15.Single-Speed (fast) Transition Band (detail).............................................................................. 31

Figure 16.Single-Speed (fast) Passband Ripple........................................................................................ 31

Figure 17.Single-Speed (slow) Stopband Rejection .................................................................................. 31

Figure 18.Single-Speed (slow) Transition Band......................................................................................... 31

Figure 19.Single-Speed (slow) Transition Band (detail)............................................................................. 32

Figure 20.Single-Speed (slow) Passband Ripple....................................................................................... 32

Figure 21.Double-Speed (fast) Stopband Rejection .................................................................................. 32

Figure 22.Double-Speed (fast) Transition Band......................................................................................... 32

Figure 23.Double-Speed (fast) Transition Band (detail)............................................................................. 32

Figure 24.Double-Speed (fast) Passband Ripple....................................................................................... 32

Figure 25.Double-Speed (slow) Stopband Rejection................................................................................. 33

Figure 26.Double-Speed (slow) Transition Band ....................................................................................... 33

Figure 27.Double-Speed (slow) Transition Band (detail) ........................................................................... 33

Figure 28.Double-Speed (slow) Passband Ripple ..................................................................................... 33

DS566F1

3

CS4351

Figure 29.Quad-Speed (fast) Stopband Rejection..................................................................................... 33

Figure 30.Quad-Speed (fast) Transition Band ........................................................................................... 33

Figure 31.Quad-Speed (fast) Transition Band (detail) ............................................................................... 34

Figure 32.Quad-Speed (fast) Passband Ripple ......................................................................................... 34

Figure 33.Quad-Speed (slow) Stopband Rejection.................................................................................... 34

Figure 34.Quad-Speed (slow) Transition Band.......................................................................................... 34

Figure 35.Quad-Speed (slow) Transition Band (detail).............................................................................. 34

Figure 36.Quad-Speed (slow) Passband Ripple........................................................................................ 34

LIST OF TABLES

Table 1. CS4351 Auto-Detect .................................................................................................................... 15

Table 2. CS4351 Mode Select ................................................................................................................... 15

Table 3. Single-Speed Mode Standard Frequencies ................................................................................. 16

Table 4. Double-Speed Mode Standard Frequencies................................................................................ 16

Table 5. Quad-Speed Mode Standard Frequencies .................................................................................. 16

Table 6. Digital Interface Format - Stand-Alone Mode............................................................................... 16

Table 7. Digital Interface Formats.............................................................................................................. 24

Table 8. ATAPI Decode ............................................................................................................................. 26

Table 9. Example Digital Volume Settings................................................................................................. 28

Table 10. Revision History ......................................................................................................................... 37

4

DS566F1

CS4351

1. PIN DESCRIPTION

20

19

18

1

SDIN

SCLK

LRCK

MCLK

VD

VL

2

AMUTEC

AOUTA

VA_H

GND

AOUTB

BMUTEC

VQ

3

4

17

16

15

14

13

12

5

6

GND

7

DIF1(SCL/CCLK)

DIF0(SDA/CDIN)

DEM(AD0/CS)

RST

8

9

VBIAS

VA

10

11

Pin Name

SDIN

#

1

2

Pin Description

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

Serial Clock (Input) - Serial clock for the serial audio interface.

SCLK

Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line.

LRCK

3

MCLK

VD

4

5

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

Digital Power (Input) - Positive power supply for the digital section.

6

16

GND

RST

Ground (Input) - Ground reference.

Reset (Input) - Powers down device and resets all internal resisters to their default settings when

enabled.

10

VA

11 Low Voltage Analog Power (Input) - Positive power supply for the analog section.

12 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.

13 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

17 High Voltage Analog Power (Input) - Positive power supply for the analog section.

20 Serial Audio Interface Power (Input) - Positive power for the serial audio interface

14

VBIAS

VQ

VA_H

VL

BMUTEC

AMUTEC

Mute Control (Output) - Control signal for optional mute circuit.

19

AOUTB

AOUTA

15 Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Character-

18 istics table.

Control Port Definitions

SCL/CCLK

SDA/CDIN

AD0/CS

7

8

9

Serial Control Port Clock (Input) - Serial clock for the control port interface.

Serial Control Data (Input/Output) - Input/Output for I²C data. Input for SPI data.

Address Bit 0 / Chip Select (Input) - Chip address bit in I²C Mode. Control Port enable in SPI Mode.

Stand-Alone Definitions

DIF0

DIF1

8

7

Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock,

Serial Clock, and Serial Audio Data.

De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1

kHz sample rates

DEM

9

DS566F1

5

CS4351

2. CHARACTERISTICS AND SPECIFICATIONS

(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.

Typical specifications are derived from performance measurements at T = 25 °C, VA_H = 12 V, VA = 3.3 V,

A

VD = 3.3 V.)

SPECIFIED OPERATING CONDITIONS

(GND = 0 V; all voltages with respect to ground.)

Parameters

Symbol

Min

Typ

Max

Units

DC Power Supply

High Voltage Analog power

Low Voltage Analog power

Digital power

V_{A_H}

V_A

V_D

8.55

3.13

1.7

12

3.3

12.6

3.47

V

Interface power

V_L

Specified Temperature Range

-CZZ

-DZZ

T_A

-10

-40

-

70

85

°C

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to ground.)

Parameters

Symbol

Min

Max

Units

DC Power Supply

High Voltage Analog power

Low Voltage Analog power

Digital power

V_{A_H}

V_A

V_D

-0.3

14

V

3.63

Interface power

V_L

Input Current, Any Pin Except Supplies

Digital Input Voltage

I_in

V_IN-L

T_A

-

±10

V_L+ 0.4

125

mA

V

Digital Interface

-0.3

-55

-65

Ambient Operating Temperature (power applied)

Storage Temperature

°C

T_stg

150

Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guar-

anteed at these extremes.

6

DS566F1

CS4351

DAC ANALOG CHARACTERISTICS

(Test conditions (unless otherwise specified): input test signal is a 997 Hz sine wave at 0 dBFS; measurement

bandwidth 10 Hz to 20 kHz)

Parameter

Symbol

Fs = 48, 96, and 192 kHz

Min

Typ

Max

Unit

All Speed Modes

Dynamic Range (Note 1)

24-bit unweighted

A-Weighted

16-bit unweighted

A-Weighted

99

102

-

109

112

95

-

dB

98

Total Harmonic Distortion + Noise

(Note 1) THD+N

0 dB

-20 dB

-60 dB

0 dB

-

24-bit

16-bit

-100

-89

-49

-92

-75

-35

-90

-79

-39

-

dB

-20 dB

-60 dB

All Speed Modes

Idle Channel Noise / Signal-to-noise ratio

Interchannel Isolation

-

109

100

-

dB

(1 kHz)

Analog Output - All Modes

Full Scale Output Voltage

Common Mode Voltage

Max DC Current draw from an AOUT pin

Max Current draw from VQ

Interchannel Gain Mismatch

Gain Drift

1.85

2.00

4

2.15

Vrms

Vdc

µA

V_Q

-

I_OUTmax

I_Qmax

10

1

-

µA

-

0.1

-100

50

-

dB

-

ppm/°C

Ω

Output Impedance

Z_OUT

R_L

-

AC-Load Resistance

5

-

kΩ

Load Capacitance

C_L

-

100

pF

Notes:

1. One-half LSB of triangular PDF dither is added to data.

DS566F1

7

CS4351

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-

ple rate by multiplying the given characteristic by Fs. See (Note 6)

Fast Roll-Off

Parameter

Min

Typ

Max

Unit

Combined Digital and On-Chip Analog Filter Response - Single-Speed Mode - 48 kHz

Passband (Note 3)

to -0.01 dB corner

to -3 dB corner

0

-

.454

.499

+0.01

-

±0.56/Fs

0

±0.23

±0.14

±0.09

Fs

dB

Fs

dB

s

dB

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

Total Group Delay (Fs = Output Sample Rate)

Intra-channel Phase Deviation

Inter-channel Phase Deviation

De-emphasis Error (Note 5)

(Relative to 1 kHz)

-0.01

0.547

102

-

(Note 4)

-

9.4/Fs

-

Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

Combined Digital and On-Chip Analog Filter Response - Double-Speed Mode - 96 kHz

Passband (Note 3)

to -0.01 dB corner

to -3 dB corner

0

-

.430

.499

0.01

-

Fs

dB

Fs

dB

s

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

Total Group Delay (Fs = Output Sample Rate)

Intra-channel Phase Deviation

Inter-channel Phase Deviation

-0.01

.583

80

-

(Note 4)

-

4.6/Fs

-

±0.03/Fs

0

-

s

-

Combined Digital and On-Chip Analog Filter Response - Quad-Speed Mode - 192 kHz

Passband (Note 3)

to -0.01 dB corner

to -3 dB corner

0

-

.105

.490

0.01

-

Fs

dB

Fs

dB

s

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

Total Group Delay (Fs = Output Sample Rate)

Intra-channel Phase Deviation

Inter-channel Phase Deviation

-0.01

.635

90

-

(Note 4)

-

4.7/Fs

-

±0.01/Fs

0

-

s

-

8

DS566F1

CS4351

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(Continued)

Slow Roll-Off (Note 2)

Parameter

Min

Typ

Max

Unit

Single-Speed Mode - 48 kHz

Passband (Note 3)

to -0.01 dB corner

to -3 dB corner

0

-

0.417

0.499

+0.01

-

±0.14/Fs

0

±0.23

±0.14

±0.09

Fs

dB

Fs

dB

s

dB

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

Total Group Delay (Fs = Output Sample Rate)

Intra-channel Phase Deviation

Inter-channel Phase Deviation

De-emphasis Error (Note 5)

(Relative to 1 kHz)

-0.01

.583

64

-

(Note 4)

-

6.5/Fs

-

Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

Double-Speed Mode - 96 kHz

Passband (Note 3))

to -0.01 dB corner

to -3 dB corner

0

-

.296

.499

0.01

-

Fs

dB

Fs

dB

s

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

Total Group Delay (Fs = Output Sample Rate)

Intra-channel Phase Deviation

Inter-channel Phase Deviation

Quad-Speed Mode - 192 kHz

Passband (Note 3))

-0.01

.792

70

-

(Note 4)

-

3.9/Fs

-

±0.01/Fs

0

-

s

-

to -0.01 dB corner

to -3 dB corner

0

-

.104

.481

0.01

-

Fs

dB

Fs

dB

s

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

Group Delay

Intra-channel Phase Deviation

Inter-channel Phase Deviation

-0.01

.868

75

(Note 4)

-

4.2/Fs

-

±0.01/Fs

0

-

s

-

Notes:

2. Slow Roll-off interpolation filter is only available in Control Port mode.

3. Response is clock dependent and will scale with Fs.

4. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.

For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.

For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

5. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in Stand-

Alone Mode.

6. Amplitude vs. Frequency plots of this data are available in the “Digital Filter Response Plots” on

page 31.

DS566F1

9

CS4351

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Parameters

Symbol

Min

1.024

45

Max

51.2

55

Units

MHz

%

MCLK Frequency

MCLK Duty Cycle

Input Sample Rate (Manual selection)

Single-Speed Mode

Double-Speed Mode

Fs

4

50

100

50

100

200

kHz

Quad-Speed Mode

Input Sample Rate (Auto selection)

Single-Speed Mode

Double-Speed Mode

Fs

4

84

170

50

100

200

kHz

Quad-Speed Mode

LRCK Duty Cycle

40

20

60

-

%

ns

-

SCLK Pulse Width Low

SCLK Pulse Width High

SCLK Period

t_sclkl

t_sclkh

t_sclkw

-

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

-

1

---------------------

(128)Fs

t_sclkw

-

1

------------------

(64)Fs

t_sclkw

2

-----------------

MCLK

SCLK rising to LRCK edge delay

SCLK rising to LRCK edge setup time

SDIN valid to SCLK rising setup time

SCLK rising to SDIN hold time

t_slrd

t_slrs

t_sdlrs

t_sdh

23

-

ns

20

LRCK

t

sclkh

slrs

t

slrd

t

sclkl

SCLK

t

sdh

sdlrs

SDATA

Figure 1. Serial Input Timing

10

DS566F1

CS4351

Switching Characteristics - Control Port - I²C^®Format

(Inputs: Logic 0 = GND, Logic 1 = VL, C = 20 pF)

L

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

f_scl

-

100

kHz

RST Rising Edge to Start

t_irs

t_buf

t_hdst

t_low

500

4.7

4.0

4.7

4.0

4.7

0

-

ns

µs

ns

µs

ns

µs

ns

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low time

-

Clock High Time

t_high

t_sust

t_hdd

-

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling

SDA Setup time to SCL Rising

Rise Time of SCL and SDA

-

(Note 7)

-

t_sud

250

-

1

t_rc, t_rc

t_fc, t_fc

t_susp

t_ack

Fall Time SCL and SDA

-

300

-

Setup Time for Stop Condition

Acknowledge Delay from SCL Falling

4.7

300

1000

Notes:

7. Data must be held for sufficient time to bridge the transition time, t , of SCL.

fc

RST

t

irs

Repeated

Stop

Start

Stop

Start

t

rd

fd

SDA

SCL

t

buf

t

high

hdst

fc

susp

hdst

low

t

sust

sud

ack

rc

hdd

Figure 2. Control Port Timing - I²C Format

DS566F1

11

CS4351

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VL, C = 20 pF)

L

Parameter

CCLK Clock Frequency

Symbol

f_sclk

t_srs

Min

-

Max

Unit

MHz

ns

6

RST Rising Edge to CS Falling

CCLK Edge to CS Falling

500

1.0

20

66

40

17

-

(Note 8)

t_spi

-

ns

CS High Time Between Transmissions

CS Falling to CCLK Edge

t_csh

t_css

t_scl

-

µs

-

ns

CCLK Low Time

-

ns

CCLK High Time

t_sch

t_dsu

t_dh

-

ns

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

ns

(Note 9)

(Note 10)

-

ns

t_r2

100

ns

t_f2

-

ns

Notes:

8.

9. Data must be held for sufficient time to bridge the transition time of CCLK.

10. For F < 1 MHz.

t

only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.

spi spi

SCK

RST

t

srs

CS

t

spi css

scl

sch

t

csh

CCLK

t

r2

f2

CDIN

t

dsu

dh

Figure 3. Control Port Timing - SPI Format (Write)

12

DS566F1

CS4351

DIGITAL CHARACTERISTICS

Parameters

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

VL = 3.3 V

VL = 2.5 V

VL = 1.8 V

V_IH

2.0

1.7

0.65•V_L

-

V

Low-Level Input Voltage

VL = 3.3 V

VL = 2.5 V

VL = 1.8 V

V_IL

-

0.8

0.7

0.33•V_L

V

Input Leakage Current

I_in

-

±10

µA

pF

mA

V

Input Capacitance

8

2

-

Maximum MUTEC Drive Current

MUTEC High-Level Output Voltage

MUTEC Low-Level Output Voltage

V_OH

V_OL

VA_H

0

V

POWER AND THERMAL CHARACTERISTICS

Parameters

Symbol

Min

Typ

Max

Units

Power Supplies

Power Supply Current

(Note 11)

normal operation, V_{A_H}= 12 V

I_{A_H}

I_A

I_D

I_L

-

15

14

6

21

100

200

20

19

8

26

400

-

mA

µA

V_{A_H}= 9 V

V_A= 3.3 V

V_D= 3.3 V

Interface current (Note 12) V_L= 3.3 V

power-down state, all supplies (Note 13)

I_pd

µA

Power Dissipation (all supplies)

VA_H = 12 V

(Note 11)

normal operation

power-down (Note 13)

normal operation

-

270

1

216

1

354

mW

-

285

-

VA_H = 9 V

power-down (Note 13)

Power Supply Rejection Ratio (Note 14)

(1 kHz)

(60 Hz)

PSRR

-

60

-

dB

Notes:

11. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are

based on highest FS and highest MCLK. Variance between speed modes is small.

12. I measured with no external loading on pin 8 (SDA).

L

13. Power-Down Mode is defined as RES pin = Low with all clock and data lines held static.

14. Valid with the recommended capacitor values on VQ and V

gram in Section 3.

as shown in the typical connection dia-

BIAS

DS566F1

13

CS4351

3. TYPICAL CONNECTION DIAGRAM

5.1Ω∗

+3.3 V

+3.3 V *

*Optional

+

10 µF

0.1 µF

12

10 µF

*Remove this supply if

optional resistor is present.

The decoupling caps should

remain.

5

11

VA

3.3 µF

+

VD

VBIAS+

4

MCLK

3

2

1

17

Digital

Audio

Source

LRCK

VA_H

+9 V to +12 V

0.1 µF

+

SCLK

SDIN

10 µF

Optional Mute Circuit

19

18

AMUTEC

AOUTA

20

+1.8 V to VD

VL

576 k

412 k

Ω

560

Ω

0.1 µF

AOUTA

+

2.2 nF*

CS4351

3.3 µF

10 k

Ω

Optional Mute Circuit

14

15

BMUTEC

AOUTB

576 k

412 k

Ω

10

7

RST

560 Ω

µ C/

Mode

Configuration

DIF1(SCL/CCLK)

DIF0(SDA/CDIN)

DEM(AD0/CS)

AOUTA

+

2.2 nF*

8

9

3.3 µF

10k

Ω

*Shown value is

for fc=130kHz

13

VQ

3.3 µF

+

GND

6

GND

16

Figure 4. Typical Connection Diagram

14

DS566F1

CS4351

4. APPLICATIONS

4.1

Sample Rate Range/Operational Mode Detect

The device operates in one of three operational modes. The allowed sample rate range in each mode will

depend on whether the Auto-Detect Defeat bit is enabled/disabled.

4.1.1

Auto-Detect Enabled

The Auto-Detect feature is enabled by default. In this state, the CS4351 will auto-detect the correct mode

when the input sample rate (F ), defined by the LRCK frequency, falls within one of the ranges illustrated

s

in Table 1. Sample rates outside the specified range for each mode are not supported.

Input Sample Rate (F )

MODE

S

4 kHz - 50 kHz

84 kHz - 100 kHz

170 kHz - 200 kHz

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

Table 1. CS4351 Auto-Detect

4.1.2

Auto-Detect Disabled

The Auto-Detect feature can be defeated only by the format bits in the control port register 02h. In this

state, the CS4351 will not auto-detect the correct mode based on the input sample rate (F ). The opera-

s

tional mode must then be set manually according to one of the ranges illustrated in Table 2. Please refer

to Section 6.2.3 for implementation details. Sample rates outside the specified range for each mode are

not supported. In stand-alone mode it is not possible to disable auto-detect of sample rates.

FM1

FM0

Input Sample Rate (F )

MODE

S

0

1

0

1

0

1

Auto speed mode detect

4 kHz - 50 kHz

Auto

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

50 kHz - 100 kHz

100 kHz - 200 kHz

Table 2. CS4351 Mode Select

4.2

System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.

The left/right clock, defined also as the input sample rate (F ), must be synchronously derived from the

s

MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard au-

dio sample rates and the required MCLK frequency, are illustrated in Tables 3 through 5.

Refer to Section 4.3 for the required SCLK timing associated with the selected Digital Interface Format and

to the “Switching Specifications - Serial Audio Interface” section on page 10 for the maximum allowed clock

frequencies.

DS566F1

15

CS4351

Sample Rate

(kHz)

MCLK (MHz)

256x

8.1920

11.2896

12.2880

384x

512x

768x

1024x

32.7680

45.1584

49.1520

1152x

36.8640

32

44.1

48

12.2880

16.9344

18.4320

16.3840

22.5792

24.5760

33.8688

36.8640

Table 3. Single-Speed Mode Standard Frequencies

Sample Rate

(kHz)

MCLK (MHz)

128x

8.1920

11.2896

12.2880

192x

256x

384x

512x

64

88.2

96

12.2880

16.9344

18.4320

16.3840

22.5792

24.5760

33.8688

36.8640

32.7680

45.1584

49.1520

Table 4. Double-Speed Mode Standard Frequencies

Sample Rate

(kHz)

MCLK (MHz)

64x

96x

128x

192x

256x

176.4

192

11.2896

12.2880

16.9344

18.4320

22.5792

24.5760

33.8688

36.8640

45.1584

49.1520

Table 5. Quad-Speed Mode Standard Frequencies

= Denotes clock modes which are NOT auto detected

4.3

Digital Interface Format

The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated

in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 7.

4.3.1

Stand-Alone Mode

The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship

between the LRCK, SCLK and SDIN, see Figures 5 through 7. For all formats, SDIN is valid on the rising

edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2, and 48 cycles per

LRCK period in format 3.

DIF0 DIF1

DESCRIPTION

I S, up to 24-bit Data

Left Justified, up to 24-bit Data

Right Justified, 24-bit Data

Right Justified, 16-bit Data

FORMAT FIGURE

2

0

1

0

1

0

1

0

1

2

3

6

5

7

Table 6. Digital Interface Format - Stand-Alone Mode

4.3.2

Control Port Mode

The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section

Section 6.2.1). For an illustration of the required relationship between LRCK, SCLK and SDIN, see

Figures 5 through 7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at

16

DS566F1

CS4351

least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and 36 cycles

in format 5.

Left Channel

Right Channel

LRCK

SCLK

LSB

MSB

-1 -2 -3 -4

MSB

SDIN

+5 +4 +3 +2 +1

-1 -2 -3 -4 -5

Figure 5. Left-Justified up to 24-Bit Data

Left Channel

Right Channel

LRCK

SCLK

LSB

MSB

-1 -2 -3 -4

MSB

SDIN

+5 +4 +3 +2 +1

-1 -2 -3 -4 -5

Figure 6. I²S, up to 24-Bit Data

Right Channel

LRCK

SCLK

Left Channel

MSB

LSB

MSB

+1 +2 +3 +4 +5

-7 -6 -5 -4 -3 -2 -1

MSB

LSB

-7 -6 -5 -4 -3 -2 -1

SDIN

+1 +2 +3 +4

+5

Figure 7. Right-Justified Data

4.4

De-Emphasis Control

The device includes on-chip digital de-emphasis. Figure 8 shows the de-emphasis curve for F equal to 44.1

s

kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample

rate, Fs.

Gain

dB

T1=50 µs

0dB

T2 = 15 µs

-10dB

F1

F2

Frequency

3.183 kHz

10.61 kHz

Figure 8. De-Emphasis Curve

Note:

DS566F1

De-emphasis is only available in Single-Speed Mode.

17

CS4351

4.4.1

4.4.2

Stand-Alone Mode

When pulled to VL the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND the DEM

pin turns off the de-emphasis filter.

Control Port Mode

The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see Section 6.2.2

for the desired de-emphasis control.

4.5

Recommended Power-Up Sequence

4.5.1

Stand-Alone Mode

1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right

clocks are locked to the appropriate frequencies, as discussed in Section 4.2. In this state, the control

port is reset to its default settings, VQ will remain low, and VBIAS will be connected to VA.

2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-

Alone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK

cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

4.5.2

Control Port Mode

1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the

appropriate frequencies, as discussed in Section 4.2. In this state, the control port is reset to its

default settings, VQ will remain low, and VBIAS will be connected to VA.

2. Bring RST high. The device will remain in a low power state with VQ low.

3. Perform a control port write to the CP_EN bit prior to the completion of approximately 512 LRCK

cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in

Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.

4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs when

the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description of

power-up timing.

®

4.6

Popguard Transient Control

The CS4351 uses a novel technique to minimize the effects of output transients during power-up and power-

down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,

minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated

inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the

appropriate DC-blocking capacitors.

4.6.1

Power-Up

When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.

Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies-

cent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V and audio output begins.

Q

This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies-

cent voltage, minimizing audible power-up transients.

18

DS566F1

CS4351

4.6.2

4.6.3

4.7

Power-Down

To prevent audible transients at power-down, the device must first enter its power-down state. When this

occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.

In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-

charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready

for the next power-on.

Discharge Time

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-

fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will

occur when the audio outputs are initially clamped to GND. The time that the device must remain in the

power-down state is related to the value of the DC-blocking capacitance and the output load. For example,

with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.

Mute Control

The Mute Control pins go active during power-up initialization, reset, muting (see Section 6.4.3), or if the

MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to

prevent the clicks and pops that can occur in any single-ended single supply system.

Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-

imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer

to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.

Please see the “Typical Connection Diagram” on page 14 for a suggested mute circuit for single supply sys-

tems. This FET circuit must be placed in series after the RC filter, otherwise noise may occur during muting

conditions. Further ESD protection will need to be taken into consideration for the FET used. If dual supplies

are available, the BJT mute circuit from Figure 12 in the CS4398 datasheet (active Low) may be used.

4.8

Grounding and Power Supply Arrangements

As with any high resolution converter, the CS4351 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 4 shows the recommended power ar-

rangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between

digital ground and analog ground, the GND pins of the CS4351 should be connected to the analog ground

plane.

All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted

coupling into the DAC.

4.8.1

Capacitor Placement

Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-

pacitor being the closest. To further minimize impedance, these capacitors should be located on the same

layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling ca-

pacitor should still be placed on each supply pin.

Note:

All decoupling capacitors should be referenced to analog ground.

The CDB4351 evaluation board demonstrates the optimum layout and power supply arrangements.

DS566F1

19

CS4351

4.9

Control Port Interface

The control port is used to load all the internal register settings (see Section 6). The operation of the control

port may be completely asynchronous with the audio sample rate. However, to avoid potential interference

problems, the control port pins should remain static if no operation is required.

The control port operates in one of two modes: I²C or SPI.

4.9.1

4.9.2

MAP Auto Increment

The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also

the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and

SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or

writes of successive registers.

I²C Mode

In the I²C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial

control port clock, SCL (see Figure 9 for the clock to data relationship). There is no CS pin. Pin AD0 en-

ables the user to alter the chip address (100110[AD0][R/W]) and should be tied to VL or GND as required,

before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after

power-up, SPI mode will be selected.

4.9.2.1 I²C Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifica-

tions in Section 8.

1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be

100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth

bit of the address byte is the R/W bit.

2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This

byte points to the register to be written.

3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to

by the MAP.

4. If the INCR bit (see Section 4.9.1) is set to 1, repeat the previous step until all the desired registers

are written, then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate

a repeated START condition and follow the procedure detailed from step 1. If no further writes to oth-

er registers are desired, initiate a STOP condition to the bus.

20

DS566F1

CS4351

4.9.2.2 I²C Read

To read from the device, follow the procedure below while adhering to the control port Switching Specifica-

tions.

1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be

100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth

bit of the address byte is the R/W bit.

2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register

pointed to by the MAP. The MAP register will contain the address of the last register written to the

MAP, or the default address (see Section 4.10.2) if an I²C read is the first operation performed on

the device.

3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.

4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.

Continue providing a clock and issue an ACK after each byte until all the desired registers are read,

then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to

initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the

I²C Write instructions followed by step 1 of the I²C Read section. If no further reads from other reg-

isters are desired, initiate a STOP condition to the bus.

NOTE

DATA

1-8

DATA

1-8

100110

R/W

ACK

SDA

SCL

AD0

Start

Stop

NOTE: If operation is a write, this byte contains the Memory Address Pointer, MAP. If

operation is a read, this byte contains the data of the register pointed to by the MAP.

Figure 9. Control Port Timing, I²C Mode

4.9.3

SPI Mode

In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK

(see Figure 10 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and

is used to control SPI writes to the control port. When the device detects a high to low transition on the

AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the

rising edge of CCLK.

4.9.3.1 SPI Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifica-

tions in Section 8.

1. Bring CS low.

2. The address byte on the CDIN pin must then be 10011000.

3. Write to the memory address pointer, MAP. This byte points to the register to be written.

DS566F1

21

CS4351

4. Write the desired data to the register pointed to by the MAP.

5. If the INCR bit (see Section 4.9.1) is set to 1, repeat the previous step until all the desired registers

are written, then bring CS high.

6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring

CS high, and follow the procedure detailed from step 1. If no further writes to other registers are de-

sired, bring CS high.

)

CS

CCLK

CHIP

ADDRESS

MAP

DATA

1001100

LSB

CDIN

MSB

R/W

byte 1

byte n

MAP = Memory Address Pointer

Figure 10. Control Port Timing, SPI mode

4.10 Memory Address Pointer (MAP)

7

INCR

0

6

Reserved

0

5

Reserved

0

4

Reserved

0

3

MAP3

0

2

1

MAP1

0

MAP0

0

MAP2

0

4.10.1 INCR (AUTO MAP INCREMENT ENABLE)

Default = ‘0’

0 - Disabled

1 - Enabled

4.10.2 MAP (MEMORY ADDRESS POINTER)

Default = ‘0000’

22

DS566F1

CS4351

5. REGISTER QUICK REFERENCE

Addr

Function

7

6

PART3

1

5

PART2

1

4

PART1

1

3

PART0

1

2

REV2

-

1

REV1

-

0

REV0

-

1h Chip ID

PART4

default

2h Mode Control

default

1

Reserved

0

DIF2

0

DIF1

0

DIF0

0

DEM1

0

DEM0

0

FM1

0

FM0

0

3h Volume, Mixing,

and Inversion

Control

VOLB=A INVERTA INVERTB Reserved

ATAPI3

ATAPI2

ATAPI1

ATAPI0

default

4h Mute Control

0

1

0

1

AMUTE

Reserved MUTEC

A=B

MUTE_A

MUTE_B Reserved Reserved Reserved

default

1

0

5h Channel A Volume

Control

VOL7

VOL6

VOL5

VOL4

VOL3

VOL2

VOL1

VOL0

default

0

6h Channel B Volume

Control

VOL7

VOL6

VOL5

VOL4

VOL3

VOL2

VOL1

VOL0

default

0

7h Ramp and Filter

Control

SZC1

SZC0

RMP_UP RMP_DN

Reserved FILT_SEL Reserved Reserved

default

8h Misc. Control

default

1

PDN

1

0

CPEN

0

1

0

1

FREEZE Reserved

Reserved Reserved Reserved Reserved

0

DS566F1

23

CS4351

6. REGISTER DESCRIPTION

** All register access is R/W unless specified otherwise**

6.1

Chip ID - Register 01h

7

PART4

1

6

PART3

1

5

PART2

1

4

PART1

1

3

PART0

1

2

REV2

-

1

REV1

-

0

REV0

-

Function:

This register is Read-Only. Bits 7 through 3 are the part number ID which is 11111b and the remaining Bits

(2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)

6.2

Mode Control 1 - Register 02h

7

6

DIF2

0

5

DIF1

0

4

DIF0

0

3

DEM1

0

2

DEM0

0

1

FM1

0

FM0

0

Reserved

0

6.2.1

Digital Interface Format (DIF2:0) Bits 6-4

Function:

These bits select the interface format for the serial audio input.

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital

Interface Format and the options are detailed in Figures 5 through 7.

DIF2

DIF1

DIF0

DESCRIPTION

Format

FIGURE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5

6

7

Left Justified, up to 24-bit data

I S, up to 24-bit data

0 (Default)

2

1

2

3

4

5

Right Justified, 16-bit data

Right Justified, 24-bit data

Right Justified, 20-bit data

Right Justified, 18-bit data

Reserved

Table 7. Digital Interface Formats

6.2.2

De-Emphasis Control (DEM1:0) Bits 3-2.

Gain

dB

Default = 0

00 - No De-emphasis

01 - 44.1 kHz De-emphasis

10 - 48 kHz De-emphasis

11 - 32 kHz De-emphasis

T1=50 µs

0dB

T2 = 15 µs

Frequency

-10dB

Function:

Selects the appropriate digital filter to maintain the stan-

dard 15 µs/50 µs digital de-emphasis filter response at

32, 44.1 or 48 kHz sample rates. (See Figure 11.)

F1

3.183 kHz

F2

10.61 kHz

Figure 11. De-Emphasis Curve

Note: De-emphasis is only available in Single-Speed Mode

24

DS566F1

CS4351

6.2.3

Functional Mode (FM) Bits 1-0

Default = 00

00 - Auto speed mode detect

01 - Single-Speed Mode (4 to 50 kHz sample rates)

10 - Double-Speed Mode (50 to 100 kHz sample rates)

11 - Quad-Speed Mode (100 to 200 kHz sample rates)

Function:

Selects the required range of input sample rates or DSD Mode.

6.3

Volume Mixing and Inversion Control - Register 03h

B7

VOLB=A

0

B6

INVERT A

0

B5

INVERT B

0

B4

Reserved

0

B3

ATAPI3

1

B2

ATAPI2

0

B1

ATAPI1

0

B0

ATAPI0

1

6.3.1

Channel A Volume = Channel B Volume (VOLB=A) Bit 7

Function:

When set to 0 (default) the AOUTA and AOUTB volume levels are independently controlled by the A and

the B Channel Volume Control Bytes.

When set to 1 the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and

Volume Control Bytes, and the B Channel Bytes are ignored.

6.3.2

6.3.3

Invert Signal Polarity (Invert_A) Bit 6

Function:

When set to 1, this bit inverts the signal polarity of channel A.

When set to 0 (default), this function is disabled.

Invert Signal Polarity (Invert_B) Bit 5

Function:

When set to 1, this bit inverts the signal polarity of channel B.

When set to 0 (default), this function is disabled.

DS566F1

25

CS4351

6.3.4

ATAPI Channel Mixing and Muting (ATAPI3:0) Bits 3-0

Default = 1001 - AOUTA=aL, AOUTB=bR (Stereo)

Function:

The CS4351 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to

Table 8 and Figure 12 for additional information.

A Channel

Volume

Control

Left Channel

Audio Data

MUTE

AoutA

Σ

B Channel

Volume

Control

Right Channel

Audio Data

MUTE

AoutB

Figure 12. ATAPI Block Diagram

ATAPI3 ATAPI2 ATAPI1 ATAPI0

AOUTA

MUTE

aR

AOUTB

MUTE

bR

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

bL

b[(L+R)/2]

MUTE

bR

aR

aL

bL

b[(L+R)/2]

MUTE

bR

bL

b[(L+R)/2]

MUTE

bR

a[(L+R)/2]

bL

b[(L+R)/2]

Table 8. ATAPI Decode

26

DS566F1

CS4351

6.4

Mute Control - Register 04h

7

6

Reserved

0

5

4

MUTE_A

0

3

MUTE_B

0

2

Reserved

0

1

Reserved

0

Reserved

0

AMUTE

1

MUTEC A=B

0

6.4.1

Auto-Mute (AMUTE) Bit 7

Function:

When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192

consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. De-

tection and muting is done independently for each channel. The quiescent voltage on the output will be

retained and the Mute Control pin will go active during the mute period. When set to 0, this function is

disabled

6.4.2

6.4.3

AMUTEC = BMUTEC (MUTEC A=B) Bit 5

Function:

When set to 0 (default), the AMUTEC and BMUTEC pins operate independently.

When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an

AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only

when the requirements for both AMUTEC and BMUTEC are valid.

A Channel Mute (MUTE_A) Bit 4

B Channel Mute (MUTE_B) Bit 3

Function:

When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will

be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross

bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any

ramping due to the soft and zero cross function.

When set to 0 (default), this function is disabled.

6.5

Channel A Volume Control - Register 05h

Channel B Volume Control - Register 06h

7

6

VOL6

0

5

VOL5

0

4

VOL4

0

3

VOL3

0

2

VOL2

0

1

VOL1

0

VOL0

0

VOL7

0

DS566F1

27

CS4351

6.5.1

Digital Volume Control (VOL7:0) Bits 7-0

Default = 00h (0 dB)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments

from 0 to -127.5 dB. Volume settings are decoded as shown in Table 9. The volume changes are imple-

mented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register.

The actual attenuation is determined by taking the decimal value of the volume register and multiplying

by 6.02/12.

Binary Code

00000000

00000001

00000110

11111111

Decimal Value

Volume Setting

0 dB

0

1

6

-0.5 dB

-3.0 dB

-127.5 dB

255

Table 9. Example Digital Volume Settings

6.6

Ramp and Filter Control - Register 07h

7

6

SZC0

0

5

RMP_UP

1

4

RMP_DN

1

3

Reserved

0

2

FILT_SEL

0

1

Reserved

0

Reserved

1

SZC1

1

6.6.1

Soft Ramp and Zero Cross Control (SZC1:0) Bits 7-6

Default = 10

SZC1 SZC0

Description

Immediate Change

Zero Cross

0

1

0

1

0

1

Soft Ramp

Soft Ramp on Zero Crossings

Function:

Immediate Change

When Immediate Change is selected all level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-

out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal

does not encounter a zero crossing. The zero cross function is independently monitored and implemented

for each channel.

Soft Ramp PCM

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

28

DS566F1

CS4351

Soft Ramp and Zero Cross

Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-

ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will

occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample

rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored

and implemented for each channel.

6.6.2

Soft Volume Ramp-Up After Error (RMP_UP) Bit 5

Function:

When set to 1 (default), an un-mute will be performed after executing a filter mode change, after a

LRCK/MCLK ratio change or error, and after changing the Functional Mode. This un-mute is affected, sim-

ilar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.

When set to 0, an immediate un-mute is performed in these instances.

Note: For best results, it is recommended this feature be used in conjunction with the RMP_DN bit.

6.6.3

Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4

Function:

When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is

affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control

register.

When set to 0, an immediate mute is performed prior to executing a filter mode change.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.

6.6.4

Interpolation Filter Select (FILT_SEL) Bit 2

Function:

When set to 0 (default), the Interpolation Filter has a fast roll off.

When set to 1, the Interpolation Filter has a slow roll off.

The specifications for each filter can be found in the “Combined Interpolation & On-Chip Analog Filter Re-

sponse” section on page 8, and response plots can be found in Figures 15 to 36.

6.7

Misc Control - Register 08h

7

PDN

1

6

CPEN

0

5

FREEZE

0

4

Reserved

0

3

Reserved

0

2

Reserved

0

1

Reserved

0

Reserved

0

DS566F1

29

CS4351

6.7.1

6.7.2

6.7.3

Power Down (PDN) Bit 7

Function:

When set to 1 (default), the entire device will enter a low-power state and the contents of the control reg-

isters will be retained. The power-down bit defaults to ‘1’ on power-up and must be disabled before normal

operation in Control Port mode can occur. This bit is ignored if CPEN is not set.

Control Port Enable (CPEN) Bit 6

Function:

This bit is set to 0 by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode

can be accessed by setting this bit to 1. This will allow operation of the device to be controlled by the reg-

isters and the pin definitions will conform to Control Port Mode.

Freeze Controls (Freeze) Bit 5

Function:

When set to 1, this function allows modifications to be made to the registers without the changes taking

effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect

simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

When set to 0 (default), register changes take effect immediately.

30

DS566F1

CS4351

7. DIGITAL FILTER RESPONSE PLOTS

0

−20

0

−20

−40

−60

−80

−100

−120

0.4

0.42

0.44

0.46

0.48

0.5

0.52

0.54

0.56

0.58

0.6

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 13. Single-Speed (fast) Stopband Rejection

Figure 14. Single-Speed (fast) Transition Band

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

0.02

0.015

0.01

0.005

0

−0.005

−0.01

−0.015

−0.02

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency(normalized to Fs)

Figure 15. Single-Speed (fast) Transition Band (detail)

Figure 16. Single-Speed (fast) Passband Ripple

0

−20

0

−20

−40

−60

−80

−100

−120

−100

−120

0.4

0.5

0.6

0.7

0.8

0.9

1

0.4

0.42

0.44

0.46

0.48

0.5

0.52

0.54

0.56

0.58

0.6

Frequency(normalized to Fs)

Figure 17. Single-Speed (slow) Stopband Rejection

Figure 18. Single-Speed (slow) Transition Band

DS566F1

31

CS4351

0.02

0.015

0.01

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

0.005

0

−0.005

−0.01

−0.015

−0.02

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

Frequency(normalized to Fs)

Figure 19. Single-Speed (slow) Transition Band (detail)

Figure 20. Single-Speed (slow) Passband Ripple

0

20

40

60

80

100

120

100

120

0.4

0.42

0.44

0.46

0.48

0.5

0.52

0.54

0.56

0.58

0.6

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 21. Double-Speed (fast) Stopband Rejection

Figure 22. Double-Speed (fast) Transition Band

0

1

0.02

0.015

0.01

2

3

0.005

0

4

5

6

0.005

0.01

7

8

0.015

0.02

9

10

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency(normalized to Fs)

Figure 23. Double-Speed (fast) Transition Band (detail)

Figure 24. Double-Speed (fast) Passband Ripple

32

DS566F1

CS4351

0

20

40

20

40

60

80

100

120

100

120

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 25. Double-Speed (slow) Stopband Rejection

Figure 26. Double-Speed (slow) Transition Band

0

1

0.02

0.015

0.01

2

3

0.005

0

4

5

6

0.005

0.01

7

8

0.015

0.02

9

10

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Frequency(normalized to Fs)

Figure 27. Double-Speed (slow) Transition Band (detail)

Figure 28. Double-Speed (slow) Passband Ripple

0

20

40

60

80

100

120

100

120

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 29. Quad-Speed (fast) Stopband Rejection

Figure 30. Quad-Speed (fast) Transition Band

DS566F1

33

CS4351

0

0.2

0.15

0.1

1

2

3

0.05

0

4

5

6

0.05

7

0.1

0.15

0.2

8

9

10

0

0.05

0.1

0.15

0.2

0.25

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

Frequency(normalized to Fs)

Figure 31. Quad-Speed (fast) Transition Band (detail)

Figure 32. Quad-Speed (fast) Passband Ripple

0

20

40

20

40

60

80

100

120

100

120

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 33. Quad-Speed (slow) Stopband Rejection

Figure 34. Quad-Speed (slow) Transition Band

0

1

0.02

0.015

0.01

0.005

0

2

3

4

5

6

0.005

0.01

0.015

0.02

7

8

9

10

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

0

0.02

0.04

0.06

0.08

0.1

0.12

Frequency(normalized to Fs)

Figure 35. Quad-Speed (slow) Transition Band (detail)

Figure 36. Quad-Speed (slow) Passband Ripple

34

DS566F1

CS4351

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full

scale. This technique ensures that the distortion components are below the noise level and do not effect the

measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-

1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci-

bels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Intra-Channel Phase Deviation

The deviation from linear phase within a given channel.

Inter-Channel Phase Deviation

The difference in phase between channels.

DS566F1

35

CS4351

9. PACKAGE DIMENSIONS

20L TSSOP (4.4 mm BODY) PACKAGE DRAWING

N

D

E1¹

A2

A

E

∝

A1

b²

e

L

END VIEW

SEATING

PLANE

SIDE VIEW

1

2

3

TOP VIEW

INCHES

NOM

MILLIMETERS

NOM

NOTE

DIM

MIN

MAX

MIN

MAX

A

A1

A2

b

D

E

E1

e

L

--

0.002

0.03346

0.00748

0.252

0.248

0.169

--

0.043

0.006

0.037

0.012

0.259

0.256

0.177

0.026

0.028

8°

--

1.10

0.15

0.95

0.30

6.60

6.50

4.50

0.65

0.70

8°

0.004

0.0354

0.0096

0.256

0.2519

0.1732

--

0.05

0.85

0.19

6.40

6.30

4.30

--

0.90

0.245

6.50

6.40

4.40

--

2,3

1

0.020

0°

0.024

4°

0.50

0°

0.60

4°

µ

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Notes:

1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mis-

match and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm

total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimen-

sion “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

Parameters

Package Thermal Resistance

Symbol

Min

-

Typ

72

Max

-

Units

°C/Watt

20L TSSOP

θ_JA

36

DS566F1

CS4351

10.ORDERING INFORMATION

Product

Description

Package Pb-Free

Grade

Temp Range Container

Order #

Rail

CS4351-CZZ

Commercial -10° to +70° C

Automotive -40° to +85° C

Tape & Reel

CS4351-CZZR

CS4351-DZZ

CS4351-DZZR

CDB4351

192 kHz Stereo DAC

with 2 Vrms Line Out

20-pin

YES

CS4351

TSSOP

Rail

Tape & Reel

-

CDB4351

CS4351 Evaluation Board

-

11.REVISION HISTORY

Release

Date

Changes

PP3

March 2005

Removed CS4351-CZ ordering option.

Added CS4351-DZZ ordering option.

Updated Tslrd spec on page 10.

Updated Tdh spec on page 12.

Updated VIL specification on page 13.

Updated legal text.

PP4

F1

July 2005

Updated full-scale output specification on page 7.

Updated gain drift on page 7

Updated ordering information.

December 2005 Updated status to final

Updated legal text

Table 10. Revision History

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject

to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale

supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third

parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,

copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-

sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent

does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-

ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE

IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-

VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD

TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE

IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED

IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA-

TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER

AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE

USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be

trademarks or service marks of their respective owners.

SPI is a trademark of Motorola, Inc.

I²C is a registered trademark of Philips Semiconductor.

DS566F1

37

型号:	CS4351-CZZR
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP20,.25
针数：	20
Reach Compliance Code：	compliant
风险等级：	5.8
Is Samacsys：	N
最大模拟输出电压：	2.15 V
最小模拟输出电压：	1.85 V
转换器类型：	D/A CONVERTER
输入位码：	2'S COMPLEMENT
输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e3
长度：	6.5 mm
湿度敏感等级：	3
位数：	24
功能数量：	1
端子数量：	20
最高工作温度：	70 °C
最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3.3,12 V
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Other Converters
最大压摆率：	26 mA
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	4.4 mm
Base Number Matches：	1

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