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产品型号CS51021AEDR16的概述

芯片CS51021AEDR16的概述 CS51021AEDR16是一款高性能的模拟前端（AFE）芯片，广泛应用于各种电子设备中，尤其是在医疗、传感器和工业控制等领域。此芯片由著名的半导体公司Cypress Semiconductor制造，旨在为用户提供准确的信号处理和高效的电能管理功能。随着科技的不断进步，CS51021AEDR16在解决复杂信号处理需求方面显示了其出色的性能。 CS51021AEDR16的设计目标是能够在多种系统条件下提供可靠和灵活的性能，这使得它适用于包括流量测量、压力监测等各种应用场景。无论是在高噪声环境下还是低电压供应条件下，CS51021AEDR16都能够保持其正常工作状态。对于那些需要高精度和低功耗的设计开发者而言，CS51021AEDR16无疑提供了极大的便利。芯片CS51021AEDR16的详细参数 CS51021AEDR16的参数设计涵盖了多方面的需...

产品型号CS51021AEDR16的Datasheet PDF文件预览

CS51021A, CS51022A,

CS51023A, CS51024A

Enhanced Current Mode

PWM Controller

The CS51021A/2A/3A/4A Fixed Frequency PWM Current Mode

Controller family provides all necessary features required for AC−DC

or DC−DC primary side control. Several features are included

eliminating the additional components needed to implement them

externally. In addition to low startup current (75 mA) and high

frequency operation capability, the CS51021A/2A/3A/4A family

includes overvoltage and undervoltage monitoring, externally

programmable dual threshold overcurrent protection, current sense

leading edge blanking, current slope compensation, accurate duty cycle

control and an externally available 5.0 V reference. The CS51021A

and CS51023A feature bidirectional synchronization capability, while

the CS51022A and CS51024A offer a sleep mode with 100 mA

maximum IC current consumption. The CS51021A/2A/3A/4A family

is available in a 16 lead narrow body SOIC package.

http://onsemi.com

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DTB SUFFIX

CASE 948F

Device

CS51021A

Sleep/Synch

Synch

Start/Stop

PIN CONNECTIONS AND

MARKING DIAGRAMS

8.25 V/7.7 V

13 V/7.7 V

CS51022A

CS51023A

CS51024A

Sleep

Synch

GATE

Sleep

PGND

SENSE

SLEEP or SYNC

SLOPE

REF

Features

LGND

• 75 mA Max. Startup Current

• Fixed Frequency Current Mode Control

• 1.0 MHz Switching Frequency

• Undervoltage Protection Monitor

R C

COMP

SET

• Overvoltage Protection Monitor with Programmable Hysteresis

• Programmable Dual Threshold Overcurrent Protection with

Delayed Restart

• Programmable Soft Start

• Accurate Maximum Duty Cycle Limit

• Programmable Slope Compensation

• Leading Edge Current Sense Blanking

• 1.0 A Sink/Source Gate Drive

= Specific Device Code

= Assembly Location

WL, L = Wafer Lot

= Year

WW, W = Work Week

G or G = Pb−Free Package

• Bidirectional Synchronization (CS51021A/3A)

• 50 ns PWM Propagation Delay

• 100 mA Max Sleep Current (CS51022A/4A)

• Pb−Free Packages are Available*

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

February, 2006 − Rev. 8

CS51021A/D

CS51021A, CS51022A, CS51023A, CS51024A

100

(36 V to 72 V)

51 k

BAS21

1.0 mF

PGND

18 V

22 mF

SYNC/SLEEP

11 V

100:1

FZT688

2:5

200 k,

1.0%

10 k

24.3 k,

1.0%

4:1

OUT

0.01 mF

4700 pF

51 k

(5 V/5 A)

2.49 k,

1.0%

SET

22 k

REF

10 k

COMP

R C

SYNC/

SLEEP

LGND

BA521

100 mF 100 mF

680 pF

SLOPE

GATE

SENSE

IRF6345

SGND

100

6.98 k, 6.98 k,

1.0% 1.0%

PGND

330 pF

0.01 mF

470 pF

100 p

0.1 mF

5.1 k

TL431

2.0 k, 1.0%

1000 pF

180

2.0 k,

1.0%

1.0 k

MOC81025

10 K

1.0 K

Figure 1. Typical Application Diagram, 36−72 V to 5.0 V, 5.0 A DC−DC Converter

MAXIMUM RATINGS*

Rating

Value

Unit

Power Supply Voltage, V

−0.3, 20

Driver Supply Voltage, V

SYNC, SLEEP, R C , SOFT−START, V , SLOPE, I

, UV, OV, I

SENSE

(Logic Pins)

0.25 to V

1.0

SET

REF

Peak GATE Output Current

Steady State Output Current

Operating Junction Temperature, T

0.2

150

°C

Storage Temperature Range, T

−65 to +150

2.0

ESD (Human Body Model)

Lead Temperature Soldering:

Reflow: (SMD styles only) (Note 1)

230 peak

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

*The maximum package power dissipation must be observed.

1. 60 second maximum above 183°C.

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40°C < T < 85°C, −40°C < T < 150°C,

3.0 V < V < 20 V, 8.2 V < V < 20 V, R = 12 kW, C = 390 pF)

Characteristic

Under Voltage Lockout

Test Conditions

Min

Typ

Max

Unit

START Threshold (CS51021A/2A)

START Threshold (CS51023A/4A)

STOP Threshold

−

7.95

12.4

7.4

0.50

4.0

−

8.25

8.8

13.4

8.2

1.00

6.0

7.7

0.75

5.0

Hysteresis (CS51021A/2A)

Hysteresis (CS51023A/4A)

@ Startup (CS51021A/2A)

@ Startup (CS51023A/4A)

Operating (CS51021A/3A)

Operating (CS51022A/4A)

Operating

< UV

Threshold

START

Threshold

−

7.0

6.0

7.0

9.0

8.0

−

Includes 1.0 nF Load

−

Voltage Reference

Initial Accuracy

Total Accuracy

Line Regulation

Load Regulation

NOISE Voltage

OP Life Shift

T = 25°C, I

= 2.0 mA, V = 14 V, (Note 2)

4.95

5.0

6.0

5.05

5.15

REF

1.0 mA < I

< 10 mA

4.9

REF

8.2 V < V < 18 V, I

= 2.0 mA

REF

−

1.0 mA < I

(Note 2)

< 10 mA

−

REF

−

T = 1000 Hours, (Note 2)

−

4.0

FAULT Voltage

OK Voltage

Force V

0.90 × V

0.94 × V

0.93 × V

0.96 × V

165

0.95 × V

REF

Force V

0.985 × V

REF

OK Hysteresis

Current Limit

Force V

250

−

REF

−20

−

Error Amplifier

Initial Accuracy

T = 25°C, I

= 2.0 mA, V = 14 V,

= COMP, (Note 2)

2.465

2.515

2.565

REF

Reference Voltage

= COMP

2.440

−

2.515

−0.2

2.590

−2.0

−

MHz

Leakage Current

= 0 V

Open Loop Gain

1.4 V < COMP < 4.0 V, (Note 2)

(Note 2)

Unity Gain Bandwidth

COMP Sink Current

COMP Source Current

COMP High Voltage

COMP Low Voltage

PS Ripple Rejection

1.5

2.0

−0.2

4.35

0.4

2.5

−

COMP = 1.5 V, V = 2.7 V

6.0

−

COMP = 1.5 V, V = 2.3 V

−0.5

4.8

−

= 2.3 V

= 2.7 V

5.0

1.2

−

0.8

FREQ = 120 Hz, (Note 2)

= 2.5 V, V = 0 V, I = 2.0 V

SET

SS Clamp, V

2.4

0.95

2.5

2.6

1.15

COMP

Clamp

(Note 2)

1.0

LIM(SET)

2. Guaranteed by design, not 100% tested in production.

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40°C < T < 85°C, −40°C < T < 150°C,

3.0 V < V < 20 V, 8.2 V < V < 20 V, R = 12 kW, C = 390 pF)

Characteristic

Test Conditions

Min

Typ

Max

Unit

Oscillator

Accuracy

R = 12 k, C = 390 pF

230

−

255

2.0

8.0

−

280

3.0

−

kHz

Voltage Stability

Delta Frequency 8.2 V < V < 20 V

Temperature Stability

< T < T (Note 3)

MAX,

−

MIN

Min Charge & Discharge Time

Duty Cycle Accuracy

Peak Voltage

(Note 3)

0.333

−

R = 12 k, C = 390 pF

−

(Note 3)

−

3.0

1.5

1.4

1.0

Valley Voltage

(Note 3)

−

Valley Clamp Voltage

Discharge Current

10 k Resistor to ground on R C

1.2

0.8

0.925

1.6

1.2

1.075

−

Discharge Current

TA = 25°C, Note 3

Synchronization (CS51021A/3A)

Input Threshold

−

1.0

160

3.5

1.5

260

4.3

2.7

400

4.8

Output Pulsewidth

Output High Voltage

Input Resistance

= 100 mA

SYNC

(Note 3)

140

150

3.5

Drive Delay

SYNC to GATE RESET

1.0 k Load

120

2.0

Output Drive Current

SLEEP (CS51022A/4A)

SLEEP Input Threshold

SLEEP Input Current

1.25

Active High

1.0

−

1.5

2.7

= 4.0 V

SLEEP

@ SLEEP

≤ 15 V

100

GATE Driver

HIGH Voltage

LOW Voltage

Measure V − GATE, V = 10 V, 150 mA Load

−

1.5

1.2

2.2

1.5

Measure GATE − PGND, 150 mA SINK

= 20 V, 1.0 nF

HIGH Voltage Clamp

LOW Voltage Clamp

Peak Current

−

13.5

0.6

Measured at 10 mA Output Current

0.8

−

= 20 V, 1.0 nF, (Note 3)

= 20 V measured at 0 V

−

1.0

UVL Leakage

RISE Time

−

−1.0

−50

100

Load = 1.0 nF, 1.0 V < GATE < 9.0 V,

= 20 V, T = 25°C

−

FALL Time

Load = 1.0 nF, 9.0 V > GATE > 1 .0 V,

= 20 V

−

SLOPE Compensation

Charge Current

SLOPE = 2.0 V

−63

−53

−43

COMP Gain

Fraction of slope voltage added to I

(Note 3)

0.095

0.100

0.105

V/V

SENSE

Discharge Voltage

SYNC = 0 V

−

0.1

0.2

3. Guaranteed by design, not 100% tested in production.

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40°C < T < 85°C, −40°C < T < 150°C,

3.0 V < V < 20 V, 8.2 V < V < 20 V, R = 12 kW, C = 390 pF)

Characteristic

Test Conditions

Min

Typ

Max

Unit

Current Sense

OFFSET Voltage

Blanking Time

(Note 4)

0.09

−

0.10

0.11

160

2.2

−

Blanking Disable Voltage

Adjust V

1.8

1.21

−

2.0

Second Current Threshold Gain

Input Resistance

−

1.33

5.0

1.45

−

V/V

SENSE

Minimum On Time

Gain

GATE High to Low

(Note 4)

110

0.82

0.78

0.80

V/V

OV & UV Voltage Monitors

OV Monitor Threshold

OV Hysteresis Current

UV Monitor Threshold

UV Monitor Hysteresis

SOFT START (SS)

Charge Current

−

2.4

−10

1.38

2.5

−12.5

1.45

2.6

−15

1.52

100

SS = 2.0 V

−70

250

4.4

−55

1000

4.7

−40

−

Discharge Current

Charge Voltage, V

−

5.0

0.30

Discharge Voltage, V

0.25

0.27

4. Guaranteed by design, not 100% tested in production.

PACKAGE PIN DESCRIPTION

PIN #

PIN SYMBOL

FUNCTION

16 Lead SO Narrow

GATE

External power switch driver with 1.0 A peak capability.

Current sense amplifier input.

SENSE

SYNC (CS51021A/3A)

Bi−directional synchronization. Locks to the highest frequency.

SLEEP (CS51022A/4A)

Active high chip disable. In sleep mode, V

and GATE are turned off.

REF

SLOPE

Additional slope to the current sense signal. Internal current source charges the external capacitor.

Undervoltage protection monitor.

Overvoltage protection monitor.

R C

Timing resistor R and capacitor C determine oscillator frequency and maximum duty cycle, D

T T MAX.

Voltage at this pin sets pulse−by−pulse overcurrent threshold, and second threshold (1.33 times

higher) with Soft Start retrigger (hiccup mode).

SET

Feedback voltage input. Connected to the error amplifier inverting input.

COMP

Error amplifier output. Frequency compensation network is usually connected between COMP and

pins.

Charging external capacitor restricts error amplifier output voltage during the start or fault

conditions (hiccup).

LGND

Logic ground.

5.0 V reference voltage output.

Logic supply voltage.

REF

PGND

Output power stage ground connection.

Output power stage supply voltage.

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

REF

_OK

Start

Stop

−

= 5.0 V

REF

−

LGND

REF

_OK

−

SLEEP

SYNC

4.75 V

200 ns

4.3 V

OSC

GATE

R C

Clamp

13.5 V

−

PGND

SET

COMP

Clamp

−

20 k

REF

2.5 V

−

PWM

Comp

E/A

−

55 mA

10 k

−

REF

Monitor

53 mA

2.0 V

−

4.7 V

−

DISABLE

0.1 V

SLOPE

55 ns

Blank

0.1

0.8

−

SENSE

ISENSE

2nd

FAULT

Discharge

Latch

Threshold

1.33

−

SET

REF

12.5 mA

−

Monitor

−

2.5 V

1.45 V

Figure 2. Block Diagram

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

CIRCUIT DESCRIPTION

Current Sense and Protection

The current is monitored at the I

200 ns

4.3 V

pin. The

SENSE

CS51021A/2A/3A/4A has leading edge blanking circuitry

that ignores the first 55 ns of each switching period.

SYNC

R C

Blanking is disabled when V is less than 2.0 V so that the

minimum on−time of the controller does not have an

additional 55 ns of delay time during fault conditions. For

the remaining portion of the switching period, the current

sense signal, combined with a fraction of the slope

compensation voltage, is applied to the positive input of the

PWM comparator where it is compared with the divided by

three error amplifier output voltage. The pulse−by−pulse

overcurrent protection threshold is set by the voltage at the

DIS

0 V

SLOPE

SLOP

0 V

pin. This voltage is passed through the I

Clamp and

IS + 0.1 SLOPE

SET

COMP

appears at the non−inverting input of the PWM comparator,

limiting its dynamic range according to the following

formula:

PWM COMP

GATE

55 ns

Blanking

0 V

0.8 V

Overcurrent Threshold +

I(SENSE)

) 0.1 V ) 0.1 V

SLOPE

where

is voltage at the I pin.

SENSE

I(SENSE)

and

is voltage at the SLOPE pin.

SLOPE

0 V

During extreme overcurrent or short circuit conditions,

the slope of the current sense signal will become much

steeper than during normal operation. Due to loop

propagation delay, the sensed signal will overshoot the

pulse−by−pulse threshold eventually reaching the second

overcurrent protection threshold which is 1.33 times higher

than the first threshold and is described by the following

equation:

Figure 3. Typical Waveforms

THEORY OF OPERATION

Powering the IC

The IC has two supply and two ground pins. V and

PGND pins provide high speed power drive for the external

2nd Threshold + 1.33 V

power switch. V

and LGND pins power the control

I(SET)

portion of the IC. The internal logic monitors the supply

Exceeding the second threshold will reset the Soft Start

voltage, V . During abnormal operating conditions, the

capacitor C

and reinitiate the Soft Start sequence,

output is held low. The CS51021A/2A/3A/4A requires only

75 mA of startup current.

repeating for as long as the fault condition persists.

Soft Start

Voltage Feedback

The output voltage is monitored via the V pin and is

During power up, when the output filter capacitor is

discharged and the output voltage is low, the voltage across

compared with the internal 2.5 V reference. The error

amplifier output minus one diode drop is divided by 3 and

connected to the negative input of the PWM comparator.

The positive input of the PWM comparator is connected to

the modified current sense signal. The oscillator turns the

external power switch on at the beginning of each cycle.

When current sense ramp voltage exceeds the reference side

of PWM comparator, the output stage latches off. It is turned

on again at the beginning of the next oscillator cycle.

the Soft Start capacitor (V ) controls the duty cycle. An

internal current source of 55 mA charges C . The maximum

error amplifier output voltage is clamped by the SS Clamp.

When the Soft Start capacitor voltage exceeds the error

amplifier output voltage, the feedback loop takes over the

duty cycle control. The Soft Start time can be estimated with

the following formula:

+ 9 10⁴ C

The Soft Start voltage, V , charges and discharges

between 0.25 V and 4.7 V.

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

Slope Compensation

where R is a resistor connected from the OV pin to ground.

DC−DC converters with current mode control require a

current sense signal with slope compensation to avoid

instability at duty cycles greater than 50%. Slope capacitor

When the monitored voltage is low and the UV pin is less

than 1.45 V, GATE shuts down. The UV pin has fixed 75 mV

hysteresis.

C is charged by an internal 53 mA current source and is

discharged during the oscillator discharge time. The slope

compensation voltage is divided by 10 and is added to the

Both OV and UV conditions are latched until the Soft Start

capacitor is discharged. This way, every time a fault

condition is detected the controller goes through the power

up sequence.

current sense voltage, V . The signal applied to the

I(SENSE)

input of the PWM comparator is a combination of these two

voltages. The slope compensation, dV

calculated using the following formula:

/dt is

SLOPE

53 mA

SLOPE

+ 0.1

It should be noted that internal capacitance of the IC will

cause an error when determining slope compensation

Figure 5. UV/OV Monitor Divider

capacitance C . This error is typically small for large values

of C , but increases as C becomes small and comparable to

To calculate the OV?UV resistor divider :

the internal capacitance. The effect is apparent as a reduction

in charging current due to the need to charge the internal

1. Solve for R , based on OV hysteresis requirements.

OV(HYST)

2.5 V

capacitance in parallel with C .Figure 4 shows a typical

MAX

12.5 mA

curve indicating this decrease in available charging current.

where

is the desired amount of

OV(HYST)

overvoltage hysteresis, and V

at which the supply will shut down.

is the input voltage

MAX

2. Find the total impedance of the divider.

MAX

TOT

+ R ) R ) R

2.5

3. Determine the value of R from the UV threshold

conditions.

1.45 R

TOT

* R

MIN

where V

will shut down.

is the UV voltage at which the supply

MIN

100

1000

Compensation Cap (pF)

4. Calculate R .

Figure 4. The Slope Compensation Pin Charge

Current Reduces When a Small Capacitor Is Used.

+ R

* R * R

TOT 2 3

5. The undervoltage hysteresis is given by :

MIN

0.075

1.45

Undervoltage (UV) and Overvoltage (OV) Monitor

Two independent comparators monitor OV and UV

conditions. A string of three resistors is connected in series

between the monitored voltage (usually the input voltage)

and ground (see Figure 5). When voltage at the OV pin

exceeds 2.5 V, an overvoltage condition is detected and

GATE shuts down. An internal 12.5 mA current source turns

UV(HYST)

V_REFMonitor

The 5.0 V reference voltage is internally monitored to

ensure that it remains within specifications. The monitor,

which outputs a fault, can be tripped by two methods:

• If the reference voltage drops below 4.75 V

on and feeds current into the external resistor, R , creating

a hysteresis determined by the value of this resistor (the

higher the value, the greater the hysteresis). The hysteresis

voltage of the OV monitor is determined by the following

formula:

• If V falls below the STOP threshold

As indicated in the block diagram, any fault causes the

output to stop switching and begins the discharge of the Soft

Start capacitor C

+ 12.5 mA R

OV(HYST)

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

Synchronization

Oscillator and Duty Cycle Limit

A bi−directional synchronization is provided to synchronize

several controllers. When SYNC pins are connected together,

the converters will lock to the highest switching frequency. The

fastest controller becomes the master, producing a 4.3 V, 200

ns pulse train. Only one, the highest frequency SYNC signal,

will appear on the SYNC line.

The switching frequency is set by R and C connected to

T T

the R C pin. C charges and discharges between 3.0 V and

1.5 V.

The maximum duty cycle is set by the ratio of the on time,

, and the whole period, T = t + t . Because the timing

OFF

capacitor’s discharge current is trimmed, the maximum duty

cycle is well defined. It is determined by the ratio between the

Sleep

timing resistor R and the timing capacitor C . Refer to figures

The sleep input is an active high input. The CS51022A/4A

is placed in sleep mode when SLEEP is driven high. In sleep

mode, the controller and MOSFET are turned off. Connect

to GND for normal operation. The sleep mode operates at

VCC ≤ 15 V.

6 and 7 to select appropriate values for R and C .

; T

+ t

) t

DIS

2500

100

1. C = 47 pF

2. C = 100 pF

2000

1500

1000

500

3. C = 150 pF

4. C = 220 pF

5. C = 390 pF

1. C = 47 pF

6. C = 470 pF

2. C = 100 pF

7. C = 560 pF

3. C = 150 pF

8. C = 680 pF

4. C = 220 pF

5. C = 390 pF

6. C = 470 pF

7. C = 560 pF

8. C = 680 pF

15 20 25 30 35

R (kW)

40 45

10 15

20 25 30 35 40 45 50 55

R (kW)

Figure 6. Frequency vs. R_Tfor Discrete

Capacitor Values

Figure 7. Duty Cycle vs. R_Tfor Discrete

Capacitor Values

ORDERING INFORMATION

Device

†

Package

Shipping

CS51021AED16

48 Units / Rail

SOIC−16

CS51021AEDR16

CS51021AEDR16G

2500 Tape & Reel

SOIC−16

(Pb−Free)

CS51022ADBG

TSSOP−16*

48 Units / Rail

2500 Tape & Reel

48 Units / Rail

CS51022ADBR2G

CS51022AED16

CS51022AEDR16

CS51022AEDR16G

SOIC−16

2500 Tape & Reel

48 Units / Rail

SOIC−16

(Pb−Free)

CS51023AED16

SOIC−16

CS51023AEDR16

CS51023AEDR16G

2500 Tape & Reel

SOIC−16

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

CASE 751B−05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−A−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

−B−

P 8 PL

0.25 (0.010)

MILLIMETERS

INCHES

MIN

DIM MIN

MAX

10.00

4.00

1.75

0.49

1.25

MAX

0.393

0.157

0.068

0.019

0.049

9.80

3.80

1.35

0.35

0.40

0.386

0.150

0.054

0.014

0.016

R X 45

1.27 BSC

0.050 BSC

0.19

0.10

0.25

0.008

0.004

0.009

−T−

SEATING

PLANE

5.80

0.25

6.20

0.50

0.229

0.010

0.244

0.019

16 PL

0.25 (0.010)

T B

PACKAGE THERMAL DATA

Parameter

SOIC−16

Unit

Typical

°C/W

115

http://onsemi.com

CS51021A, CS51022A, CS51023A, CS51024A

TSSOP−16

CASE 948F−01

ISSUE A

NOTES:

16X KREF

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

0.10 (0.004)

T U

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

0.15 (0.006) T U

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

2X L/2

−U−

PIN 1

IDENT.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

0.15 (0.006) T U

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

−V−

4.90

4.30

−−−

0.05

0.50

5.10 0.193 0.200

4.50 0.169 0.177

1.20

−−− 0.047

0.15 0.002 0.006

0.75 0.020 0.030

0.25 (0.010)

0.65 BSC

0.026 BSC

0.18

0.09

0.19

0.28 0.007 0.011

0.20 0.004 0.008

0.16 0.004 0.006

0.30 0.007 0.012

0.25 0.007 0.010

6.40 BSC

0.252 BSC

SECTION N−N

DETAIL E

−W−

0.10 (0.004)

DETAIL E

SEATING

PLANE

−T−

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

Literature Distribution Center for ON Semiconductor

P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada

Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

For additional information, please contact your

local Sales Representative.

CS51021/D

http://onsemi.com

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CS51021AEDR16产品参数

型号:	CS51021AEDR16
生命周期：	Obsolete
包装说明：	0.150 INCH, SO-16
Reach Compliance Code：	unknown
风险等级：	5.74
Is Samacsys：	N
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	20 V
最小输入电压：	8.2 V
标称输入电压：	14 V
JESD-30 代码：	R-PDSO-G16
功能数量：	1
端子数量：	16
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	1 A
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
认证状态：	Not Qualified
表面贴装：	YES
切换器配置：	SINGLE
最大切换频率：	1000 kHz
温度等级：	INDUSTRIAL
端子形式：	GULL WING
端子位置：	DUAL
Base Number Matches：	1

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