CS51413E各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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SO–8

The CS5141X products are 1.5 A buck regulator ICs. These devices

are fixed–frequency operating at 260 kHz and 520 kHz. The regulators

use the V  control architecture to provide unmatched transient

D SUFFIX

CASE 751

8

1

2

response, the best overall regulation and the simplest loop

compensation for today’s high–speed logic. These products

accommodate input voltages from 4.5 V to 40 V.

MARKING DIAGRAM

8

The CS51411 and CS51413 contain synchronization circuitry. The

CS51412 and CS51414 have the option of powering the controller

from an external 3.3 V to 6.0 V supply in order to improve efficiency,

especially in high input voltage, light load conditions.

The on–chip NPN transistor is capable of providing a minimum of

1.5 A of output current, and is biased by an external “boost” capacitor

to ensure saturation, thus minimizing on–chip power dissipation.

Protection circuitry includes thermal shutdown, cycle–by–cycle

current limiting and frequency foldback. The CS51411 and CS51413

are functionally pin–compatible with the LT1375. The CS51412 and

CS51414 are functionally pin–compatible with the LT1376.

5141X

ALYWT

1

X

A

WL, L

YY, Y

= 1, 2, 3 or 4

= Assembly Location

= Wafer Lot

= Year

WW, W = Work Week

= Temperature Range, E or G

T

Features

PIN CONNECTIONS

CS51411/3

2

• V Architecture Provides Ultra–Fast Transient Response, Improved

Regulation and Simplified Design

1

8

• 2.0% Error Amp Reference Voltage Tolerance

BOOST

V

C

• Switch Frequency Decrease of 4:1 in Short Circuit Conditions

V

IN

FB

Reduces Short Circuit Power Dissipation

V

SW

GND

• BOOST Lead Allows “Bootstrapped” Operation to Maximize

Efficiency

• Sync Function for Parallel Supply Operation or Noise Minimization

• Shutdown Lead Provides Power–Down Option

• 85 µA Quiescent Current During Power–Down

• Thermal Shutdown

• Soft Start

• Pin–Compatible with LT1375 and LT1376

SHDNB

SYNC

CS51412/4

1

8

BOOST

V

C

V

IN

FB

V

SW

GND

BIAS

SHDNB

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 14 of this data sheet.

 Semiconductor Components Industries, LLC, 2002

1

Publication Order Number:

September, 2002 – Rev. 11

CS51411/D

CS51411, CS51412, CS51413, CS51414

PRODUCT SELECTION GUIDE

Part Number

CS51411E

Frequency

260 kHz

520 kHz

Temperature Range

–40°C to 85°C

0°C to 70°C

Bias/Sync

Sync

Bias

CS51411G

CS51412E

–40°C to 85°C

0°C to 70°C

CS51412G

Bias

CS51413E

–40°C to 85°C

0°C to 70°C

Sync

Bias

CS51413G

CS51414E

–40°C to 85°C

0°C to 70°C

CS51414G

Bias

1N4148

D1

C1

4.5 V – 16 V

0.1 µF

C2

100 µF

1

U1

2

3

V

3.3 V

BOOST

IN

V

SW

L1

15 µH

4

5

Shutdown

SYNC

SHDNB

CS51411/3

R1

205

C3

D3

1N5821

SYNC

100 µF

V

C

GND

V

7

FB

8

6

R2

127

C4

0.1 µF

Figure 1. Application Diagram, 4.5 V – 16 V to 3.3 V @ 1.0 A Converter

MAXIMUM RATINGS*

Rating

Value

–40 to 150

230 peak

–65 to +150

2.0

Unit

°C

Operating Junction Temperature Range, T

Lead Temperature Soldering:

J

Reflow: (SMD styles only) (Note 1)

°C

Storage Temperature Range, T

°C

S

ESD Damage Threshold (Human Body Model)

kV

1. 60 second maximum above 183°C.

*The maximum package power dissipation must be observed.

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2

CS51411, CS51412, CS51413, CS51414

MAXIMUM RATINGS

Pin Name

V

Max

V

MIN

I

SINK

SOURCE

V

40 V

7.0 V

–0.3 V

N/A

4.0 A

100 mA

10 mA

1.0 mA

50 mA

1.0 mA

IN

BOOST

N/A

V

SW

–0.6 V/–1.0 V, t < 50 ns

–0.3 V

4.0 A

V

1.0 mA

50 mA

C

SHDNB

SYNC

BIAS

–0.3 V

V

FB

–0.3 V

GND

–0.3 V

ELECTRICAL CHARACTERISTICS (–40°C < T < 125°C (CS51411E/2E/3E/4E); –40°C < T < 85°C (CS51411E/2E/3E/4E);

J

A

0°C < T < 70°C (CS51411G/2G/3G/4G), 4.5 V< V < 40 V; unless otherwise specified.)

A

IN

Characteristic

Test Conditions

Min

Typ

Max

Unit

Oscillator

Operating Frequency

Frequency Line Regulation

Maximum Duty Cycle

CS51411/CS51412

CS51413/CS51414

224

446

–

260

520

0.05

90

296

594

0.15

95

kHz

%/V

%

–

85

V

FB

Frequency Foldback Threshold

0.29

0.32

0.36

V

PWM Comparator

Slope Compensation Voltage

CS51411/CS51412, Fix V ∆V /∆T

ON

CS51413/CS51414

8.0

25

17

50

26

75

mV/µs

FB,

C

Minimum Output Pulse Width

CS51411/CS51412, V to V

–

150

–

300

230

ns

FB

SW

CS51413/CS51414, V to V

FB

SW

Power Switch

Current Limit

V

> 0.36 V

< 0.29 V

= 1.5 A, V

1.6

0.9

0.4

–

2.3

1.5

0.7

120

3.0

2.1

1.0

160

A

FB

Foldback Current

FB

Saturation Voltage

Current Limit Delay

Error Amplifier

I

= V + 2.5 V

V

OUT

BOOST

IN

Note 2

ns

Internal Reference Voltage

Reference PSRR

–

1.244

–

1.270

40

1.296

–

V

dB

Note 2

FB Input Bias Current

Output Source Current

Output Sink Current

Output High Voltage

Output Low Voltage

Unity Gain Bandwidth

Open Loop Amplifier Gain

Amplifier Transconductance

–

0.02

25

0.1

35

1.53

60

–

µA

V

= 1.270 V, V = 1.0 V

15

1.39

5.0

–

µA

C

FB

= 1.270 V, V = 2.0 V

25

µA

C

FB

= 1.0 V

= 2.0 V

1.46

20

V

FB

mV

kHz

dB

Note 2

500

70

–

6.4

–

mA/V

2. Guaranteed by design, not 100% tested in production.

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3

CS51411, CS51412, CS51413, CS51414

ELECTRICAL CHARACTERISTICS (continued) (–40°C < T < 125°C (CS51411E/2E/3E/4E); –40°C < T < 85°C (CS51411E/2E/3E/4E);

J

A

0°C < T < 70°C (CS51411G/2G/3G/4G), 4.5 V< V < 40 V; unless otherwise specified.)

A

IN

Characteristic

Test Conditions

Min

Typ

Max

Unit

Sync

Sync Frequency Range

Sync Pin Bias Current

CS51411/CS51412

CS51413/CS51414

305

575

–

470

880

kHz

V

SYNC

V

SYNC

= 0 V

= 5.0 V

–

250

0.1

360

0.2

460

µA

Sync Threshold Voltage

–

1.0

1.5

1.9

V

Shutdown

Shutdown Threshold Voltage

–

1.0

1.3

1.6

35

V

Shutdown Pin Bias Current

V

= 0 V

0.14

5.00

µA

SHDNB

Thermal Shutdown

Overtemperature Trip Point

Note 3

175

185

42

195

°C

Thermal Shutdown Hysteresis

General

–

Quiescent Current

I

= 0 A

3.0

8.0

6.0

–

4.0

20

15

–

6.25

85

mA

µA

SW

Shutdown Quiescent Current

Boost Operating Current

Minimum Boost Voltage

Start up Voltage

V

= 0 V

SHDNB

BOOST

V

– V

= 2.5 V

40

mA/A

V

SW

Note 3

2.5

4.4

12

–

2.2

–

3.3

7.0

V

Minimum Output Current

mA

3. Guaranteed by design, not 100% tested in production.

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

PIN SYMBOL

FUNCTION

1

BOOST

The BOOST pin provides additional drive voltage to the on–chip NPN power transistor.

The resulting decrease in switch on voltage increases efficiency.

2

3

V

This pin is the main power input to the IC.

IN

V

SW

This is the connection to the emitter of the on–chip NPN power transistor and serves

as the switch output to the inductor. This pin may be subjected to negative voltages

during switch off–time. A catch diode is required to clamp the pin voltage in normal

operation. This node can stand –1.0 V for less than 50 ns during switch node flyback.

4 (CS51412/CS51414)

5 (CS51411/CS51413)

BIAS

The BIAS pin connects to the on–chip power rail and allows the IC to run most of its

internal circuitry from the regulated output or another low voltage supply to improve

efficiency. The BIAS pin is left floating if this feature is not used.

SYNC

This pin provides the synchronization input.

5 (CS51412/CS51414)

4 (CS51411/CS51413)

SHDNB

The shutdown pin is active low and TTL compatible. The IC goes into sleep mode,

drawing less than 85 µA when the pin voltage is pulled below 1.0 V. This pin should be

left floating in normal position.

6

7

GND

Power return connection for the IC.

V

FB

The FB pin provides input to the inverting input of the error amplifier. If V is lower

FB

than 0.29 V, the oscillator frequency is divided by four, and current limit folds back to

about 1 ampere. These features protect the IC under severe overcurrent or short

circuit conditions.

8

V

C

The V pin provides a connection point to the output of the error amplifier and input to

the PWM comparator. Driving of this pin should be avoided because on–chip test

C

circuitry becomes active whenever current exceeding 0.5 mA is forced into the IC.

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4

CS51411, CS51412, CS51413, CS51414

SHDNB

SYNC

V

IN

5.0 µA

Shutdown

Comparator

+

2.9 V LDO

Voltage

Regulator

Thermal

Shutdown

Artificial

Ramp

Oscillator

BIAS

BOOST

–

+

–

1.3 V

Output

Driver

S

R

Q

V

SW

∑

+

Current

Limit

–

Comparator

+

PWM

Comparator

I

REF

1.46 V

–

V

FB

–

+

I

FOLDBACK

+

–

Frequency

+

GND

0.32 V

and Current

Limit Foldback

+

–

1.270 V

Error

Amplifier

V

C

Figure 2. Block Diagram

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CS51411, CS51412, CS51413, CS51414

APPLICATIONS INFORMATION

THEORY OF OPERATION

The slope compensation signal is a fixed voltage ramp

provided by the oscillator. Adding this signal eliminates

subharmonic oscillation associated with the operation at

duty cycle greater than 50%. The artificial ramp also ensures

the proper PWM function when the output ripple voltage is

inadequate. The slope compensation signal is properly sized

to serve it purposes without sacrificing the transient

response speed.

Under load and line transient, not only the ramp signal

changes, but more significantly the DC component of the

feedback voltage varies proportionally to the output voltage.

FFB path connects both signals directly to the PWM

comparator. This allows instant modulation of the duty cycle

to counteract any output voltage deviations. The transient

response time is independent of the error amplifier

bandwidth. This eliminates the delay associated with error

amplifier and greatly improves the transient response time.

The error amplifier is used here to ensure excellent DC

accuracy.

V²Control

The CS5141X family of buck regulators provides leading

edge technology, a high level of integration and high

operating frequencies allowing the layout of a switch–mode

power supply in a very small board area. These devices are

based on the proprietary V control architecture. V control

uses the output voltage and its ripple as the ramp signal,

providing an ease of use not generally associated with

voltage or current mode control. Improved line regulation,

load regulation and very fast transient response are also

major advantages.

2

S1

L1

V

IN

V

O

R1

C1

Duty Cycle

D1

Buck

Controller

Error Amplifier

Slope

Comp

The CS5141X has a transconductance error amplifier,

whose non–inverting input is connected to an Internal

Reference Voltage generated from the on–chip regulator.

Oscillator

+

FFB

The inverting input connects to the V pin. The output of

FB

Latch

R

S

the error amplifier is made available at the V pin. A typical

C

frequency compensation requires only a 0.1 µF capacitor

R2

+

−

SFB

connected between the V pin and ground, as shown in

C

−

+

V

C

Figure 1. This capacitor and error amplifier’s output

resistance (approximately 8.0 MΩ) create a low frequency

V

REF

PWM

Comparator

+

2

pole to limit the bandwidth. Since V control does not

–

Error

Amplifier

require a high bandwidth error amplifier, the frequency

compensation is greatly simplified.

2

V

Control

The V pin is clamped below Output High Voltage. This

C

allows the regulator to recover quickly from over current or

short circuit conditions.

Figure 3. Buck Converter with V²Control.

As shown in Figure 3, there are two voltage feedback

paths in V control, namely FFB(Fast Feedback) and

Oscillator and Sync Feature (CS51411 and CS51413 only)

The on–chip oscillator is trimmed at the factory and

requires no external components for frequency control. The

high switching frequency allows smaller external

components to be used, resulting in a board area and cost

savings. The tight frequency tolerance simplifies magnetic

components selection. The switching frequency is reduced

2

SFB(Slow Feedback). In FFB path, the feedback voltage

connects directly to the PWM comparator. This feedback

path carries the ramp signal as well as the output DC voltage.

Artificial ramp derived from oscillator is added to the

feedback signal to improve stability. The other feedback

path SFB connects the feedback voltage to the error

to 25% of the nominal value when the V pin voltage is

FB

amplifier whose output V feeds to the other input of the

C

below Frequency Foldback Threshold. In short circuit or

over–load conditions, this reduces the power dissipation of

the IC and external components.

PWM comparator. In a constant frequency mode, the

oscillator signal sets the output latch and turns on the switch

S1. This starts a new switch cycle. The ramp signal,

composed of both artificial ramp and output ripple,

An external clock signal can sync CS51411/CS51414 to

a higher frequency. The rising edge of the sync pulse turns

on the power switch to start a new switching cycle, as shown

in Figure 4. There is approximately 0.5 µs delay between the

eventually comes across the V voltage, and consequently

C

resets the latch to turn off the switch. The switch S1 will turn

on again at the beginning of the next switch cycle. In a buck

converter, the output ripple is determined by the ripple

current of the inductor L1 and the ESR (equivalent series

resistor) of the output capacitor C1.

rising edge of the sync pulse and rising edge of the V pin

SW

voltage. The sync threshold is TTL logic compatible, and

duty cycle of the sync pulses can vary from 10% to 90%. The

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CS51411, CS51412, CS51413, CS51414

frequency foldback feature is disabled during the sync

mode.

components. When the peak of the switching current reaches

the Current Limit, the power switch turns off after the

Current Limit Delay. The switch will not turn on until the

next switching cycle. The current limit threshold is

independent of switching duty cycle. The maximum load

current, given by the following formula under continuous

conduction mode, is less than the Current Limit due to the

ripple current.

V (V * V )

IN

O

I

+ I *

LIM

O(MAX)

2(L)(V )(f )

IN

s

where:

f = switching frequency,

S

I

= current limit threshold,

LIM

V = output voltage,

O

V

IN

= input voltage,

L = inductor value.

When the regulator runs under current limit, the

subharmonic oscillation may cause low frequency

oscillation, as shown in Figure 6. Similar to current mode

control, this oscillation occurs at the duty cycle greater than

50% and can be alleviated by using a larger inductor value.

The current limit threshold is reduced to Foldback Current

when the FB pin falls below Foldback Threshold. This

feature protects the IC and external components under the

power up or over–load conditions.

Figure 4. A CS51411 Buck Regulator is Synced by an

External 350 kHz Pulse Signal

Power Switch and Current Limit

The collector of the built–in NPN power switch is

connected to the V pin, and the emitter to the V pin.

IN

SW

When the switch turns on, the V voltage is equal to the

SW

V

IN

minus switch Saturation Voltage. In the buck regulator,

the V

voltage swings to one diode drop below ground

SW

when the power switch turns off, and the inductor current is

commutated to the catch diode. Due to the presence of high

pulsed current, the traces connecting the V pin, inductor

SW

and diode should be kept as short as possible to minimize the

noise and radiation. For the same reason, the input capacitor

should be placed close to the V pin and the anode of the

IN

diode.

The saturation voltage of the power switch is dependent

on the switching current, as shown in Figure 5.

0.7

0.6

0.5

0.4

0.3

0.2

Figure 6. The Regulator in Current Limit

BOOST Pin

The BOOST pin provides base driving current for the

power switch. A voltage higher than V provides required

IN

headroom to turn on the power switch. This in turn reduces

IC power dissipation and improves overall system

efficiency. The BOOST pin can be connected to an external

boost–strapping circuit which typically uses a 0.1 µF capacitor

and a 1N914 or 1N4148 diode, as shown in Figure 1. When the

power switch is turned on, the voltage on the BOOST pin is

equal to

0.1

0

0.5

1.0

1.5

Switching Current (A)

Figure 5. The Saturation Voltage of the Power Switch

Increases with the Conducting Current

V

+ V ) V * V

IN F

BOOST

O

Members of the CS5141X family contain pulse–by–pulse

current limiting to protect the power switch and external

where:

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7

CS51411, CS51412, CS51413, CS51414

2

V = diode forward voltage.

to the inductor, IC and catch diode. In V control , the

compensation capacitor provides Soft Start with no need for

extra pin or circuitry. During the power up, the Output

Source Current of the error amplifier charges the

F

The anode of the diode can be connected to any DC voltage

other than the regulated output voltage. However, the

maximum voltage on the BOOST pin shall not exceed 40 V.

As shown in Figure 7, the BOOST pin current includes a

constant 7.0 mA pre–driver current and base current

proportional to switch conducting current. A detailed

discussion of this current is conducted in Thermal

Consideration section. A 0.1 µF capacitor is usually

adequate for maintaining the Boost pin voltage during the on

time.

compensation capacitor which forces V pin and thus output

voltage ramp up gradually. The Soft Start duration can be

calculated by

C

V

C

I

COMP

T

+

SS

SOURCE

where:

V = V pin steady–state voltage, which is approximately

C

equal to error amplifier’s reference voltage.

30

25

20

15

C

I

= Compensation capacitor connected to the V pin

COMP

C

= Output Source Current of the error amplifier.

SOURCE

Using a 0.1 µF C

, the calculation shows a T over

SS

5.0 ms which is adequate to avoid any current stresses.

COMP

Figure 8 shows the gradual rise of the V , V and envelope

C

O

of the V during power up. There is no voltage over–shoot

SW

after the output voltage reaches the regulation. If the supply

10

5

voltage rises slower than the V pin, output voltage may

C

over–shoot.

0

0.5

1.0

1.5

Switching Current (A)

Figure 7. The Boost Pin Current Includes 7.0 mA

Pre–Driver Current and Base Current when the

Switch is Turned On. The Beta Decline of the

Power Switch Further Increases the Base

Current at High Switching Current

BIAS Pin (CS51412 and CS51414 Only)

The BIAS pin allows a secondary power supply to bias the

control circuitry of the IC. The BIAS pin voltage should be

between 3.3 V and 6.0 V. If the BIAS pin voltage falls below

that range, use a diode to prevent current drain from the

BIAS pin. Powering the IC with a voltage lower than the

regulator’s input voltage reduces the IC power dissipation

and improves energy transfer efficiency.

Figure 8. The Power Up Transition of CS5141X

Regulator

Short Circuit

When the V

Shutdown

pin voltage drops below Foldback

FB

The internal power switch will not turn on until the V

IN

Threshold, the regulator reduces the peak current limit by

40% and switching frequency to 1/4 of the nominal

frequency. These features are designed to protect the IC and

external components during over load or short circuit

conditions. In those conditions, peak switching current is

clamped to the current limit threshold. The reduced

switching frequency significantly increases the ripple

current, and thus lowers the DC current. The short circuit can

cause the minimum duty cycle to be limited by Minimum

Output Pulse Width. The foldback frequency reduces the

minimum duty cycle by extending the switching cycle. This

protects the IC from overheating, and also limits the power

that can be transferred to the output. The current limit

foldback effectively reduces the current stress on the

pin rises above the Start Up Voltage. This ensures no

switching until adequate supply voltage is provided to the

IC.

The IC enters a sleep mode when the SHDNB pin is pulled

below Shutdown Threshold Voltage. In the sleep mode, the

power switch keeps open and the supply current reduces to

Shutdown Quiescent Current. This pin has internal pull–up

current. So when this pin is not used, leave the SHDNB pin

open.

Start–Up

During power up, the regulator tends to quickly charge up

the output capacitors to reach voltage regulation. This gives

rise to an excessive in–rush current which can be detrimental

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8

CS51411, CS51412, CS51413, CS51414

inductor and diode. When the output is shorted, the DC

current when the transistor needs to be on. The power

dissipated by the IC due to this current is

current of the inductor and diode can approach the current

limit threshold. Therefore, reducing the current limit by 40%

can result in an equal percentage drop of the inductor and

diode current. The short circuit waveforms are captured in

Figure 9, and the benefit of the foldback frequency and

current limit is self–evident.

2

V

I

S

60

O

W

+

BASE

IN

where:

I = DC switching current.

S

When the power switch turns on, the saturation voltage

and conduction current contribute to the power loss of a

non–ideal switch. The power loss can be quantified as

V

O

W

+

I V

S SAT

SAT

V

IN

where:

V

SAT

= saturation voltage of the power switch which is

shown in Figure 5.

The switching loss occurs when the switch experiences

both high current and voltage during each switch transition.

This regulator has a 30 ns turn–off time and associated

power loss is equal to

I

S

V

2

IN

W

+

20 ns f

S

Figure 9. In Short Circuit, the Foldback Current and

Foldback Frequency Limit the Switching Current to

Protect the IC, Inductor and Catch Diode

The turn–on time is much shorter and thus turn–on loss is

not considered here.

The total power dissipated by the IC is sum of all the above

W

+ W ) W

) W

SAT S

IC

Q

DRV

BASE

Thermal Considerations

A calculation of the power dissipation of the IC is always

necessary prior to the adoption of the regulator. The current

drawn by the IC includes quiescent current, pre–driver

current, and power switch base current. The quiescent

current drives the low power circuits in the IC, which

include comparators, error amplifier and other logic blocks.

Therefore, this current is independent of the switching

current and generates power equal to

The IC junction temperature can be calculated from the

ambient temperature, IC power dissipation and thermal

resistance of the package. The equation is shown as follows,

T + W R

J IC

) T

A

qJA

The maximum IC junction temperature shall not exceed

125°C to guarantee proper operation and avoid any damages

to the IC.

W

+ V I

IN

Q

Minimum Load Requirement

As pointed out in the previous section, a minimum load is

required for this regulator due to the pre–driver current

where:

I = quiescent current.

Q

feeding the output. Placing a resistor equal to V divided by

O

The pre–driver current is used to turn on/off the power

switch and is approximately equal to 12 mA in worst case.

During steady state operation, the IC draws this current from

the Boost pin when the power switch is on and then receives

12 mA should prevent any voltage overshoot at light load

conditions. Alternatively, the feedback resistors can be

valued properly to consume 12 mA current.

it from the V pin when the switch is off. The pre–driver

IN

COMPONENT SELECTION

current always returns to the V pin. Since the pre–driver

SW

current goes out to the regulator’s output even when the

power switch is turned off, a minimum load is required to

prevent overvoltage in light load conditions. If the Boost pin

Input Capacitor

In a buck converter, the input capacitor witnesses pulsed

current with an amplitude equal to the load current. This

pulsed current and the ESR of the input capacitors determine

voltage is equal to V + V when the switch is on, the power

IN

O

dissipation due to pre–driver current can be calculated by

the V ripple voltage, which is shown in Figure 10. For V

IN

2

ripple, low ESR is a critical requirement for the input

capacitor selection. The pulsed input current possesses a

significant AC component, which is absorbed by the input

capacitors. The RMS current of the input capacitor can be

calculated using:

V

O

W

+ 12 mA (V * V

IN

)

O

)

DRV

IN

The base current of a bipolar transistor is equal to collector

current divided by beta of the device. Beta of 60 is used here

to estimate the base current. The Boost pin provides the base

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9

CS51411, CS51412, CS51413, CS51414

Selecting the capacitor type is determined by each

Ǹ

D(1 * D)

O

I

+ I

RMS

design’s constraint and emphasis. The aluminum

electrolytic capacitors are widely available at lowest cost.

Their ESR and ESL (equivalent series inductor) are

relatively high. Multiple capacitors are usually paralleled to

achieve lower ESR. In addition, electrolytic capacitors

usually need to be paralleled with a ceramic capacitor for

filtering high frequency noises. The OS–CON are solid

aluminum electrolytic capacitors, and therefore has a much

lower ESR. Recently, the price of the OS–CON capacitors

has dropped significantly so that it is now feasible to use

them for some low cost designs. Electrolytic capacitors are

physically large, and not used in applications where the size,

and especially height is the major concern.

where:

D = switching duty cycle which is equal to V /V .

I = load current.

O

IN

Ceramic capacitors are now available in values over 10 µF.

Since the ceramic capacitor has low ESR and ESL, a single

ceramic capacitor can be adequate for both low frequency

and high frequency noises. The disadvantage of ceramic

capacitors are their high cost. Solid tantalum capacitors can

have low ESR and small size. However, the reliability of the

tantalum capacitor is always a concern in the application

where the capacitor may experience surge current.

Figure 10. Input Voltage Ripple in a Buck Converter

To calculate the RMS current, multiply the load current

with the constant given by Figure 11 at each duty cycle. It is

a common practice to select the input capacitor with an RMS

current rating more than half the maximum load current. If

multiple capacitors are paralleled, the RMS current for each

capacitor should be the total current divided by the number

of capacitors.

Output Capacitor

In a buck converter, the requirements on the output

capacitor are not as critical as those on the input capacitor.

The current to the output capacitor comes from the inductor

and thus is triangular. In most applications, this makes the

RMS ripple current not an issue in selecting output

capacitors.

The output ripple voltage is the sum of a triangular wave

caused by ripple current flowing through ESR, and a square

wave due to ESL. Capacitive reactance is assumed to be

small compared to ESR and ESL. The peak to peak ripple

current of the inductor is:

0.6

0.5

0.4

V (V * V )

IN

O

I

+

P * P

(V )(L)(f )

IN

S

0.3

0.2

V

, the output ripple due to the ESR, is equal

RIPPLE(ESR)

to the product of I

and ESR. The voltage developed

P–P

across the ESL is proportional to the di/dt of the output

capacitor. It is realized that the di/dt of the output capacitor

is the same as the di/dt of the inductor current. Therefore,

when the switch turns on, the di/dt is equal to (V – V )/L,

and it becomes V /L when the switch turns off. The total

0.1

0

IN

O

0

0.2

0.4

0.6

Duty Cycle

0.8

1.0

O

ripple voltage induced by ESL can then be derived from

Figure 11. Input Capacitor RMS Current can be

Calculated by Multiplying Y Value with Maximum Load

Current at any Duty Cycle

V

IN

* V

L

V

L

V

IN

L

O

IN

V

+ ESL(

) ) ESL(

) + ESL(

)

RIPPLE(ESL)

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10

CS51411, CS51412, CS51413, CS51414

The total output ripple is the sum of the V

and

RIPPLE(ESR)

V

.

RIPPLE(ESR)

Figure 15. The Output Voltage Ripple Using

One 100 mF Tantalum Capacitor

Figure 12 to Figure 15 show the output ripple of a 5.0 V

to 3.3 V/500 mA regulator using 22 µH inductor and various

capacitor types. At the switching frequency, the low ESR

and ESL make the ceramic capacitors behave capacitively

as shown in Figure 12. Additional paralleled ceramic

capacitors will further reduce the ripple voltage, but

inevitably increase the cost. “POSCAP”, manufactured by

SANYO, is a solid electrolytic capacitor. The anode is

sintered tantalum and the cathode is a highly conductive

polymerized organic semiconductor. TPC series, featuring

low ESR and low profile, is used in the measurement of

Figure 13. It is shown that POSCAP presents a good balance

of capacitance and ESR, compared with a ceramic capacitor.

In this application, the low ESR generates less than 5.0 mV

of ripple and the ESL is almost unnoticeable. The ESL of the

through–hole OS–CON capacitor give rise to the inductive

impedance. It is evident from Figure 14 which shows the

step rise of the output ripple on the switch turn–on and large

spike on the switch turn–off. The ESL prevents the output

capacitor from quickly charging up the parasitic capacitor of

the inductor when the switch node is pulled below ground

through the catch diode conduction. This results in the spike

associated with the falling edge of the switch node. The D

package tantalum capacitor used in Figure 15 has the same

footprint as the POSCAP, but doubles the height. The ESR

of the tantalum capacitor is apparently higher than the

POSCAP. The electrolytic and tantalum capacitors provide

a low–cost solution with compromised performance. The

reliability of the tantalum capacitor is not a serious concern

for output filtering because the output capacitor is usually

free of surge current and voltage.

Figure 12. The Output Voltage Ripple Using Two 10 mF

Ceramic Capacitors in Parallel

Figure 13. The Output Voltage Ripple Using One 100 mF

POSCAP Capacitor

Diode Selection

The diode in the buck converter provides the inductor

current path when the power switch turns off. The peak

reverse voltage is equal to the maximum input voltage. The

peak conducting current is clamped by the current limit of

the IC. The average current can be calculated from:

Figure 14. The Output Voltage Ripple Using

One 100 mF OS–CON

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11

CS51411, CS51412, CS51413, CS51414

The DC current through the inductor is equal to the load

I (V * V )

IN

O

I

+

D(AVG)

current. The worse case occurs during maximum load

current. Check the vendor’s spec to adjust the inductor value

under current loading. Inductors can lose over 50% of

inductance when it nears saturation.

V

IN

The worse case of the diode average current occurs during

maximum load current and maximum input voltage. For the

diode to survive the short circuit condition, the current rating

of the diode should be equal to the Foldback Current Limit.

See Table 1 for schottky diodes from ON Semiconductor

which are suggested for CS5141X regulator.

The core materials have a significant effect on inductor

performance. The ferrite core has benefits of small physical

size, and very low power dissipation. But be careful not to

operate these inductors too far beyond their maximum

ratings for peak current, as this will saturate the core.

Powered Iron cores are low cost and have a more gradual

saturation curve. The cores with an open magnetic path, such

as rod or barrel, tend to generate high magnetic field

radiation. However, they are usually cheap and small. The

cores providing a close magnetic loop, such as pot–core and

toroid, generate low electro–magnetic interference (EMI).

There are many magnetic component vendors providing

standard product lines suitable for CS5141X. Table 2 lists

three vendors, their products and contact information.

Inductor Selection

When choosing inductors, one might have to consider

maximum load current, core and copper losses, component

height, output ripple, EMI, saturation and cost. Lower

inductor values are chosen to reduce the physical size of the

inductor. Higher value cuts down the ripple current, core

losses and allows more output current. For most

applications, the inductor value falls in the range between

2.2 µH and 22 µH. The saturation current ratings of the

inductor shall not exceed the I

, calculated according to

L(PK)

V (V * V )

IN

O

I

+ I

)

L(PK)

O

2(f )(L)(V

)

S

IN

Table 1.

Part Number

1N5817

V

(V)

I

(A)

V

(F)

(V) @ I

AVERAGE

Package

Axial Lead

SOD–123

SMB

BREAKDOWN

AVERAGE

20

1.0

0.45

0.55

0.6

1N5818

30

40

20

30

40

20

30

40

1.0

0.5

1.0

1N5819

MBR0520

MBR0530

MBR0540

MBRS120

MBRS130

MBRS140

0.385

0.43

0.53

0.55

0.395

0.6

SMB

Table 2.

Vendor

Product Family

Web Site

Telephone

Coiltronics

UNI–Pac1/2: SMT, barrel

www.coiltronics.com

(516) 241–7876

THIN–PAC: SMT, toroid, low profile

CTX: Leaded, toroid

Coilcraft

Pulse

DO1608: SMT, barrel

DS/DT 1608: SMT, barrel, magnetically shielded

DO3316: SMT, barrel

DS/DT 3316: SMT, barrel, magnetically shielded

DO3308: SMT, barrel, low profile

www.coilcraft.com

(800) 322–2645

(619) 674–8100

–

www.pulseeng.com

http://onsemi.com

12

CS51411, CS51412, CS51413, CS51414

R2

373

U1

7

V

5.0 V – 12 V input

C5

0.1 µF

D2

L1

2

4

FB

V

IN

1N4148

1

3

BOOST

C1

22 µF

SHDNB

CS51411/3

V

SW

5

15 µH

R3

SYNC

V

C

GND

6

127

D1

MBR0520

C6

22 µ

8

C2

0.1 µF

–5.0 V output

C3

C4

0.01 µF

R1

50 k

0.1 µF

Figure 16. Additional Application Diagram, 5.0 V – 12 V to –5.0 V/400 mA Inverting Converter

1N4148

D2

1N4148

D1

12 V

C1

0.1 µF

C1

100 µF

U1

2

V

1

4

3

BIAS

BOOST

5.0 V

IN

V

SW

L1

15 µH

5

Shutdown

SHDNB

CS51412/4

R1

373

C3

100 µF

D3

1N5821

V

7

GND

C

FB

8

6

R2

127

C4

0.1 µF

Figure 17. Additional Application Diagram, 12 V to 5.0 V/1.0 A Buck Converter using the BIAS Pin

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13

CS51411, CS51412, CS51413, CS51414

ORDERING INFORMATION

Operating

Temperature Range

Device

Package

Shipping

CS51411ED8

95 Units/Rail

CS51411EDR8

CS51412ED8

CS51412EDR8

CS51413ED8

CS51413EDR8

CS51414ED8

CS51414EDR8

CS51411GD8

CS51411GDR8

CS51412GD8

CS51412GDR8

CS51413GD8

CS51413GDR8

CS51414GD8

CS51414GDR8

2500 Tape & Reel

95 Units/Rail

2500 Tape & Reel

95 Units/Rail

–40°C < T < 85°C

A

2500 Tape & Reel

95 Units/Rail

2500 Tape & Reel

95 Units/Rail

SO

–8

2500 Tape & Reel

95 Units/Rail

2500 Tape & Reel

95 Units/Rail

0°C < T < 70°C

A

2500 Tape & Reel

95 Units/Rail

2500 Tape & Reel

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14

CS51411, CS51412, CS51413, CS51414

PACKAGE DIMENSIONS

SO–8

D SUFFIX

CASE 751–07

ISSUE V

ꢀ ꢁ ꢂꢃ ꢄ ꢅ

ꢆꢇ ꢈ ꢉ ꢊꢃꢀ ꢄ ꢉ ꢁꢀ ꢉ ꢀ ꢋ ꢌ ꢀꢈ ꢂꢁ ꢍꢃ ꢎ ꢌꢀ ꢏ ꢉ ꢀ ꢋ ꢐꢃ ꢎ ꢌꢀ ꢄ ꢉ

ꢑ ꢆꢒꢇ ꢓꢊꢔ ꢆꢕꢖ ꢗꢇ

ꢗꢇ ꢏ ꢁ ꢀ ꢂꢎ ꢁ ꢍꢍ ꢉꢀ ꢋ ꢈ ꢉ ꢊꢃꢀ ꢄ ꢉꢁ ꢀ ꢅ ꢊꢉ ꢍꢍꢉ ꢊꢃ ꢂꢃ ꢎꢇ

ꢘꢇ ꢈ ꢉ ꢊꢃꢀ ꢄ ꢉ ꢁꢀ ꢌ ꢌ ꢀ ꢈ ꢙ ꢈ ꢁ ꢀ ꢁ ꢂ ꢉ ꢀ ꢏꢍ ꢚ ꢈ ꢃ ꢊ ꢁ ꢍꢈ

ꢐ ꢎꢁ ꢂ ꢎ ꢚ ꢄꢉ ꢁ ꢀ ꢇ

–X–

A

8

5

4

ꢒꢇ ꢊꢌ ꢛꢉ ꢊꢚ ꢊ ꢊꢁ ꢍꢈ ꢐ ꢎ ꢁꢂ ꢎ ꢚ ꢄꢉ ꢁ ꢀ ꢜꢇ ꢆꢓ ꢝ ꢜꢇ ꢜꢜ ꢞꢟ ꢐꢃ ꢎ

ꢄ ꢉꢈ ꢃ ꢇ

ꢓꢇ ꢈ ꢉ ꢊꢃꢀ ꢄ ꢉ ꢁꢀ ꢈ ꢈ ꢁ ꢃꢄ ꢀ ꢁ ꢂ ꢉ ꢀ ꢏꢍ ꢚ ꢈ ꢃ ꢈ ꢌꢊ ꢙꢌꢎ

ꢐ ꢎꢁ ꢂ ꢎ ꢚ ꢄꢉ ꢁ ꢀ ꢇ ꢌ ꢍꢍꢁ ꢠꢌ ꢙꢍꢃ ꢈ ꢌ ꢊꢙꢌ ꢎ

ꢐ ꢎꢁ ꢂ ꢎ ꢚ ꢄꢉ ꢁ ꢀ ꢄ ꢡꢌ ꢍꢍ ꢙ ꢃ ꢜꢇ ꢆꢗꢢ ꢝꢜ ꢇꢜꢜ ꢓꢟ ꢂꢁ ꢂꢌꢍ ꢉꢀ

ꢃ ꢛꢏ ꢃ ꢄꢄ ꢁ ꢣ ꢂ ꢡ ꢃ ꢈ ꢈ ꢉ ꢊꢃꢀ ꢄ ꢉꢁ ꢀ ꢌꢂ ꢊꢌꢛ ꢉꢊ ꢚ ꢊ

ꢊꢌꢂ ꢃꢎ ꢉ ꢌꢍ ꢏ ꢁ ꢀ ꢈ ꢉꢂ ꢉ ꢁꢀ ꢇ

S

ꢊ

B

ꢜꢇ ꢗꢓ ꢤꢝ ꢜ ꢇꢜ ꢆꢜꢟ

ꢑ

1

K

–Y–

G

MILLIMETERS

INCHES

C

N X 45

DIM MIN

MAX

ꢓꢇ ꢜꢜ

ꢒꢇ ꢜꢜ

ꢆꢇ ꢢꢓ

ꢜꢇ ꢓꢆ

MIN

MAX

ꢜꢇ ꢆ ꢕꢢ

ꢜꢇ ꢆ ꢓꢢ

ꢜꢇ ꢜ ꢞꢕ

ꢜꢇ ꢜ ꢗꢜ

_

A

B

C

D

G

H

J

ꢒꢇ ꢖꢜ

ꢘꢇ ꢖꢜ

ꢆꢇ ꢘꢓ

ꢜꢇ ꢘꢘ

ꢜꢇ ꢆꢖꢕ

ꢜꢇ ꢆꢓꢜ

ꢜꢇ ꢜꢓꢘ

ꢜꢇ ꢜꢆꢘ

SEATING

PLANE

–Z–

ꢜꢇ ꢆꢜ ꢤꢝ ꢜ ꢇꢜꢜ ꢒ ꢟ

ꢆꢇ ꢗꢢꢤ ꢙ ꢄꢏ

ꢜ

ꢇ

ꢜ

ꢓ

ꢜ

ꢤ

ꢙ

ꢄ

ꢏ

M

ꢜꢇ ꢆꢜ

ꢜꢇ ꢆꢕ

ꢜꢇ ꢒꢜ

ꢜꢤ ꢤ

ꢜꢇ ꢗꢓ

ꢆꢇ ꢗꢢ

ꢖꢤ ꢤ

ꢜꢇ ꢜꢜꢒ

ꢜꢇ ꢜꢜꢢ

ꢜꢇ ꢜꢆꢞ ꢜꢇꢜ ꢓꢜ

ꢜꢇ ꢜ ꢆꢜ

J

H

D

K

M

N

S

ꢜꢤ ꢤ

ꢜꢇ ꢜꢆꢜ

ꢜꢇ ꢗꢗꢖ

ꢖ ꢤꢤ

ꢜꢇ ꢜ ꢗꢜ

ꢜꢇ ꢗ ꢒꢒ

_

ꢊ

ꢄ

ꢛ

ꢜꢇ ꢗꢓ ꢤꢝ ꢜ ꢇꢜ ꢆꢜꢟ

ꢥ

ꢑ

ꢜꢇ ꢗꢓ

ꢓꢇ ꢖꢜ

ꢜꢇ ꢓꢜ

ꢞꢇ ꢗꢜ

PACKAGE THERMAL DATA

Parameter

SO–8

45

Unit

R

Typical

°C/W

Θ

JC

JA

165

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15

CS51411, CS51412, CS51413, CS51414

2

V is a trademark of Switch Power, Inc.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make

changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

JAPAN: ON Semiconductor, Japan Customer Focus Center

2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051

Phone: 81–3–5773–3850

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local

Sales Representative.

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

CS51411/D

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