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CS5332

Two−Phase Buck Controller

with Integrated Gate

Drivers for VRM 9.0

The CS5332 is a two−phase step down controller which

incorporates all control functions required to power high performance

processors and high current power supplies. Proprietary multi−phase

architecture guarantees balanced load current distribution and reduces

overall solution cost in high current applications. Enhanced V ™

control architecture provides the fastest possible transient response,

excellent overall regulation, and ease of use.

The CS5332 multi−phase architecture reduces output voltage and

input current ripple, allowing for a significant reduction in inductor

values and a corresponding increase in inductor current slew rate. This

approach allows a considerable reduction in input and output capacitor

requirements, as well as reducing overall solution size and cost.

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2

SO−28L

DW SUFFIX

CASE 751F

28

1

MARKING DIAGRAM

28

CS5332

Features

• Enhanced V Control Method

• VRM 9.0 Compatible 5−Bit DAC with 1.0% Accuracy

• Adjustable Output Voltage Positioning

• 4 On−Board GATE Drivers

AWLYYWW

2

1

A

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

• 200 kHz to 800 kHz Operation Set by Resistor

• Current Sensed through Buck Inductors, or Sense Resistors

• Hiccup Mode Current Limit

• Individual Current Limits for Each Phase

• On−Board Current Sense Amplifiers

• 3.3 V, 1.0 mA Reference Output

• 5.0 V and/or 12 V Operation

• On/Off Control (through Soft Start Pin)

• Power Good Output with Internal Delay

PIN CONNECTIONS

1

28

COMP

R

OSC

CCL

V

FB

V

DRP

CCL1

CS1

CS2

GATE(L)1

GND1

GATE(H)1

CS

REF

PWRGD

V

CCH1

V

LGND

SS

ID0

ID1

ID2

ID3

ID4

LIM

V

CCL2

GATE(L)2

GND2

GATE(H)2

I

REF

V

CCH2

ORDERING INFORMATION

Device

Package

Shipping

CS5332GDW28

27 Units/Rail

SO−28L

CS5332GDWR28

1000 Tape & Reel

©

Semiconductor Components Industries, LLC, 2006

1

Publication Order Number:

July, 2006 − Rev. 11

CS5332/D

CS5332

300 nH

+12 V

+5 V

3 × 16SP270M

+

1.0 μF

ENABLE

600 nH

56.2 k

1.0 nF

2.74 k

R

COMP

+

OSC

V

CCL

CCL1

GATE(L)1

FB

DRP

8 × 4SP560M

V

25.4 k

CS1

CS2

GND1

10 k

GATE(H)1

CS

V

OUT

REF

V

PWRGD

CCH1

LGND

V

ID0

ID1

ID2

ID3

ID4

LIM

PWRGD

12 × 10 μF

SS

V

CCL2

0.1 μF

V

ID0

V

ID1

V

ID2

GATE(L)2

V

GND2

GATE(H)2

I

V

REF

CCH2

V

ID3

4.87 k

1.0 k

1.0 μF

0.1 μF

V

ID4

600 nH

25.5 k

.01 μF

25.5 k

.01 μF

Figure 1. Application Diagram, Pentiumꢀ 4 Converter

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2

CS5332

ABSOLUTE MAXIMUM RATINGS*

Rating

Value

150

Unit

°C

Operating Junction Temperature

Lead Temperature Soldering:

Storage Temperature Range

Reflow: (SMD styles only) (Note 1)

230 peak

−65 to +150

2.0

°C

ESD Susceptibility (Human Body Model)

kV

1. 60 second maximum above 183°C.

*The maximum package power dissipation must be observed.

ABSOLUTE MAXIMUM RATINGS

Pin Name

Pin Symbol

V

I

SINK

MAX

MIN

SOURCE

Power for Logic

V

16 V

20 V

6.0 V

−0.3 V

N/A

50 mA

CCL

Power for GATE(L)1

Power for GATE(L)2

Power for GATE(H)1

Power for GATE(H)2

Power Good Output

Soft Start Capacitor

V

N/A

1.5 A, 1.0 μs 200 mA DC

20 mA

CCL1

CCL2

CCH1

CCH2

V

N/A

PWRGD

SS

1.0 mA

Voltage Feedback Compensation

Network

COMP

1.0 mA

Voltage Feedback Input

V

6.0 V

−0.3 V

1.0 mA

FB

Output for Adjusting Adaptive

Voltage Positioning

V

DRP

Frequency Resistor

Reference Output

R

6.0 V

20 V

−0.3 V

1.0 mA

50 mA

OSC

REF

High−Side FET Drivers

GATE(H)1−2

−0.3 V DC

1.5 A, 1.0 μs 200 mA DC 1.5 A, 1 μs 200 mA DC

−2.0 V for 100 nS

Low−Side FET Drivers

GATE(L)1−2

16 V

−0.3 V DC

1.5 A, 1.0 μs 200 mA DC 1.5 A, 1.0 μs 200 mA DC

−2.0 V for 100 nS

Return for Logic

Return for #1 Driver

LGND

GND1

N/A

50 mA

2.0 A, 1.0 μs 200 mA DC

1.0 mA

N/A

0.3 V

6.0 V

−0.3 V

Return for #2 Driver

GND2

N/A

Current Sense for Phases 1 − 2

Current Limit Set Point

Current Sense Reference

Voltage ID DAC Inputs

CS1−CS2

1.0 mA

I

1.0 mA

LIM

CS

1.0 mA

REF

VID0−4

1.0 mA

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3

CS5332

ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V

< 14 V; 8.0 V < V

< 20 V;

A

J

CCL

CCH

C

= 3.3 nF, C

= 3.3 nF, R

= 32.4 k, C

= 1.0 nF, C = 0.1 μF, C

= 0.1 μF, DAC Code 10000, C = 1.0 μF,

VCC

GATE(H)

GATE(L)

R(OSC)

COMP

SS

REF

I

≥ 1.0 V; unless otherwise specified.)

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

Voltage Identification DAC (0 = Connected to V ; 1 = Open or Pull−up to 3.3 V)

SS

Accuracy (all codes)

Measure V = COMP

± 1.0

%

FB

V

ID0

ID4

ID3

ID2

ID1

1

−

1.064

1.089

1.114

1.139

1.163

1.188

1.213

1.238

1.262

1.287

1.312

1.337

1.361

1.386

1.411

1.436

1.460

1.485

1.510

1.535

1.559

1.584

1.609

1.634

1.658

1.683

1.708

1.733

1.757

1.782

1.807

1.832

1.00

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.25

1.086

1.111

1.136

1.162

1.187

1.212

1.237

1.263

1.288

1.313

1.338

1.364

1.389

1.414

1.439

1.465

1.490

1.515

1.540

1.566

1.591

1.616

1.641

1.667

1.692

1.717

1.742

1.768

1.793

1.818

1.843

1.869

1.50

V

kΩ

V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Input Threshold

V

, V , V , V , V

ID3 ID2 ID1

ID4

ID0

Input Pull−up Resistance

Pull−up Voltage

, V , V , V , V

25

50

100

ID4

ID3

ID2

ID1

ID0

−

3.15

3.30

3.45

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4

CS5332

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V

< 14 V; 8.0 V < V

< 20 V;

A

J

CCL

CCH

C

= 3.3 nF, C

= 3.3 nF, R

= 32.4 k, C

= 1.0 nF, C = 0.1 μF, C

= 0.1 μF, DAC Code 10000, C = 1.0 μF,

VCC

GATE(H)

GATE(L)

R(OSC)

COMP

SS

REF

I

≥ 1.0 V; unless otherwise specified.)

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

Power−Good Output

Power Good Fault Delay

Output Low Voltage

CS

= V

to V

± 15%

25

−

50

0.25

0.1

125

0.40

10.0

−10

2.1

μs

V

REF

DAC

= 1.0 V, I

= 4.0 mA

PWRGD

Output Leakage Current

Lower Threshold

= 1.45 V, PWRGD = 5.5 V

−

μA

%

V

% of Nominal VID Code

−18

1.9

−14

2.0

Upper Threshold

−

Voltage Feedback Error Amplifier

V

Bias Current (Note 2)

28.5

15

31

30

33.5

60

μA

1.0 V < V < 1.9 V

FB

COMP Source Current

COMP = 0.5 V to 2.0 V;

V

= 1.8 V; DAC = 00000

FB

COMP Sink Current

15

30

60

μA

COMP = 0.5 V to 2.0 V;

V

= 1.9 V; DAC = 00000

FB

COMP Max Voltage

COMP Min Voltage

Transconductance

V

= 1.8 V COMP Open; DAC = 00000

= 1.9 V COMP Open; DAC = 00000

2.4

−

2.7

0.1

32

−

0.2

−

V

FB

−

mmho

−10 μA < I

< +10 μA

COMP

Output Impedance

Open Loop DC Gain

Unity Gain Bandwidth

−

60

−

2.5

90

−

MΩ

dB

Note 3

400

kHz

0.01 μF COMP Capacitor

−

70

−

dB

PSRR @ 1.0 kHz

Soft Start

Soft Start Charge Current

Soft Start DisCharge Current

Hiccup Mode Charge/Discharge Ratio

Peak Soft Start Charge Voltage

Soft Start DisCharge Threshold Voltage

PWM Comparators

0.2 V ≤ SS ≤ 3.0 V

15

4.0

30

7.5

50

13.0

−

μA

−

0.2 V ≤ SS ≤ 3.0 V

−

3.0

4.0

3.3

4.0

4.2

0.34

V

0.20

0.27

V

Minimum Pulse Width

Measured from CSx to GATE(H)x

−

350

0.4

515

0.5

ns

V

V(V ) = V(CS

) = 1.0 V, V(COMP) = 1.5 V

REF

FB

60 mV step applied between V

and

CSX

V

CREF

Channel Start Up Offset

0.3

V(CS1) = V(CS2) = V(V ) = V(CS

) = 0 V;

REF

FB

Measure V(COMP) when GATE(H)1,

GATE(H)2, switch high

2. The V Bias Current changes with the value of R

per Figure 4.

OSC

FB

3. Guaranteed by design. Not tested in production.

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5

CS5332

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V

< 14 V; 8.0 V < V

< 20 V;

A

J

CCL

CCH

C

= 3.3 nF, C

= 3.3 nF, R

= 32.4 k, C

= 1.0 nF, C = 0.1 μF, C

= 0.1 μF, DAC Code 10000, C = 1.0 μF,

VCC

GATE(H)

GATE(L)

R(OSC)

COMP

SS

REF

I

≥ 1.0 V; unless otherwise specified.)

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

GATE(H) and GATE(L)

High Voltage (AC)

Note 4 Measure V

− GATE(L) or

−

0

1.0

V

CCLX

X

V

− GATE(H)

CCHX

X

Low Voltage (AC)

Note 4 Measure GATE(L) or GATE(H)

−

0

0.5

80

V

X

Rise Time GATE(H)

1.0 V < GATE < 8.0 V; V

8.0 V > GATE > 1.0 V; V

= 10 V

35

65

1.2

ns

V

X

CCHX

CCLX

CCHX

CCLX

Rise Time GATE(L)

−

80

X

Fall Time GATE(H)

−

80

X

Fall Time GATE(L)

−

80

X

GATE(H) to GATE(L) Delay

GATE(L) to GATE(H) Delay

GATE Pull−down

GATE(H) < 2.0 V, GATE(L) > 2.0 V

30

−

110

1.6

X

GATE(L) < 2.0 V, GATE(H) > 2.0 V

X

Force 100 μA into GATE Driver with no power

applied to V and V = 2.0 V.

CCHX

CCLX

Oscillator

Switching Frequency

Measure any phase (R

= 32.4k)

300

150

600

−

400

200

800

1.00

180

500

250

1000

−

kHz

V

OSC

Note 4 Measure any phase (R

−

= 63.4 k)

OSC

= 16.2 k)

R

OSC

Voltage

Phase Delay

Rising Edge Only

165

195

deg

Adaptive Voltage Positioning

V

Output Voltage to DAC

Offset

CS1 = CS2 = CS , V = COMP

REF FB

−15

240

2.75

−

15

mV

V/V

DRP

OUT

Measure V

− COMP

DRP

Maximum V

Voltage

(CS1 = CS2) − C

= 50 mV,

310

3.15

380

3.65

DRP

REF

V

= COMP, Measure V

− COMP

FB

DRP

Current Sense Amp to V

Gain

−

DRP

Current Sensing and Sharing

CS Input Bias Current

V(CSx) = V(CS

) = 0 V

−

0.5

0.2

3.15

−

4.0

2.0

μA

V/V

mV

V

REF

CS1−CS2 Input Bias Current

Current Sense Amplifiers Gain

Current Sense Amp Mismatch

REF

2.80

−5.0

0

3.53

5.0

Note 4 0 ≤ (CSx − CS

) ≤ 50 mV

REF

Current Sense Amplifiers Input

Common Mode Range Limit

Note 4

−

V

− 2

CCL

Current Sense Input to I

Gain

0.25 V < I

< 1.20 V

LIM

5.00

4.0

−

6.25

10

8.00

26

V/V

mV/μs

μA

LIM

Current Limit Filter Slew Rate

Bias Current

Note 4

I

0 < I

< 1.0 V

0.1

105

1.0

135

LIM

Single Phase Pulse by Pulse

−

90

mV

Current Limit: V(CSx) − V(CS

)

REF

Current Share Amplifier Bandwidth

Note 4

1.0

−

mHz

4. Guaranteed by design. Not tested in production.

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6

CS5332

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V

< 14 V; 8.0 V < V

< 20 V;

A

J

CCL

CCH

C

= 3.3 nF, C

= 3.3 nF, R

= 32.4 k, C

= 1.0 nF, C = 0.1 μF, C

= 0.1 μF, DAC Code 10000, C = 1.0 μF,

VCC

GATE(H)

GATE(L)

R(OSC)

COMP

SS

REF

I

≥ 1.0 V; unless otherwise specified.)

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

Reference Output

Output Voltage

V

3.2

3.3

3.4

V

0 mA < I(V ) < 1.0 mA

REF

General Electrical Specifications

V

Operating Current

V

= COMP (no switching)

−

20.0

4.0

24.5

5.5

mA

V

CCL

FB

Operating Current

CCL1

CCL2

CCH1

CCH2

−

4.0

5.5

−

2.8

4.0

−

2.5

3.5

Start Threshold

Stop Threshold

Hysteresis

GATEs switching, Soft Start charging

4.05

3.75

100

1.8

1.55

100

4.40

4.20

200

2.0

4.70

4.60

300

2.2

CCL

GATEs stop switching, Soft Start discharging

GATEs not switching, Soft Start not charging

GATEs switching, Soft Start charging

V

CCL

mV

V

CCL

Start Threshold

Stop Threshold

Hysteresis

CCH1

GATEs stop switching, Soft Start discharging

GATEs not switching, Soft Start not charging

1.75

200

1.90

300

V

mV

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7

CS5332

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

28 Lead SO Wide

1

PIN SYMBOL

COMP

FUNCTION

Output of the error amplifier and input for the PWM

comparators.

2

V

Voltage Feedback Pin. To use Adaptive Voltage Positioning

(AVP) select an offset voltage at light load and connect a

FB

resistor between V and V

. The input current of the V

FB

OUT

FB

pin and the resistor value determine output voltage offset for

zero output current. Short V to V for no AVP.

FB

OUT

3

V

Current sense output for AVP. The offset of this pin above the

DAC voltage is proportional to the output current. Connect a

DRP

resistor from this pin to V to set amount AVP or leave this

FB

pin open for no AVP.

4−5

CS1−CS2

Current sense inputs. Connect current sense network for the

corresponding phase to each input.

6

CS

Reference for current sense amplifiers and input for Power

Good comparators. To balance input offset voltages between

the inverting and non−inverting inputs of the current sense

REF

amplifiers, connect a resistor between CS

and the output

REF

voltage. The value should be 2/5 of the value of the resistors

connected to the CSx pins.

7

PWRGD

Power−Good Output. Open collector output goes low when

the CS

is out of regulation.

REF

8−12

V

−V

Voltage ID DAC inputs. These pins are internally pulled up to

3.3 V if left open.

ID4

ID0

13

I

Sets threshold for current limit. Connect to reference through

a resistive divider.

LIM

Reference output. Decouple with 0.1 μF to LGND

Power for GATE(H)2.

14

15

16

17

18

19

20

REF

V

CCH2

GATE(H)2

GND2

High side driver #2.

Return for #2 drivers.

GATE(L)2

Low side driver #2.

V

Power for GATE(L)2.

CCL2

SS

Soft Start capacitor pin. The Soft Start capacitor controls both

Soft Start time and hiccup mode frequency. The COMP pin is

clamped below Soft Start during start up and hiccup mode.

21

22

LGND

Return for internal control circuits and IC substrate connection.

V

Power for GATE(H)1. UVLO Sense for High Side Driver sup-

ply connects to this pin.

CCH1

23

24

25

26

27

GATE(H)1

GND1

High side driver #1.

Return for #1 drivers.

Low side driver #1.

Power for GATE(L)1.

GATE(L)1

V

CCL1

V

Power for internal control circuits. UVLO Sense for Logic

connects to this pin.

CCL

28

R

OSC

A resistor from this pin to ground sets operating frequency

and V bias current.

FB

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8

CS5332

−

V

CCL

Start

Stop

+

PWRGD

+

−

3.3 V

REF

4.4 V

4.2 V

−

REF

V

Start

CCH1

Stop

+

PH 1

+

−

2.0 V

1.8 V

V

ID0

ID1

DAC

OUT

S

R

GATE(H)1

Gate

Nonoverlap

V

CCL1

DAC

−

V

ID2

ID3

PWMC1

+

GATE(L)1

GND1

Delay

CO1

+

V

ID4

MAXC1

−

+

−

LGN-

D

FAULT

CO1

0.33 V

V

CCH2

PH 2

−

V

S

R

AVPA

2.0 V

DRP

+

GATE(H)2

−

+

Gate

Nonoverlap

V

CCL2

−

PWMC2

+

GATE(L)2

GND2

CS

REF

CO2

−

+

MAXC2

CS1

CO1

CO2

−

CSA1

−

+

−

−14%

FAULT

0.33 V

CO2

+

−

×

2.0

CSA2

−

CS2

Offset

I

LIM

Filter

+

−

Current

Source

Gen

I

LIM

BIAS

−

EA

SS

+

FAULT

Charge

Current

S

R

DAC

OUT

FAULT

PH 1

PH 2

+

−

+ SS

Discharge

Current

SS

Discharge

Current

OSC

−

+

−

V

COMP

R

OSC

SS

FB

Figure 2. Block Diagram

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9

CS5332

TYPICAL PERFORMANCE CHARACTERISTICS

900

800

700

80

60

40

20

0

600

500

400

300

200

100

10

20

30

40

50

60

70

10

20

30

40

50

60

70

80

R

OSC

Value, kΩ

R

OSC

Value, kΩ

Figure 3. Oscillator Frequency

Figure 4. V_FBBias Current vs. R_OSCValue

120

100

80

100

80

60

40

20

0

20

0

16

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

Load Capacitance, nF

Figure 5. GATE(H) Rise−time vs. Load Capacitance

Figure 6. GATE(H) Fall−time vs. Load Capacitance

measured from 1.0 V to 4.0 V with V_CCat 5.0 V.

measured from 4.0 V to 1.0 V with V_CCat 5.0 V.

120

100

80

120

100

80

60

40

20

0

20

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

Load Capacitance, nF

Figure 7. GATE(L) Rise−time vs. Load Capacitance

Figure 8. GATE(L) Fall−time vs. Load Capacitance

measured from 4.0 V to 1.0 V with V_CCat 5.0 V.

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10

CS5332

APPLICATIONS INFORMATION

FIXED FREQUENCY MULTI−PHASE CONTROL

comparator rises and terminates the PWM cycle. If the

inductor starts the cycle with a higher current, the PWM

cycle will terminate earlier providing negative feedback.

In a multi−phase converter, multiple converters are

connected in parallel and are switched on at different times.

This reduces output current from the individual converters

and increases the apparent ripple frequency. Because several

converters are connected in parallel, output current can ramp

up or down faster than a single converter (with the same

value output inductor) and heat is spread among multiple

components.

The CS5332 provides a C input for each phase, but the

X

CS , V and COMP inputs are common to all phases.

REF FB

Current sharing is accomplished by referencing all phases to

the same V and COMP pins, so that a phase with a larger

FB

current signal will turn off earlier than phases with a smaller

current signal.

Including both current and voltage information in the

feedback signal allows the open loop output impedance of

the power stage to be controlled. If the COMP pin is held

steady and the inductor current changes, there must also be

a change in the output voltage. Or, in a closed loop

configuration when the output current changes, the COMP

pin must move to keep the same output voltage. The required

change in the output voltage or COMP pin depends on the

scaling of the current feedback signal and is calculated as

The CS5332 uses a two−phase, fixed frequency,

2

Enhanced V architecture. Each phase is delayed 180° from

the previous phase. Normally GATE(H) transitions high at

the beginning of each oscillator cycle. Inductor current

ramps up until the combination of the current sense signal

and the output ripple trip the PWM comparator and bring

GATE(H) low. Once GATE(H) goes low, it will remain low

until the beginning of the next oscillator cycle. While

2

GATE(H) is high, the Enhanced V loop will respond to line

DV + R CSA Gain DI

S

and load transients. Once GATE(H) is low, the loop will not

respond again until the beginning of the next cycle.

The single−phase power stage output impedance is;

2

Therefore, constant frequency Enhanced V will typically

Single Stage Impedance + DVńDI + R CSA Gain.

S

respond within the off−time of the converter.

The multi−phase power stage output impedance is the

single−phase output impedance divided by the number of

phases. The output impedance of the power stage determines

how the converter will respond during the first few μs of a

transient before the feedback loop has repositioned the

COMP pin.

2

The Enhanced V architecture measures and adjusts

current in each phase. An additional input (C ) for inductor

X

2

current information has been added to the V loop for each

phase as shown in Figure 9.

The peak output current of each phase can also be

calculated from;

SWNODE

CS

L

X

R

L

+

CSA

+

V

* V

FB

* V

OFFSET

COMP

R

I

(per phase) +

S

pkout

OFFSET

CSA Gain

S

CS

V

REF

PWM-

COMP

Figure 10 shows the step response of a single phase with

the COMP pin at a fixed level. Before T1 the converter is in

normal steady state operation. The inductor current provides

the PWM ramp through the Current Sense Amplifier. The

PWM cycle ends when the sum of the current signal, voltage

signal and OFFSET exceed the level of the COMP pin. At

T1 the output current increases and the output voltage sags.

The next PWM cycle begins and the cycle continues longer

than previously while the current signal increases enough to

V

+

OUT

FB

+

E.A.

+

DAC

OUT

+

COMP

Figure 9. Enhanced V²Current Sense Scheme

make up for the lower voltage at the V pin and the cycle

FB

ends at T2. After T2 the output voltage remains lower than

at light load and the current signal level is raised so that the

sum of the current and voltage signal is the same as with the

original load. In a closed loop system the COMP pin would

move higher to restore the output voltage to the original level.

The inductor current is measured across R , amplified by

S

CSA and summed with the OFFSET and Output Voltage at

the non−inverting input of the PWM comparator. The

inductor current provides the PWM ramp and as inductor

current increases the voltage on the positive pin of the PWM

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11

CS5332

considered when setting the I

threshold. If a more

LIM

accurate current sense is required than inductive sensing can

provide, current can be sensed through a resistor as shown

in Figure 9.

SWNODE

Current Sharing Accuracy

PCB traces that carry inductor current can be used as part

of the current sense resistance depending on where the

current sense signal is picked off. For accurate current

sharing, the current sense inputs should sense the current at

the same point for each phase and the connection to the

V

(V

)

FB

OUT

CSA Out

CS

should be made so that no phase is favored. (In some

REF

COMP − Offset

CSA Out + V

cases, especially with inductive sensing, resistance of the

pcb can be useful for increasing the current sense

resistance.) The total current sense resistance used for

calculations must include any pcb trace between the CS

FB

T1

T2

Figure 10. Open Loop Operation

inputs and the CS

input that carries inductor current.

REF

Current Sense Amplifier Input Mismatch and the value of

the current sense element will determine the accuracy of

current sharing between phases. The worst case Current

Sense Amplifier Input Mismatch is 5.0 mV and will typically

be within 3.0 mV. The difference in peak currents between

phases will be the CSA Input Mismatch divided by the current

sense resistance. If all current sense elements are of equal

resistance, a 3.0 mV mismatch with a 2.0 mΩ sense resistance

will produce a 1.5 A difference in current between phases.

Inductive Current Sensing

For lossless sensing current can be sensed across the

inductor as shown in Figure 11. In the diagram, L is the

output inductance and R is the inherent inductor resistance.

L

To compensate the current sense signal the values of R1 and

C1 are chosen so that L/R = R1 × C1. If this criteria is met

L

the current sense signal will be the same shape as the

inductor current, the voltage signal at Cx will represent the

instantaneous value of inductor current and the circuit can be

analyzed as if a sense resistor of value R was used as a sense

L

Operation at > 50% Duty Cycle

For operation at duty cycles above 50% Enhanced V

2

resistor (R ).

S

will exhibit subharmonic oscillation unless a compensation

ramp is added to each phase. A circuit like the one on the left

side of Figure 12 can be added to each current sense network

to implement slope compensation. The value of R1 can be

varied to adjust the ramp size.

R1

SWNODE

CS

X

+

L

+

CSA

C1

R

L

OFFSET

CS

REF

PWM-

COMP

Switch Node

GATE(L)X

+

V

OUT

V

FB

E.A.

+

DAC

OUT

25 k

R1

3.0 k

COMP

CS

X

Figure 11. Lossless Inductive Current Sensing with

Enhanced V²

1.0 nF

.01 μF

0.1 μF

When choosing or designing inductors for use with

inductive sensing, tolerances and temperature effects should

be considered. Cores with a low permeability material or a

large gap will usually have minimal inductance change with

temperature and load. Copper magnet wire has a

temperature coefficient of 0.39% per °C. The increase in

winding resistance at higher temperatures should be

CS

REF

MMBT2222LT1

Existing Current

Sense Circuit

Slope Comp

Circuit

Figure 12. External Slope Compensation Circuit

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12

CS5332

Ramp Size and Current Sensing

Because the current ramp is used for both the PWM ramp

and to sense current, the inductor and sense resistor values

will be constrained. A small ramp will provide a quick

transient response by minimizing the difference over which

the COMP pin must travel between light and heavy loads,

but a steady state ramp of 25 mV

or greater is typically

P−P

required to prevent pulse skipping and minimize pulse width

jitter. For resistive current sensing, the combination of the

inductor and sense resistor values must be chosen to provide

a large enough steady state ramp. For large inductor values

the sense resistor value must also be increased.

For inductive current sensing the RC network must meet

the requirement of L/R = R × C to accurately sense the AC

L

and DC components of the current the signal. Again the

values for L and R will be constrained in order to provide

L

a large enough steady state ramp with a compensated current

sense signal. A smaller L, or a larger R than optimum might

L

Figure 13. Inductive Sensing waveform during a

Load Step with Fast RC Time Constant (50 μs/div)

be required. But unlike resistive sensing, with inductive

sensing small adjustments can be made easily with the

values of R and C to increase the ramp size if needed.

Current Limit

If RC is chosen to be smaller (faster) than L/R , the AC

L

Two levels of overcurrent protection are provided. Any

portion of the current sensing signal will be scaled larger

than the DC portion. This will provide a larger steady state

ramp, but circuit performance will be affected and must be

evaluated carefully. The current signal will overshoot during

transients and settle at the rate determined by R × C. It will

eventually settle to the correct DC level, but the error will

decay with the time constant of R × C. If this error is

excessive it will effect transient response, adaptive

positioning and current limit. During transients, the COMP

pin will be required to overshoot along with the current

time the voltage on a Current Sense pin exceeds CS

by

REF

more than the Single Phase Pulse by Pulse Current Limit, the

PWM comparator for that phase is turned off. This provides

fast peak current protection for individual phases. The

outputs of all the currents are also summed and filtered to

compare an averaged current signal to the voltage on the

I

pin. If this voltage is exceeded, the fault latch trips and

LIM

the Soft Start capacitor is discharged by a 7.5 μA source until

the COMP pin reaches 0.2 V. Then Soft−Start begins. The

converter will continue to operate in this mode until the fault

condition is corrected.

signal in order to maintain the output voltage. The V

DRP

will also overshoot during transients and possibly slow the

response. Single phase overcurrent will trip earlier than it

would if compensated correctly and hiccup mode current

limit will have a lower threshold for fast rise step loads than

for slowly rising output currents.

The waveforms in Figure 13 show a simulation of the

current sense signal and the actual inductor current during

a positive step in load current with values of L = 500 nH,

Overvoltage Protection

Overvoltage protection (OVP) is provided as a result of

2

the normal operation of the Enhanced V control topology

with synchronous rectifiers. The control loop responds to an

overvoltage condition within 400 ns, causing the top

MOSFET’s to shut off, and the synchronous MOSFET’s to

turn on. This results in a “crowbar” action to clamp the

output voltage and prevent damage to the load. The regulator

will remain in this state until the overvoltage condition

ceases or the input voltage is pulled low.

R = 1.6 mΩ, R1 = 20 k and C1 = .01 μF. For ideal current

L

signal compensation the value of R1 should be 31 kΩ. Due

to the faster than ideal RC time constant there is an

overshoot of 50% and the overshoot decays with a 200 μs

time constant. With this compensation the I

LIM

Transient Response and Adaptive Positioning

For applications with fast transient currents the output

filter is frequently sized larger than ripple currents require in

threshold must be set more than 50% above the full load

current to avoid triggering hiccup mode during a large

output load step.

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13

CS5332

order to reduce voltage excursions during transients.

to the final voltage after a transient. This will be most

apparent with lower capacitance output filters.

Note: Large levels of adaptive positioning can cause pulse

width jitter.

Adaptive voltage positioning can reduce peak−peak output

voltage deviations during load transients and allow for a

smaller output filter. The output voltage can be set higher

than nominal at light loads to reduce output voltage sag

when the load current is stepped up and set lower than

nominal during heavy loads to reduce overshoot when the

load current is stepped up. For low current applications a

droop resistor can provide fast accurate adaptive

positioning. However at high currents, the loss in a droop

resistor becomes excessive. For example, in a 50 A

converter a 1.0 mΩ resistor to provide a 50 mV change in

output voltage between no load and full load would dissipate

2.5 Watts.

Lossless adaptive positioning is an alternative to using a

droop resistor, but must respond quickly to changes in load

current. Figure 14 shows how adaptive positioning works.

The waveform labeled normal shows a converter without

adaptive positioning. On the left, the output voltage sags

when the output current is stepped down and later

overshoots when current is stepped back down. With fast

(ideal) adaptive positioning the peak to peak excursions are

cut in half. In the slow adaptive positioning waveform the

output voltage is not repositioned quickly enough after

current is stepped up and the upper limit is exceeded.

Error Amp Compensation

The transconductance error amplifier requires a capacitor

between the COMP pin and GND. Use of values less than 1.0

nF may result in error amp oscillation of several MHz.

The capacitor between the COMP pin and the inverting

error amplifier input and the parallel resistance of the V

FB

resistor and the V

resistor are used to roll off the error

DRP

amp gain. The gain is rolled off at a high enough frequency

to give a quick transient response, but low enough to cross

zero dB well below the switching frequency to minimize

ripple and noise on the COMP pin.

UVLO

The CS5332 has undervoltage lockout functions

connected to two pins. One, intended for the logic and

low−side drivers, with a 4.4 V turn−on threshold is

connected to the V

pin. A second, for the high side

CCL

drivers, has a 2.0 V threshold and is connected to the V

pin.

CCH1

The UVLO threshold for the high side drivers was chosen

at a low value to allow for flexibility in the part and an input

voltage as low as 3.3 V. In many applications this will be

disabled or will only check that the applicable supply is on

− not that it is at a high enough voltage to run the converter.

For the 12 V converter in Figure 1. the UVLO pin for the

IN

high side driver is pulled up by the 5.0 V supply (through two

diode drops) and the function is not used. The diode between

the Soft Start pin and the 12 V supply holds the Soft Start pin

near GND and prevents start−up while the 12 V supply is off.

In an application where a higher UVLO threshold is

necessary a circuit like the one in Figure 15 will lock out the

converter until the 12 V supply exceeds 9.0 V.

Normal

FastAdaptive Positioning

SlowAdaptive Positioning

Limits

Figure 14. Adaptive Positioning

The CS5332 can be configured to adjust the output

voltage based on the output current of the converter. (Refer

to Figure 1.)

+12 V

+5.0 V

To set the no−load positioning, a resistor is placed

50 k

between the output voltage and V pin. The V bias

FB

Soft Start

current will develop a voltage across the resistor to decrease

the output voltage. The V bias current is dependent on the

FB

value of R

. See Figure 4 on the datasheet.

OSC

During no load conditions the V

pin is at the same

FB

DRP

100 k

voltage as the V pin, so none of the V bias current flows

FB

100 k

through the V

resistor. When output current increases

DRP

the V

pin increases proportionally and the V

DRP

current offsets the V bias current and causes the output

FB

voltage to decrease.

Figure 15. External UVLO Circuit

The V and V

pins take care of the slower and DC

FB

DRP

Remote Sense

voltage positioning. The first few μs are controlled primarily

by the ESR and ESL of the output filter. The transition

between fast and slow positioning is controlled by the ramp

size and the error amp compensation. If the ramp size is too

large or the error amp too slow there will be a long transition

In some applications that require remote output voltage

sensing, there are conditions when the path of the feedback

signal can be broken. In a voltage regulator module (VRM)

the remote voltage feedback sense point is typically off the

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14

CS5332

module. If the module is powered apart from the intended

considered when laying out the power, filter and feedback

signal sections of the board. Typically, a multi−layer board

with at least one ground plane is recommended. If the layout

is such that high currents can exist in the ground plane

underneath the controller or control circuitry, the ground

plane can be slotted to reroute the currents away from the

controller. The slots should typically not be placed between

the controller and the output voltage or in the return path of

the gate drive. Additional power and ground planes or

islands can be added as required for a particular layout.

Gate drives experience high di/dt during switching and the

inductance of gate drive traces should be minimized. Gate

drive traces should be kept as short and wide as practical and

should have a return path directly below the gate trace.

Output filter components should be placed on wide planes

connected directly to the load to minimize resistive drops

during heavy loads and inductive drops and ringing during

transients. If required, the planes for the output voltage and

return can be interleaved to minimize inductance between

the filter and load.

application, the feedback will be left open. On a

motherboard, the feedback path might be broken when the

processor socket is left open. Without the feedback

connection the output voltage is likely to exceed the

intended voltage. To protect the circuit from overvoltage

conditions, a resistor can be connected between the local

output voltage and the remote sense line as shown in Figure 16.

Local V

Remote V

OUT

Remote

Sense

Line

100 Ω

Voltage feedback should be taken from a point of the

output or the output filter that doesn’t favor any one phase.

If the feedback connection is closer to one inductor than the

others the ripple associated with that phase may appear

larger than the ripple associated with the other phases and

poor current sharing can result.

The current sense signal is typically tens of milli−volts.

Noise pick−up should be avoided wherever possible.

Current feedback traces should be routed away from noisy

areas such as switch nodes and gate drive signals. The paths

should be matched as well as possible. It is especially

important that all current sense signals be picked off at

similar points for accurate current sharing. If the current

signal is taken from a place other than directly at the inductor

any additional resistance between the pick−off point and the

inductor appears as part of the inherent inductor resistance

and should be considered in design calculations. Capacitors

for the current feedback networks should be placed as close

to the current sense pins as practical.

CS

Network

V

Network

REF

FB

Figure 16. Remote Sense Connection

Soft Start Enable, and Hiccup Mode

A capacitor between the Soft Start pin and GND controls

Soft Start and hiccup mode slopes. A 0.1 μF capacitor with

30 μA charge current will allow the output to ramp up at 0.3

V/ms or 1.5 V in 5.0 ms at start−up.

When a fault is detected due to overcurrent or UVLO the

converter will enter a low duty cycle hiccup mode. During

hiccup mode the converter will not switch from the time a

fault is detected until the Soft Start capacitor has discharged

below the Soft Start Discharge Threshold and then charged

back up above the Channel Start Up Offset.

The Soft Start pin will disable the converter when pulled

below 0.3 V.

Layout Guidelines

With the fast rise, high output currents of microprocessor

applications, parasitic inductance and resistance should be

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CS5332

DESIGN PROCEDURE

Multiply the converterZ by the output current step size

to calculate where the output voltage should recover to

within the first switching cycle after a transient. If the

ConverterZ is higher than the value required to recover

to where the adaptive positioning is set, the remainder

of the recovery will be controlled by the error amp

compensation and will typically recover in 10 − 20 μs.

Current Sensing, Power Stage and

Output Filter Components

1. Choose the output filter components to meet peak

transient requirements. The formula below can be

used to provide an approximate starting point for

capacitor choice, but will be inadequate to calculate

actual values.

DVR + DI

ConverterZ

OUT

Make sure that ΔVR is less than the expected peak

transient for a good transient response.

DV

+ (DIńDT) ESL ) DI ESR

PEAK

Ideally the output filter should be simulated with

models including ESR, ESL, circuit board parasitics

and delays due to switching frequency and converter

response. Typically both bulk capacitance

(electrolytic, Oscon, etc,) and low impedance

capacitance (ceramic chip) will be required. The bulk

capacitance provides “hold up” during the converter

response. The low impedance capacitance reduces

steady state ripple and bypasses the bulk capacitance

during slewing of output current.

5. Adjust L and R or R as required to meet the best

L

S

combination of transient response, steady state output

voltage ripple and pulse width jitter.

Current Limit

When the sum of the Current Sense amplifiers (V

)

ITOTAL

exceeds the voltage on the I

pin the part will enter hiccup

LIM

mode. For inductive sensing the I

pin voltage should be

LIM

set based on the inductor resistance (or current sense

resistor) at max temperature and max current. To set the level

of the I

pin:

LIM

2. For inductive current sensing (only) choose the

current sense network RC to provide a 25 mV

minimum ramp during steady state operation.

6. V

+ R I

CS to I

Gain

LIM

I(LIM)

OUT(LIM)

where:

R is R or R

V

ńV

L

S;

OUT IN

R + (V * V

)

IN OUT

I

is the current limit threshold.

F C 25 mV

OUT(LIM)

For the overcurrent to work properly the inductor time

constant (L/R) should be≤ the Current sense RC. If the

RC is too fast, during step loads the current waveform

will appear larger than it is (typically for a few hundred

μs) and may trip the current limit at a level lower than

the DC limit.

Then choose the inductor value and inherent resistance

to satisfy L/R = R × C.

L

For ideal current sense compensation the ratio of L and

R

L

is fixed, so the values of L and R will be a

L

compromise typically with the maximum value R

L

limited by conduction losses or inductor temperature

rise and the minimum value of L limited by ripple

current.

Adaptive Positioning

7. To set the amount of voltage positioning below the

DAC setting at no load, connect a resistor (R ( ))

3. For resistive current sensing choose L and R to

S

V FB

provide a steady state ramp greater than 25 mV.

between the output voltage and the V pin. Choose

FB

LńR + (V * V

IN OUT

) T

ń25 mV

ON

R ( ) as;

V FB

S

R

V(FB)

+ NL PositionńV Bias Current

FB

Again the ratio of L and R is fixed and the values of

L

L and R will be a compromise.

S

See Figure 4 for V Bias Current.

FB

4. Calculate the high frequency output impedance

(ConverterZ) of the converter during transients. This

is the impedance of the Output filter ESR in parallel

with the power stage output impedance (PwrstgZ)

and will indicate how far from the original level

(ΔVR) the output voltage will typically recover to

within one switching cycle. For a good transient

response ΔVR should be less than the peak output

voltage overshoot or undershoot.

8. To set the difference in output voltage between no

load and full load, connect a resistor (R

)

V(DRP)

between the V

and V pins. R

can be

DRP

FB

V(DRP)

calculated in two steps. First calculate the difference

between the V and V pin at full load. (The V

FB

DRP

FB

voltage should be the same as the DAC voltage during

closed loop operation.) Then choose the R to

V(DRP)

source enough current across R ( ) for the desired

V FB

change in output voltage.

DVR + ConverterZ ESR

DV

+ I

R CS to V

Gain

DRP

V(DRP)

OUTFL

PwrstgZ ESR

ConverterZ +

where:

PwrstgZ ) ESR

R = R or R for one phase;

L

S

where:

I

is the full load output current.

OUTFL

PwrstgZ + R CSA Gainń2.0

S

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CS5332

The peak output voltage transient is 70 mV max during a 41

A step current.

R

+ DV

DRP

R

ńDV

V(FB) OUT

V(DRP)

Calculate Input Filter Capacitor Current Ripple

The procedure below assumes that phases do not overlap

and output inductor ripple current (P−P) is less than the

average output current of one phase.

Current Sensing, Power Stage and

Output Filter Components

1.Assume 1.5 mΩ of output filter ESR.

+ (V * V

) (V ńV ń(F C 25 mV)

OUT IN)

2.R

IN

OUT

9. Calculate Input Current

+ (12 * 1.55) (1.55ń12)ń(240 k .01mF 25mV)

+ 22.5 k

V

I

OUT

Efficiency V

I

+

IN

(

)

IN

LńR + .01 mF 22.5 kW + 225 ms

L

10. Calculate Duty Cycle (per phase).

Choose R + 2.0 mW

L

V

L + 2.0 mW 225 ms + 450 nH

OUT

Duty Cycle +

(

)

Efficiency V

3. n/a

4. PwrstgZ+ R CSA Gainń2.0

IN

11. Calculate Apparent Duty Cycle.

L

+ 2.0 mW 3.15ń2 + 3.1 mW

Apparent Duty Cycle + Duty Cycle # of Phases

PwrstgZ ESR

12. Calculate Input Filter Capacitor Ripple Current. Use

the chart in Figure 17 to calculate the normalized

+

ConverterZ

PwrstgZ ) ESR

3.1 mW 1.5 mW

3.1 mW ) 1.5 mW

ripple current (K ) based on the reciprocal of

RMS

^ 1.0 mW

Apparent Duty Cycle. Then multiply the input current

by K to obtain the Input Filter Capacitor Ripple

DVR + 1.0 mW 41 A + 41 mV

RMS

Current.

5. n/a

Ripple (RMS) + I K

IN

RMS

Current Limit

4.00

3.50

3.00

2.50

2.00

1.50

6.

V

+ R I

+ 2.0 mW 50 A 6.25 + 625 mV

CS to I

Gain

LIM

I(LIM)

L

OUT(LIM)

Adaptive Positioning

7. R

+ NL PositionńV

FB

+ 50 mVń18 mA + 2.78 kW

Bias Current

V(FB)

8.

+ R I Current Sense to V

Gain

DRP

DV

1.00

0.50

0.00

L

OUT

DRP

+ 2.0 mW 41 A 3.1 + 254 mV

+ DV

DRP

R

ńDV

V(FB) OUT

R

V(DRP)

15

10

5

0

+ 254 mV 2.78 kWń50 mV + 25.4 kW

1/ Apparent Duty Cycle

Figure 17. Normalized Input Filter Capacitor

Ripple Current

1.52 V 41 A

9.

I

+

+ 6.1 A

IN

(

)

0.85 12V

IN

DESIGN EXAMPLE

1.52 V

Duty Cycle +

+ 0.15

10.

(

)

0.85 12 V

IN

Choose the component values for a 240 kHz, 12 V to 1.525

V, 41 A converter with lossless current sensing, adaptive

positioning and a 50 A current limit. The adaptive

positioning is chosen 50 mV below the DAC setting at no

load and 50 mV below the no−load position with 41 A out.

11.Apparent Duty Cycle + 0.15 2.0 + 0.3

12.RMS ripple is 6.1 A 1.5 + 9.2 A

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CS5332

300 nH

V

IN

+

1.0 μF

ENABLE

1.2 μH

10 k

1 nF

56.2 k

1 nF

R

COMP

OSC

CCL

3 × 4SP560M

V

FB

DRP

2.74 k

12.7 k

V

CCL1

V

25.4 k

GATE(L)1

GND1

CS1

CS2

V

OUT

GATE(H)1

CS

REF

V

PWRGD

CCH1

LGND

V

ID0

ID1

ID2

ID3

ID4

PWRGD

3 × 10 μF

SS

V

CCL2

0.1 μF

GATE(L)2

V

GND2

V

GATE(H)2

V

I

LIM

REF

CCH2

1.0 μF

2.8 k

1.0 k

0.1 μF

1.2 μH

25.5 k

0.1 μF

25.5 k

0.1 μF

GL1

GL2

Figure 18. Additional Application Diagram, 5.0 V only to 2.5 V

300 nH

+5 V

+

+12 V

3 × 16SP270M

1.0 μF

ENABLE

470 nH

56.2 k

1.0 nF

2.74 k

1.0 nF

R

V

COMP

OSC

CCL

+

V

FB

8 × 4SP560M

V

CCL1

V

DRP

GATE(L)1

GND1

25.4 k

12.7 k

CS1

CS2

GATE(H)1

CS

REF

V

OUT

V

CCH1

PWRGD

LGND

V

PWRGD

ID0

ID1

12 × 1.0 μF

SS

V

CCL2

V

0.1 μF

ID2

ID3

ID4

V

ID0

GATE(L)2

GND2

V

GATE(H)2

I

LIM

ID1

V

CCH2

REF

V

ID2

V

ID3

1.0 μF

4.87 k

1.0 k

0.1 μF

ID4

470 nH

25.5 k

.01 μF

25.5 k

.01 μF

Figure 19. Additional Application Diagram, 5.0 V to 1.6 V with 12 V Bias

http://onsemi.com

18

CS5332

300 nH

+5 V

+

1.0 μF

3 × 6SP680M

ENABLE

470 nH

56.2 k

1.0 nF

2.74 k

R

+

COMP

OSC

CCL

V

DRP

8 × 4SP560M

FB

V

CCL1

V

25.4 k

12.7 k

GATE(L)1

GND1

CS1

CS2

CS

GATE(H)1

REF

V

OUT

V

CCH1

PWRGD

V

LGND

SS

ID0

PWRGD

12 × 10 μF

V

ID1

V

CCL2

ID2

0.1 μF

V

ID0

ID1

ID2

ID3

V

GATE(L)2

GND2

ID3

ID4

V

I

GATE(H)2

LIM

V

CCH2

REF

V

4.87 k

1.0 k

1.0 μF

0.1 μF

V

ID4

470 nH

25.5 k

.01 μF

25.5 k

.01 μF

Figure 20. Additional Application Diagram, 5.0 V only to 1.6 V

http://onsemi.com

19

CS5332

PACKAGE DIMENSIONS

SO−28

DW SUFFIX

CASE 751F−05

ISSUE F

D

NOTES:

A

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSIONS.

4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS

OF B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

28

15

1

14

MILLIMETERS

B

PIN 1 IDENT

DIM MIN

MAX

2.65

0.29

0.49

0.32

18.05

7.60

A

A1

B

C

D

E

2.35

0.13

0.35

0.23

17.80

7.40

L

0.10

e

1.27 BSC

H

L

10.05

0.41

10.55

0.90

e

C

q

0

8

ꢀ

SEATING

PLANE

B

C

q

M

S

B

0.025

C A

PACKAGE THERMAL DATA

Parameter

SO−28L

Unit

R

Typical

15

75

°C/W

Θ

JC

JA

Θ

2

V

is a trademark of Switch Power, Inc.

Pentium is a registered trademark of Intel Corporation.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

CS5332/D

http://onsemi.com

20

型号:	CS5332GDW28
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	ROCHESTER ELECTRONICS INC
零件包装代码：	SOIC
包装说明：	SOP,
针数：	28
Reach Compliance Code：	unknown
风险等级：	5.91
Is Samacsys：	N
其他特性：	ALSO REQUIRES 8V TO 20V SUPPLY
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT/VOLTAGE-MODE
控制技术：	PHASE-SHIFT CONTROL
最大输入电压：	14 V
最小输入电压：	4.7 V
标称输入电压：	10 V
JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e0
长度：	17.925 mm
湿度敏感等级：	NOT SPECIFIED
功能数量：	1
端子数量：	28
最高工作温度：	70 °C
最低工作温度：
最大输出电流：	1.5 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	2.65 mm
表面贴装：	YES
切换器配置：	PHASE-SHIFT
最大切换频率：	1000 kHz
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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