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  • CS5532-ASZ图
  • 深圳市科庆电子有限公司

     该会员已使用本站16年以上
  • CS5532-ASZ 现货库存
  • 数量34021 
  • 厂家CIRRUS 
  • 封装SSOP20 
  • 批号23+ 
  • 现货只售原厂原装可含13%税
  • QQ:2850188252QQ:2850188252 复制
    QQ:2850188256QQ:2850188256 复制
  • 0755 QQ:2850188252QQ:2850188256
  • CS5532-ASZ【特价现货】图
  • 齐创科技(上海北京青岛)有限公司

     该会员已使用本站14年以上
  • CS5532-ASZ【特价现货】 现货库存
  • 数量7600 
  • 厂家CIRRUS代理 
  • 封装SOP-20 
  • 批号24+热销 
  • 热卖全新原装现货特价长期供应
  • QQ:2394092314QQ:2394092314 复制
    QQ:792179102QQ:792179102 复制
  • 021-62153656 QQ:2394092314QQ:792179102
  • CS5532-ASZ图
  • 集好芯城

     该会员已使用本站13年以上
  • CS5532-ASZ 现货库存
  • 数量17122 
  • 厂家Cirrus Logic 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • CS5532-ASZ图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • CS5532-ASZ 现货库存
  • 数量5580 
  • 厂家 
  • 封装 
  • 批号16+ 
  • 价格及优,真实库存,全新原装正品!!
  • QQ:2880824479QQ:2880824479 复制
  • 010-62104891 QQ:2880824479
  • CS5532-ASZ图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • CS5532-ASZ 现货库存
  • 数量4500 
  • 厂家CIRRUS 
  • 封装TSSOP20 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:2216987084QQ:2216987084 复制
  • 0755-83222787 QQ:1950791264QQ:2216987084
  • CS5532-ASZ图
  • 深圳市力拓辉电子有限公司

     该会员已使用本站13年以上
  • CS5532-ASZ 现货库存
  • 数量8000 
  • 厂家CIRRUS 
  • 封装TSSOP-20 
  • 批号1445+ 
  • 全新原装特价热卖中
  • QQ:2881140004QQ:2881140004 复制
    QQ:2881140005QQ:2881140005 复制
  • 755-82787180 QQ:2881140004QQ:2881140005
  • CS5532-ASZ图
  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
  • CS5532-ASZ 现货库存
  • 数量20000 
  • 厂家CIRR 
  • 封装SOP 
  • 批号23+ 
  • 原装现货热卖!请联系吴先生 13681678667
  • QQ:617677003QQ:617677003 复制
  • 15618836863 QQ:617677003
  • CS5532-ASZ图
  • 深圳市惠诺德电子有限公司

     该会员已使用本站7年以上
  • CS5532-ASZ 现货库存
  • 数量29500 
  • 厂家CIRRUS 
  • 封装SSOP20 
  • 批号21+ 
  • 只做原装现货代理
  • QQ:1211267741QQ:1211267741 复制
    QQ:1034782288QQ:1034782288 复制
  • 159-7688-9073 QQ:1211267741QQ:1034782288
  • CS5532-ASZ图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • CS5532-ASZ 现货库存
  • 数量8000 
  • 厂家Cirrus Logic 
  • 封装SSOP-20 
  • 批号22+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • CS5532-ASZR图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • CS5532-ASZR 热卖库存
  • 数量2000 
  • 厂家CIRRUS LOGIC 
  • 封装TSSOP20 
  • 批号21+ 
  • CIRRUS专卖长期现货/批量样品支持长期供应■
  • QQ:2881664480QQ:2881664480 复制
  • 0755-83532193 QQ:2881664480
  • CS5532-ASZ图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • CS5532-ASZ
  • 数量5300 
  • 厂家CirrusLogic(凌云逻辑) 
  • 封装SSOP-20_208mil 
  • 批号21+ 
  • 全新原装正品,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • CS5532-ASZ图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • CS5532-ASZ
  • 数量8800 
  • 厂家CIRRUS 
  • 封装SSOP20 
  • 批号新年份 
  • 羿芯诚只做原装,原厂渠道,价格优势可谈!
  • QQ:2853992132QQ:2853992132 复制
  • 0755-82570683 QQ:2853992132
  • CS5532-ASZ图
  • 深圳市科庆电子有限公司

     该会员已使用本站16年以上
  • CS5532-ASZ
  • 数量2700 
  • 厂家CIRRUS 
  • 封装SSOP-20 
  • 批号23+ 
  • 现货只售原厂原装可含13%税
  • QQ:2850188252QQ:2850188252 复制
    QQ:2850188256QQ:2850188256 复制
  • 0755 QQ:2850188252QQ:2850188256
  • CS5532-ASZ/BSZ图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • CS5532-ASZ/BSZ
  • 数量10000 
  • 厂家 
  • 封装 
  • 批号16+ 
  • 特价,原装正品,绝对公司现货库存,原装特价!
  • QQ:2880824479QQ:2880824479 复制
  • 010-62104891 QQ:2880824479
  • CS5532-ASZ图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • CS5532-ASZ
  • 数量2300 
  • 厂家CYPRESS 
  • 封装SSOP 
  • 批号2020+ 
  • 全新原装进口现货特价热卖,长期供货
  • QQ:1327510916QQ:1327510916 复制
    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788
  • CS5532-ASZ图
  • 集好芯城

     该会员已使用本站13年以上
  • CS5532-ASZ
  • 数量14445 
  • 厂家CIRRUS 
  • 封装SSOP20 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • CS5532-ASZ图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • CS5532-ASZ
  • 数量1000 
  • 厂家CIRRUSLOG 
  • 封装TSSOP-20 
  • 批号2018+ 
  • 原装柜台现货电力系统专业经销
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • CS5532-ASZ图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • CS5532-ASZ
  • 数量32222 
  • 厂家CIRRUS LOGIC/凌云 
  • 封装SSOP 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • CS5532-ASZ图
  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • CS5532-ASZ
  • 数量5200 
  • 厂家CIRRUSLOGIC 
  • 封装TSSOP-20 
  • 批号20+ 
  • 全新原装现货优势产品
  • QQ:215672808QQ:215672808 复制
  • 0755-83229772 QQ:215672808
  • CS5532-ASZ图
  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
  • CS5532-ASZ
  • 数量3778 
  • 厂家Cirrus 
  • 封装原厂封装 
  • 批号22+ 
  • 原装正品★真实库存★价格优势★欢迎来电洽谈
  • QQ:1686616797QQ:1686616797 复制
    QQ:2440138151QQ:2440138151 复制
  • 0755-22655674 QQ:1686616797QQ:2440138151
  • CS5532-ASZ图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CS5532-ASZ
  • 数量5000 
  • 厂家Cirrus Logic Inc. 
  • 封装20-SSOP 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • CS5532-ASZ图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • CS5532-ASZ
  • 数量8500 
  • 厂家CIRRUS 
  • 封装TSSOP-20 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495
  • CS5532-ASZ图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CS5532-ASZ
  • 数量12500 
  • 厂家CIRRUS 
  • 封装66 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • CS5532-ASZ图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • CS5532-ASZ
  • 数量85000 
  • 厂家CirrusLogic(凌云逻辑) 
  • 封装SSOP-20_208mil 
  • 批号2023+ 
  • 原装现货特价
  • QQ:2885134398QQ:2885134398 复制
    QQ:2885134554QQ:2885134554 复制
  • 0755- QQ:2885134398QQ:2885134554
  • CS5532-ASZ图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • CS5532-ASZ
  • 数量18310 
  • 厂家CIRRUS 
  • 封装SSOP-20 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • CS5532-ASZ图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CS5532-ASZ
  • 数量5000 
  • 厂家Cirrus Logic Inc. 
  • 封装20-SSOP 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • CS5532-ASZ图
  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • CS5532-ASZ
  • 数量3850 
  • 厂家CirrusLogic(凌云逻辑) 
  • 封装SSOP-20_208mil 
  • 批号23+ 
  • ▉原装现货▉可含税可订货
  • QQ:3003797048QQ:3003797048 复制
    QQ:3003797050QQ:3003797050 复制
  • 0755-82779553 QQ:3003797048QQ:3003797050
  • CS5532-ASZ图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • CS5532-ASZ
  • 数量2368 
  • 厂家CIRRUS 
  • 封装TSSOP-20 
  • 批号▉▉:2年内 
  • ▉▉¥92.7元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • CS5532-ASZ图
  • 深圳市宇川湘科技有限公司

     该会员已使用本站6年以上
  • CS5532-ASZ
  • 数量23000 
  • 厂家Cirrus Logic Inc. 
  • 封装20-SSOP 
  • 批号23+ 
  • 原装正品现货,郑重承诺只做原装!
  • QQ:2885348305QQ:2885348305 复制
    QQ:2885348305QQ:2885348305 复制
  • 0755-84534256 QQ:2885348305QQ:2885348305
  • CS5532-ASZ图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • CS5532-ASZ
  • 数量50000 
  • 厂家CIRRUS 
  • 封装SSOP20 
  • 批号24+ 
  • 公司原装现货可含税!假一罚十!
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • CS5532-ASZ.图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • CS5532-ASZ.
  • 数量5000 
  • 厂家CIRRUS 
  • 封装SSOP-20 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931 QQ:857273081QQ:1594462451
  • CS5532-ASZ图
  • 深圳市银鑫达科技有限公司

     该会员已使用本站10年以上
  • CS5532-ASZ
  • 数量
  • 厂家2000 
  • 封装深圳现货、低价 
  • 批号CIRRUS代理 
  • TSSOP-20
  • QQ:1229556666QQ:1229556666 复制
    QQ:164547788QQ:164547788 复制
  • 0755-82802007 QQ:1229556666QQ:164547788
  • CS5532-ASZ图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • CS5532-ASZ
  • 数量8460 
  • 厂家CIRRUS代理 
  • 封装SOP-20 
  • 批号NEW 
  • 【优势库存】专业代理全新现货特价热卖
  • QQ:1134344845QQ:1134344845 复制
    QQ:847984313QQ:847984313 复制
  • 86-0755-83536093 QQ:1134344845QQ:847984313
  • CS5532-ASZ图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CS5532-ASZ
  • 数量70 
  • 厂家CIRRUS 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • CS5532-ASZ图
  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • CS5532-ASZ
  • 数量5800 
  • 厂家CIRRUS 
  • 封装SSOP 
  • 批号2024+ 
  • 全新原装现货,杜绝假货。
  • QQ:3003653665QQ:3003653665 复制
    QQ:1325513291QQ:1325513291 复制
  • 021-60341766 QQ:3003653665QQ:1325513291
  • CS5532-ASZ图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • CS5532-ASZ
  • 数量5000 
  • 厂家Cirrus Logic Inc. 
  • 封装20-SSOP 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 96-010-62104931 QQ:2880824479QQ:1344056792
  • CS5532-ASZ图
  • 深圳市中杰盛科技有限公司

     该会员已使用本站14年以上
  • CS5532-ASZ
  • 数量12000 
  • 厂家Cirrus Logic 
  • 封装SSOP-20 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:409801605QQ:409801605 复制
  • 0755-22968359 QQ:409801605

产品型号CS5532-ASZ的概述

芯片CS5532-ASZ的概述 CS5532-ASZ是一款高性能的模数转换器(ADC),广泛应用于工业测量、医疗设备、音频处理及其他要求高精度数据采集的场景。它具备多通道输入、低噪声性能以及高解析度,能够满足多种复杂应用需求。CS5532-ASZ由Cirrus Logic公司研发,是其ADC产品中的一款重要器件。 芯片CS5532-ASZ的详细参数 对于CS5532-ASZ来说,其性能参数至关重要。以下是该芯片的核心技术指标: - 转换方式: 逐次逼近(SAR) - 分辨率: 16位 - 输入通道数: 2通道差分输入(Analog Input) - 采样频率: 最大采样率为100 kSPS - 参考电压: 0V至Vref(可调范围) - 工作电压: 2.7V至5.25V - 功耗: 约为500µA(在工作状态下) - 数字接口: SPI或I2C(可选择) - 输入阻抗: 高达10 MΩ...

产品型号CS5532-ASZ的Datasheet PDF文件预览

CS5531/32/33/34-AS  
16-bit and 24-bit ADCs with Ultra-low-noise PGIA  
Features  
General Description  
The CS5531/32/33/34 are highly integrated ∆Σ Analog-  
to-Digital Converters (ADCs) which use charge-balance  
techniques to achieve 16-bit (CS5531/33) and 24-bit  
(CS5532/34) performance. The ADCs are optimized for  
measuring low-level unipolar or bipolar signals in weigh  
scale, process control, scientific, and medical  
applications.  
‰Chopper-stabilized PGIA (Programmable  
Gain Instrumentation Amplifier, 1x to 64x)  
12 nV/Hz @ 0.1 Hz (No 1/f noise) at 64x  
1200 pA Input Current with Gains >1  
‰Delta-sigma Analog-to-digital Converter  
Linearity Error: 0.0007% FS  
Noise Free Resolution: Up to 23 bits  
To accommodate these applications, the ADCs come as  
either two-channel (CS5531/32) or four-channel  
(CS5533/34) devices and include a very low noise chop-  
per-stabilized instrumentation amplifier (6 nV/Hz @ 0.1  
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and  
64×. These ADCs also include a fourth order ∆Σ modu-  
lator followed by a digital filter which provides twenty  
selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,  
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,  
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).  
‰Two- or Four-channel Differential MUX  
‰Scalable Input Span via Calibration  
±5 mV to differential ±2.5V  
‰Scalable V  
Input: Up to Analog Supply  
REF  
‰Simple Three-wire Serial Interface  
SPI™ and Microwire™ Compatible  
Schmitt Trigger on Serial Clock (SCLK)  
To ease communication between the ADCs and a micro-  
controller, the converters include a simple three-wire se-  
rial interface which is SPI and Microwire compatible with  
a Schmitt-trigger input on the serial clock (SCLK).  
‰R/W Calibration Registers Per Channel  
‰Selectable Word Rates: 6.25 to 3,840 Sps  
‰Selectable 50 or 60 Hz Rejection  
‰Power Supply Configurations  
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V  
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V  
VA+ = +3 V; VA- = -3 V; VD+ = +3 V  
High dynamic range, programmable output rates, and  
flexible power supply options makes these ADCs ideal  
solutions for weigh scale and process control  
applications.  
ORDERING INFORMATION  
See page 47  
VA+  
C1  
C2  
VREF+ VREF-  
VD+  
CS  
AIN1+  
AIN1-  
AIN2+  
AIN2-  
DIFFERENTIAL  
TH ORDER ∆Σ  
MODULATOR  
PGIA  
1,2,4,8,16  
32,64  
PROGRAMMABLE  
SINC FIR FILTER  
4
SDI  
SERIAL  
INTERFACE  
SDO  
MUX  
SCLK  
(CS5533/34  
SHOWN)  
AIN3+  
AIN3-  
CLOCK  
GENERATOR  
CALIBRATION  
SRAM/CONTROL  
LOGIC  
LATCH  
AIN4+  
AIN4-  
VA-  
A0/GUARD  
A1  
OSC1  
OSC2  
DGND  
OCT ‘08  
DS289F5  
Copyright © Cirrus Logic, Inc. 2008  
http://www.cirrus.com  
(All Rights Reserved)  
CS5531/32/33/34-AS  
TABLE OF CONTENTS  
1. CHARACTERISTICS AND SPECIFICATIONS ..........................................................4  
ANALOG CHARACTERISTICS..........................................................................4  
TYPICAL RMS NOISE (NV), CS5531/32/33/34 .................................................7  
TYPICAL NOISE-FREE RESOLUTION(BITS), CS5532/34...............................7  
5 V DIGITAL CHARACTERISTICS ....................................................................8  
3 V DIGITAL CHARACTERISTICS ....................................................................8  
DYNAMIC CHARACTERISTICS ........................................................................9  
ABSOLUTE MAXIMUM RATINGS .....................................................................9  
SWITCHING CHARACTERISTICS ..................................................................10  
2. GENERAL DESCRIPTION .......................................................................................12  
2.1. Analog Input ....................................................................................................12  
2.1.1. Analog Input Span .................................................................................... 13  
2.1.2. Multiplexed Settling Limitations ............................................................13  
2.1.3. Voltage Noise Density Performance .....................................................13  
2.1.4. No Offset DAC ......................................................................................14  
2.2. Overview of ADC Register Structure and Operating Modes ............................14  
2.2.1. System Initialization ..............................................................................15  
2.2.2. Serial Port Interface ..............................................................................22  
2.2.3. Reading/Writing On-Chip Registers ......................................................23  
2.3. Configuration Register .....................................................................................23  
2.3.1. Power Consumption .............................................................................23  
2.3.2. System Reset Sequence ......................................................................23  
2.3.3. Input Short ............................................................................................24  
2.3.4. Guard Signal .........................................................................................24  
2.3.5. Voltage Reference Select .....................................................................24  
2.3.6. Output Latch Pins .................................................................................24  
2.3.7. Offset and Gain Select ..........................................................................25  
2.3.8. Filter Rate Select ..................................................................................25  
2.4. Setting up the CSRs for a Measurement .........................................................27  
2.5. Calibration ........................................................................................................30  
2.5.1. Calibration Registers ............................................................................30  
2.5.2. Performing Calibrations ........................................................................31  
2.5.3. Self-calibration ......................................................................................31  
2.5.4. System Calibration ................................................................................32  
2.5.5. Calibration Tips .....................................................................................32  
2.5.6. Limitations in Calibration Range ...........................................................33  
2.6. Performing Conversions ..................................................................................33  
2.6.1. Single Conversion Mode .......................................................................33  
2.6.2. Continuous Conversion Mode ..............................................................34  
2.6.3. Examples of Using CSRs to Perform Conversions and Calibrations ....35  
2.7. Using Multiple ADCs Synchronously ...............................................................36  
2.8. Conversion Output Coding ..............................................................................36  
2.9. Digital Filter ......................................................................................................38  
2.10. Clock Generator ...............................................................................................39  
2.11. Power Supply Arrangements ...........................................................................39  
2.12. Getting Started ................................................................................................43  
2.13. PCB Layout .....................................................................................................43  
3. PIN DESCRIPTIONS ...............................................................................................44  
4. SPECIFICATION DEFINITIONS ...............................................................................46  
5. ORDERING INFORMATION .....................................................................................47  
6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ..............47  
7. PACKAGE DRAWINGS ...........................................................................................48  
2
DS289F5  
CS5531/32/33/34-AS  
LIST OF FIGURES  
Figure 1. SDI Write Timing (Not to Scale)...............................................................................11  
Figure 2. SDO Read Timing (Not to Scale).............................................................................11  
Figure 3. Multiplexer Configuration .........................................................................................12  
Figure 4. Input models for AIN+ and AIN- pins .......................................................................13  
Figure 5. Measured Voltage Noise Density.............................................................................13  
Figure 6. CS5531/32/33/34 Register Diagram........................................................................14  
Figure 7. Command and Data Word Timing ...........................................................................22  
Figure 8. Guard Signal Shielding Scheme..............................................................................24  
Figure 9. Input Reference Model when VRS = 1 ....................................................................25  
Figure 10. Input Reference Model when VRS = 0 ..................................................................25  
Figure 11. Self-calibration of Offset.........................................................................................32  
Figure 12. Self-calibration of Gain...........................................................................................32  
Figure 13. System Calibration of Offset ..................................................................................32  
Figure 14. System Calibration of Gain ....................................................................................32  
Figure 15. Synchronizing Multiple ADCs.................................................................................36  
Figure 16. Digital Filter Response (Word Rate = 60 Sps).......................................................38  
Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz ...............................................................38  
Figure 18. 120 Sps Filter Phase Plot to 120 Hz......................................................................38  
Figure 19. Z-Transforms of Digital Filters................................................................................38  
Figure 20. On-chip Oscillator Model........................................................................................39  
Figure 21. CS5532 Configured with a Single +5 V Supply .....................................................40  
Figure 22. CS5532 Configured with ±2.5 V Analog Supplies..................................................41  
Figure 23. CS5532 Configured with ±3 V Analog Supplies.....................................................41  
Figure 24. CS5532 Configured for Thermocouple Measurement ...........................................42  
Figure 25. Bridge with Series Resistors..................................................................................42  
LIST OF TABLES  
Table 1. Conversion Timing – Single Mode ............................................................................34  
Table 2. Conversion Timing – Continuous Mode....................................................................34  
Table 3. Command Byte Pointer.............................................................................................35  
Table 4. Output Coding for 16-bit CS5531 and CS5533.........................................................36  
Table 5. Output Coding for 24-bit CS5532 and CS5534.........................................................37  
DS289F5  
3
CS5531/32/33/34-AS  
1. CHARACTERISTICS AND SPECIFICATIONS  
ANALOG CHARACTERISTICS  
(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz;  
OWR (Output Word Rate) = 60 Sps; Bipolar Mode; Gain = 32)  
(See Notes 1 and 2.)  
CS5531/CS5533  
Parameter  
Min  
Typ  
Max  
Unit  
Accuracy  
Linearity Error  
No Missing Codes  
Bipolar Offset  
-
16  
-
0.0015  
0.003  
%FS  
Bits  
-
-
1
±2  
LSB  
LSB  
16  
16  
Unipolar Offset  
-
2
4
Offset Drift  
(Notes 3 and 4)  
(Note 4)  
-
-
-
-
10  
8
-
nV/°C  
ppm  
Bipolar Full-scale Error  
Unipolar Full-scale Error  
Full-scale Drift  
31  
62  
-
16  
2
ppm  
ppm/°C  
CS5532/CS5534  
Parameter  
Min  
Typ  
Max  
Unit  
Accuracy  
Linearity Error  
No Missing Codes  
Bipolar Offset  
-
24  
-
0.0015  
0.003  
-
%FS  
Bits  
-
16  
±32  
LSB  
LSB  
24  
24  
Unipolar Offset  
-
32  
64  
Offset Drift  
(Notes 3 and 4)  
(Note 4)  
-
-
-
-
10  
8
-
nV/°C  
ppm  
Bipolar Full-scale Error  
Unipolar Full-scale Error  
Full-scale Drift  
31  
62  
-
16  
2
ppm  
ppm/°C  
Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.  
2. Specifications guaranteed by design, characterization, and/or test. LSB is 16 bits for the CS5531/33 and  
LSB is 24 bits for the CS5532/34.  
3. This specification applies to the device only and does not include any effects by external parasitic  
thermocouples.  
4. Drift over specified temperature range after calibration at power-up at 25 °C.  
4
DS289F5  
CS5531/32/33/34-AS  
ANALOG CHARACTERISTICS (Continued)  
(See Notes 1 and 2.)  
Parameter  
Min  
Typ  
Max  
Unit  
Analog Input  
Common Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode  
Gain = 1  
Gain = 2, 4, 8, 16, 32, 64  
VA-  
-
-
VA+  
VA+ - 1.7  
V
V
(Note 5) VA- + 0.7  
CVF Current on AIN+ or AIN-  
Input Current Noise  
Gain = 1  
Gain = 2, 4, 8, 16, 32, 64  
(Note 6, 7)  
-
-
50  
1200  
-
-
nA  
pA  
Gain = 1  
Gain = 2, 4, 8, 16, 32, 64  
-
-
200  
1
-
-
pA/Hz  
pA/Hz  
Input Leakage for Mux when Off (at 25 °C)  
Off-channel Mux Isolation  
-
-
10  
-
-
-
pA  
dB  
nA  
120  
300  
Open Circuit Detect Current  
100  
Common Mode Rejection  
dc, Gain = 1  
dc, Gain = 64  
50, 60 Hz  
-
-
-
90  
130  
120  
-
-
-
dB  
dB  
dB  
Input Capacitance  
Guard Drive Output  
Voltage Reference Input  
Range  
-
-
60  
20  
-
-
pF  
µA  
(VREF+) - (VREF-)  
1
-
2.5 (VA+)-(VA-)  
V
CVF Current  
(Note 6, 7)  
50  
-
nA  
Common Mode Rejection  
dc  
-
-
120  
120  
-
-
dB  
dB  
50, 60 Hz  
Input Capacitance  
11  
-
22  
pF  
System Calibration Specifications  
Full-scale Calibration Range  
Offset Calibration Range  
Offset Calibration Range  
Bipolar/Unipolar Mode  
Bipolar Mode  
3
-
-
-
110  
100  
90  
%FS  
%FS  
%FS  
-100  
-90  
Unipolar Mode  
Notes: 5. The voltage on the analog inputs is amplified by the PGIA, and becomes V  
Gain*(AIN+ - AIN-)/2 at  
CM  
the differential outputs of the amplifier. In addition to the input common mode + signal requirements for  
the analog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and  
(VA+ - 0.1 V) to avoid saturation of the output stage.  
6. See the section of the data sheet which discusses input models.  
7. Input current on AIN+ or AIN- (with Gain = 1), or VREF+ or VREF- may increase to 250 nA if operated  
within 50 mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these  
conditions.  
DS289F5  
5
CS5531/32/33/34-AS  
ANALOG CHARACTERISTICS (Continued)  
(See Notes 1 and 2.)  
Max  
Parameter  
Min  
Typ  
Unit  
Power Supplies  
DC Power Supply Currents (Normal Mode)  
I
I
I
-
-
6
0.6  
8
1
mA  
mA  
A+, A-  
D+  
Power Consumption  
Normal Mode  
Standby  
Sleep  
(Notes 8 and 9)  
(Note 10)  
-
-
-
35  
5
500  
45  
-
-
mW  
mW  
µW  
Power Supply Rejection  
dc Positive Supplies  
dc Negative Supply  
-
-
115  
115  
-
-
dB  
dB  
8. All outputs unloaded. All input CMOS levels.  
9. Power is specified when the instrumentation amplifier (Gain 2) is on. Analog supply current is reduced  
by approximately 1/2 when the instrumentation amplifier is off (Gain = 1).  
10. Tested with 100 mV change on VA+ or VA-.  
6
DS289F5  
CS5531/32/33/34-AS  
TYPICAL RMS NOISE (nV), CS5531/32/33/34  
(See notes 11, 12 and 13)  
Instrumentation Amplifier Gain  
Output Word  
-3 dB Filter  
Rate (Sps)  
Frequency (Hz)  
x64  
17  
24  
34  
48  
x32  
17  
25  
35  
49  
x16  
19  
27  
39  
54  
x8  
26  
36  
51  
72  
102  
527  
748  
1060  
1840  
10800  
x4  
42  
59  
84  
118  
x2  
79  
111  
157  
222  
x1  
155  
218  
308  
436  
7.5  
15  
30  
60  
120  
240  
480  
960  
1.94  
3.88  
7.75  
15.5  
31  
68  
70  
77  
167  
314  
616  
62  
115  
163  
229  
344  
1390  
160  
230  
321  
523  
2710  
276  
392  
554  
946  
5390  
1040  
1480  
2090  
3650  
21500  
2070  
2950  
4170  
7290  
43000  
4150  
5890  
8340  
14600  
86100  
122  
230  
390  
780  
1,920  
3,840  
Notes: 11. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.  
12. For peak-to-peak noise multiply by 6.6 for all ranges and output rates.  
13. Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.  
TYPICAL NOISE-FREE RESOLUTION(BITS), CS5532/34 (See Notes 14 and 15)  
Instrumentation Amplifier Gain  
Output Word  
-3 dB Filter  
Rate (Sps)  
Frequency (Hz)  
x64  
19  
19  
18  
18  
17  
16  
16  
15  
15  
13  
x32  
20  
20  
19  
19  
18  
17  
17  
16  
15  
13  
x16  
21  
21  
20  
20  
19  
17  
17  
16  
15  
13  
x8  
22  
21  
21  
20  
20  
17  
17  
16  
15  
13  
x4  
22  
21  
21  
20  
20  
17  
17  
16  
15  
13  
x2  
22  
22  
21  
21  
20  
17  
17  
16  
15  
13  
x1  
22  
22  
21  
21  
20  
17  
17  
16  
15  
13  
7.5  
15  
30  
60  
120  
240  
480  
960  
1.94  
3.88  
7.75  
15.5  
31  
62  
122  
230  
390  
780  
1,920  
3,840  
14. Noise-free resolution listed is for bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMS  
Noise))/LOG(2) rounded to the nearest bit. For unipolar operation, the input span is 1/2 as large, so one  
bit is lost. The input span is calculated in the analog input span section of the data sheet. The noise-free  
resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the  
noise, and change the noise-free resolution accordingly.  
15. “Noise-free resolution” is not the same as “effective resolution”. Effective resolution is based on the  
RMS noise value, while noise-free resolution is based on a peak-to-peak noise value specified as 6.6  
times the RMS noise value. Effective resolution is calculated as LOG((Input Span)/(RMS  
Noise))/LOG(2).  
Specifications are subject to change without notice.  
DS289F5  
7
CS5531/32/33/34-AS  
5 V DIGITAL CHARACTERISTICS  
(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V;  
See Notes 2 and 16.)  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
High-level Input Voltage  
Low-level Input Voltage  
High-level Output Voltage  
All Pins Except SCLK  
V
0.6 VD+  
(VD+) - 0.45  
-
-
VD+  
VD+  
V
IH  
SCLK  
All Pins Except SCLK  
SCLK  
V
0.0  
0.0  
-
0.8  
0.6  
V
V
IL  
A0 and A1, I = -1.0 mA  
V
(VA+) - 1.0  
(VD+) - 1.0  
-
-
out  
OH  
SDO, I = -5.0 mA  
out  
Low-level Output Voltage  
A0 and A1, I = 1.0 mA  
V
I
-
-
(VA-) + 0.4  
0.4  
V
out  
OL  
SDO, I = 5.0 mA  
out  
Input Leakage Current  
-
-
-
±1  
-
±10  
±10  
-
µA  
µA  
pF  
in  
SDO Tri-state Leakage Current  
Digital Output Pin Capacitance  
I
OZ  
C
9
out  
3 V DIGITAL CHARACTERISTICS  
(T = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V;  
A
See Notes 2 and 16.)  
Parameter  
High-level Input Voltage  
Symbol  
Min  
Typ  
Max  
Unit  
All Pins Except SCLK  
SCLK  
V
0.6 VD+  
(VD+) - 0.45  
-
VD+  
VD+  
V
IH  
Low-level Input Voltage  
High-level Output Voltage  
All Pins Except SCLK  
SCLK  
V
0.0  
0.0  
-
-
0.8  
0.6  
V
V
IL  
A0 and A1, I = -1.0 mA  
V
(VA+) - 1.0  
(VD+) - 1.0  
-
out  
OH  
SDO, I = -5.0 mA  
out  
Low-level Output Voltage  
A0 and A1, I = 1.0 mA  
V
-
-
(VA-) + 0.4  
0.4  
V
out  
OL  
SDO, I = 5.0 mA  
out  
Input Leakage Current  
I
-
-
-
±1  
-
±10  
±10  
-
µA  
µA  
pF  
in  
SDO Tri-state Leakage Current  
Digital Output Pin Capacitance  
I
OZ  
C
9
out  
16. All measurements performed under static conditions.  
8
DS289F5  
CS5531/32/33/34-AS  
DYNAMIC CHARACTERISTICS  
Parameter  
Symbol  
Ratio  
Unit  
Modulator Sampling Rate  
f
MCLK/16  
Sps  
s
Filter Settling Time to 1/2 LSB (Full-scale Step Input)  
Single Conversion mode (Notes 17, 18, and 19)  
Continuous Conversion mode, OWR < 3200 Sps  
Continuous Conversion mode, OWR 3200 Sps  
t
t
t
1/OWR  
s
s
s
s
s
s
SC  
5/OWR  
+ 3/OWR  
sinc5  
5/OWR  
5
5
17. The ADCs use a Sinc filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc filter  
3
followed by a Sinc filter for the other OWRs. OWR  
(FRS = 0) word rate associated with the Sinc filter.  
refers to the 3200 Sps (FRS = 1) or 3840 Sps  
sinc5  
5
18. The single conversion mode only outputs fully settled conversions. See Table 1 for more details about  
single conversion mode timing. OWR is used here to designate the different conversion time  
SC  
associated with single conversions.  
19. The continuous conversion mode outputs every conversion. This means that the filter’s settling time  
with a full-scale step input in the continuous conversion mode is dictated by the OWR.  
ABSOLUTE MAXIMUM RATINGS  
(DGND = 0 V; See Note 20.)  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
DC Power Supplies  
(Notes 21 and 22)  
Positive Digital  
Positive Analog  
Negative Analog  
VD+  
VA+  
VA-  
-0.3  
-0.3  
+0.3  
-
-
-
+6.0  
+6.0  
-3.75  
V
V
V
Input Current, Any Pin Except Supplies (Notes 23 and 24)  
Output Current  
I
-
-
-
-
-
-
±10  
±25  
500  
mA  
mA  
mW  
IN  
I
OUT  
Power Dissipation  
(Note 25)  
PDN  
Analog Input Voltage  
VREF pins  
AIN Pins  
V
V
(VA-) -0.3  
(VA-) -0.3  
-
-
(VA+) + 0.3  
(VA+) + 0.3  
V
V
INR  
INA  
Digital Input Voltage  
V
-0.3  
-40  
-65  
-
-
-
(VD+) + 0.3  
V
IND  
Ambient Operating Temperature  
Storage Temperature  
T
85  
°C  
°C  
A
T
150  
stg  
Notes: 20. All voltages with respect to ground.  
21. VA+ and VA- must satisfy {(VA+) - (VA-)} +6.6 V.  
22. VD+ and VA- must satisfy {(VD+) - (VA-)} +7.5 V.  
23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.  
24. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power  
supply pin is ±50 mA.  
25. Total power dissipation, including all input currents and output currents.  
WARNING: Operation at or beyond these limits may result in permanent damage to the device.  
Normal operation is not guaranteed at these extremes.  
DS289F5  
9
CS5531/32/33/34-AS  
SWITCHING CHARACTERISTICS  
(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V;  
Levels: Logic 0 = 0 V, Logic 1 = VD+; C = 50 pF; See Figures 1 and 2.)  
L
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Master Clock Frequency  
(Note 26)  
MCLK  
External Clock or Crystal Oscillator  
1
4.9152  
-
5
MHz  
%
Master Clock Duty Cycle  
Rise Times  
40  
60  
(Note 27)  
Any Digital Input Except SCLK  
SCLK  
t
rise  
-
-
-
-
-
50  
1.0  
100  
-
µs  
µs  
ns  
Any Digital Output  
Fall Times  
(Note 27)  
Any Digital Input Except SCLK  
SCLK  
t
fall  
-
-
-
-
-
50  
1.0  
100  
-
µs  
µs  
ns  
Any Digital Output  
Start-up  
Oscillator Start-up Time  
XTAL = 4.9152 MHz (Note 28)  
t
-
20  
-
ms  
ost  
Serial Port Timing  
Serial Clock Frequency  
Serial Clock  
SCLK  
0
-
2
MHz  
Pulse Width High  
Pulse Width Low  
t
t
250  
250  
-
-
-
-
ns  
ns  
1
2
SDI Write Timing  
CS Enable to Valid Latch Clock  
Data Set-up Time prior to SCLK rising  
Data Hold Time After SCLK Rising  
SCLK Falling Prior to CS Disable  
t
t
t
t
50  
50  
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
3
4
5
6
100  
100  
SDO Read Timing  
CS to Data Valid  
t
t
t
-
-
-
-
-
-
150  
150  
150  
ns  
ns  
ns  
7
8
9
SCLK Falling to New Data Bit  
CS Rising to SDO Hi-Z  
Notes: 26. Device parameters are specified with a 4.9152 MHz clock.  
27. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.  
28. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an  
external clock source.  
10  
DS289F5  
CS5531/32/33/34-AS  
C S  
t3  
SD I  
M SB  
M SB -1  
LSB  
t4  
t5  
t1  
t6  
SC LK  
t2  
Figure 1. SDI Write Timing (Not to Scale)  
C S  
t7  
t9  
S D O  
M S B  
M SB -1  
LSB  
t8  
t2  
SC LK  
t1  
Figure 2. SDO Read Timing (Not to Scale)  
DS289F5  
11  
CS5531/32/33/34-AS  
2. GENERAL DESCRIPTION  
The CS5531/32/33/34 are highly integrated ∆Σ An-  
alog-to-Digital Converters (ADCs) which use  
charge-balance techniques to achieve 16-bit  
(CS5531/33) and 24-bit (CS5532/34) performance.  
The ADCs are optimized for measuring low-level  
unipolar or bipolar signals in weigh scale, process  
control, scientific, and medical applications.  
crowire compatible with a Schmitt-trigger input on  
the serial clock (SCLK).  
2.1. Analog Input  
Figure 3 illustrates a block diagram of the  
CS5531/32/33/34. The front end consists of a multi-  
plexer, a unity gain coarse/fine charge input buffer,  
and a programmable gain chopper-stabilized instru-  
mentation amplifier. The unity gain buffer is activat-  
ed any time conversions are performed with a gain  
of one and the instrumentation amplifier is activated  
any time conversions are performed with gain set-  
tings greater than one.  
To accommodate these applications, the ADCs  
come as either two-channel (CS5531/32) or four-  
channel (CS5533/34) devices and include a very-  
low-noise, chopper-stabilized, programmable-gain  
instrumentation amplifier (PGIA, 6 nV/Hz @ 0.1  
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×,  
32×, and 64×. These ADCs also include a fourth or-  
der ∆Σ modulator followed by a digital filter which  
provides twenty selectable output word rates of 6.25,  
7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400,  
480, 800, 960, 1600, 1920, 3200, and 3840 Samples  
per second (MCLK = 4.9152 MHz).  
The unity gain buffer is designed to accommodate  
rail to rail input signals. The common-mode plus  
signal range for the unity gain buffer amplifier is  
VA- to VA+. Typical CVF (sampling) current for  
the unity gain buffer amplifier is about 50 nA  
(MCLK = 4.9152 MHz, see Figure 4).  
The instrumentation amplifier is chopper stabilized  
and operates with a chop clock frequency of  
MCLK/128. The CVF (sampling) current into the  
To ease communication between the ADCs and a  
microcontroller, the converters include a simple  
three-wire serial interface which is SPI and Mi-  
VREF+ VREF-  
IN+  
IN-  
CS5531/32  
AIN2+  
AIN2-  
AIN1+  
AIN1-  
X1  
X1  
M
U
X
X1  
1000  
Differential  
5
Programmable  
Sinc  
Digital Filter  
Sinc  
Digital  
Filter  
IN+  
IN-  
th  
C1 PIN  
C2 PIN  
4
Order  
∆Σ  
Modulator  
3
Serial  
Port  
22 nF  
XGAIN  
AIN4+  
AIN4-  
CS5533/34  
1000  
IN+  
IN-  
*
*
*
X1  
M
U
X
AIN1+  
AIN1-  
GAIN is the gain setting of the PGIA (i.e. 2, 4, 8, 16, 32, 64)  
Figure 3. Multiplexer Configuration  
12  
DS289F5  
CS5531/32/33/34-AS  
instrumentation amplifier is typically 1200 pA Select bit, and must be set according to the differen-  
over  
-40°C to +85°C (MCLK=4.9152 MHz). tial voltage applied to the VREF+ and VREF- pins  
The common-mode plus signal range of the instru-  
mentation amplifier is (VA-) + 0.7 V to (VA+) -  
1.7 V.  
on the part. See section 2.3.5 for more details.  
After reset, the unity gain buffer is engaged. With a  
2.5V reference this would make the full-scale input  
range default to 2.5 V. By activating the instrumen-  
tation amplifier (i.e. a gain setting other than 1) and  
using a gain setting of 32, the full-scale input range  
can quickly be set to 2.5/32 or about 78 mV. Note  
that these input ranges assume the calibration regis-  
ters are set to their default values (i.e. Gain = 1.0 and  
Offset = 0.0).  
Figure 4 illustrates the input models for the ampli-  
fiers. The dynamic input current for each of the  
pins can be determined from the models shown.  
Gain = 2, 4, 8, 16, 32, 64  
AIN  
= 3 .9 pF  
C
2.1.2. Multiplexed Settling Limitations  
= fV  
V
8 mV  
The settling performance of the CS5531/32/33/34  
in multiplexed applications is affected by the sin-  
gle-pole, low-pass filter which follows the instru-  
mentation amplifier (see Figure 3). To achieve data  
sheet settling and linearity specifications, it is rec-  
ommended that a 22 nF C0G capacitor be used.  
Capacitors as low as 10 nF or X7R type capacitors  
can also be used with some minor increase in dis-  
tortion for AC signals.  
os  
i
C
n
os  
MCLK  
128  
f =  
Gain = 1  
φ
Fine  
1
φ
Coarse  
1
AIN  
C = 14 pF  
V
12 mV  
os  
= fV  
i
C
n
os  
2.1.3. Voltage Noise Density Performance  
MCLK  
16  
f =  
Figure 5 illustrates the measured voltage noise  
density versus frequency from 0.025 Hz to 10 Hz  
of a CS5532-AS. The device was powered with  
±2.5 V supplies, using 30 Sps OWR, the 64x gain  
range, bipolar mode, and with the input short bit  
enabled.  
Figure 4. Input models for AIN+ and AIN- pins  
Note:  
The C=3.9pF and C = 14pF capacitors are  
for input current modeling only. For physical  
input capacitance see ‘Input Capacitance’  
specification under Analog Characteristics.  
1000  
100  
10  
2.1.1. Analog Input Span  
The full-scale input signal that the converter can  
digitize is a function of the gain setting and the ref-  
erence voltage connected between the VREF+ and  
VREF- pins. The full-scale input span of the con-  
verter is [(VREF+) - (VREF-)]/(GxA), where G is  
the gain of the amplifier and A is 2 for VRS = 0, or  
A is 1 for VRS = 1. VRS is the Voltage Reference  
1
0.025  
0.10  
1.00  
Frequency (Hz)  
10.00  
Figure 5. Measured Voltage Noise Density, 64x  
DS289F5  
13  
CS5531/32/33/34-AS  
2.1.4. No Offset DAC  
converters with four channels have four offset and  
four gain calibration registers. These registers hold  
calibration results. The contents of these registers  
can be read or written by the user. This allows cal-  
ibration data to be off-loaded into an external EE-  
PROM. The user can also manipulate the contents  
of these registers to modify the offset or the gain  
slope of the converter.  
An offset DAC was not included in the CS553X  
family because the high dynamic range of the con-  
verter eliminates the need for one. The offset regis-  
ter can be manipulated by the user to mimic the  
function of a DAC if desired.  
2.2. Overview of ADC Register Structure  
and Operating Modes  
The converters include a 32-bit configuration reg-  
ister which is used for setting options such as the  
power down modes, resetting the converter, short-  
ing the analog inputs, and enabling diagnostic test  
bits like the guard signal.  
The CS5531/32/33/34 ADCs have an on-chip con-  
troller, which includes a number of user-accessible  
registers. The registers are used to hold offset and  
gain calibration results, configure the chip's operat-  
ing modes, hold conversion instructions, and to  
store conversion data words. Figure 6 depicts a  
block diagram of the on-chip controller’s internal  
registers.  
A group of registers, called Channel Setup Regis-  
ters, are used to hold pre-loaded conversion in-  
structions. Each channel setup register is 32 bits  
long, and holds two 16-bit conversion instructions  
referred to as Setups. Upon power up, these regis-  
ters can be initialized by the system microcontrol-  
ler with conversion instructions. The user can then  
Each of the converters has 32-bit registers to func-  
tion as offset and gain calibration registers for each  
channel. The converters with two channels have  
two offset and two gain calibration registers, the  
Channel Setup  
Registers (4 x 32)  
Conversion Data  
Register (1 x 32)  
Offset Registers (4 x 32)  
Offset 1 (1 x 32)  
Gain Registers (4 x 32)  
Gain 1 (1 x 32)  
Setup 1  
(1 x 16)  
Setup 2  
(1 x 16)  
Data (1 x 32)  
Setup 3  
(1 x 16)  
Setup 4  
(1 x 16)  
Offset 2 (1 x 32)  
Offset 3 (1 x 32)  
Offset 4 (1 x 32)  
Gain 2 (1 x 32)  
Gain 3 (1 x 32)  
Gain 4 (1 x 32)  
Setup 5  
(1 x 16)  
Setup 6  
(1 x 16)  
Setup 7  
(1 x 16)  
Setup 8  
(1 x 16)  
CS  
SDI  
Serial  
SDO  
SCLK  
Interface  
Configuration Register (1 x 32)  
Power Save Select  
Reset System  
Input Short  
Channel Select  
Gain  
Word Rate  
Command  
Register (1 × 8)  
Guard Signal  
Voltage Reference Select  
Output Latch  
Unipolar/Bipolar  
Output Latch  
Delay Time  
Output Latch Select  
Offset/Gain Select  
Open Circuit Detect  
Offset/Gain Pointer  
Filter Rate Select  
Figure 6. CS5531/32/33/34 Register Diagram  
14  
DS289F5  
CS5531/32/33/34-AS  
instruct the converter to perform single or multiple  
This sequence resets the serial port to the command  
conversions or calibrations with the converter in mode and is accomplished by transmitting at least  
the mode defined by one of these Setups.  
15 SYNC1 command bytes (0xFF hexadecimal),  
followed by one SYNC0 command (0xFE hexa-  
decimal). Note that this sequence can be initiated at  
anytime to reinitialize the serial port. To complete  
the system initialization sequence, the user must  
also perform a system reset sequence which is as  
follows: Write a logic 1 into the RS bit of the con-  
figuration register. This will reset the calibration  
registers and other logic (but not the serial port). A  
valid reset will set the RV bit in the configuration  
register to a logic 1. After writing the RS bit to a  
logic 1, wait 20 microseconds, then write the RS bit  
back to logic 0. While this involves writing an en-  
tire word into the configuration register, the RV bit  
is a read only bit, therefore a write to the configu-  
ration register will not overwrite the RV bit. After  
clearing the RS bit back to logic 0, read the config-  
uration register to check the state of the RV bit as  
this indicates that a valid reset occurred. Reading  
the configuration register clears the RV bit back to  
logic 0.  
Using the single conversion mode, an 8-bit com-  
mand word can be written into the serial port. The  
command includes pointer bits which ‘point’ to a  
16-bit command in one of the Channel Setup Reg-  
isters which is to be executed. The 16-bit Setups  
can be programmed to perform a conversion on any  
of the input channels of the converter. More than  
one of the 16-bit Setups can be used for the same  
analog input channel. This allows the user to con-  
vert on the same signal with either a different con-  
version speed, a different gain range, or any of the  
other options available in the channel setup regis-  
ters. Alternately, the user can set up the registers to  
perform different conversion conditions on each of  
the input channels.  
The ADCs also include continuous conversion ca-  
pability. The ADCs can be instructed to continu-  
ously convert, referencing one 16-bit command  
Setup. In the continuous conversions mode, the  
conversion data words are loaded into a shift regis-  
ter. The converter issues a flag on the SDO pin  
when a conversion cycle is completed so the user  
can read the register, if need be. See the section on  
Performing Conversions for more details.  
Completing the reset cycle initializes the on-chip  
registers to the following states:  
Configuration Register:  
Offset Registers:  
Gain Registers:  
00000000(H)  
00000000(H)  
01000000(H)  
The following pages document how to initialize the  
converter, perform offset and gain calibrations, and  
how to configure the converter for the various con-  
version modes. Each of the bits of the configuration  
register and of the Channel Setup Registers is de-  
scribed. A list of examples follows the description  
section. Also the Command Register Quick Refer-  
ence can be used to decode all valid commands (the  
first 8-bits into the serial port).  
Channel Setup Registers: 00000000(H)  
Note:  
Previous datasheets stated that the RS bit  
would clear itself back to logic 0 and therefore  
the user was not required to write the RS bit  
back to logic 0. The current data sheet  
instruction that requires the user to write into  
the configuration register to clear the RS bit  
has been added to insure that the RS bit is  
cleared. Characterizationacrossmultiplelots  
of silicon has indicated some chips do not  
automatically reset the RS bit to logic 0 in the  
configuration register, although the reset  
function is completed. This occurs only on  
small number of chips when the VA- supply is  
negative with respect to DGND. This has not  
2.2.1. System Initialization  
The CS5531/32/33/34 provide no power-on-reset  
function. To initialize the ADCs, the user must per-  
form a software reset by resetting the ADC’s serial  
port with the Serial Port Initialization sequence.  
DS289F5  
15  
CS5531/32/33/34-AS  
caused an operational issue for customers  
because their start-up sequence includes  
writing a word (with RS=0) into the  
configuration register after performing a  
reset. The change in the reset sequence to  
include writing the RS bit back to 0 insures  
the clearing of the RS bit in the event that a  
user does not write into the configuration  
register after the RS bit has been set.  
reset cycle. After a system initialization or reset,  
the on-chip controller is initialized into command  
mode where it waits for a valid command (the first  
8-bits written into the serial port are shifted into the  
command register). Once a valid command is re-  
ceived and decoded, the byte instructs the converter  
to either acquire data from or transfer data to an in-  
ternal register(s), or perform a conversion or a cal-  
ibration. The Command Register Descriptions  
section can be used to decode all valid commands.  
The RV bit in the Configuration Register is set to  
indicate a valid reset has occurred. The RS bit  
should be written back to logic “0” to complete the  
16  
DS289F5  
CS5531/32/33/34-AS  
2.2.2. Command Register Quick Reference  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
ARA  
CS1  
CS0  
R/W  
RSB2  
RSB1  
RSB0  
BIT  
NAME  
VALUE FUNCTION  
D7  
Command Bit, C  
0
1
Must be logic 0 for these commands.  
These commands are invalid if this bit is logic 1.  
D6  
Access Registers as  
Arrays, ARA  
0
1
Ignore this function.  
Access the respective registers, offset, gain, or channel-setup, as an array of regis-  
ters. The particular registers accessed are determined by the RS bits. The registers  
are accessed MSB first with physical channel 0 accessed first followed by physical  
channel 1 next and so forth.  
D5-D4 Channel Select Bits,  
CS1-CS0  
00  
01  
10  
11  
CS1-CS0 provide the address of one of the two (four for CS5533/34) physical input  
channels. These bits are also used to access the calibration registers associated  
with the respective physical input channel. Note that these bits are ignored when  
reading data register.  
D3  
Read/Write, R/W  
0
1
Write to selected register.  
Read from selected register.  
D2-D0 Register Select Bit,  
RSB3-RSB0  
000  
001  
010  
011  
101  
110  
111  
Reserved  
Offset Register  
Gain Register  
Configuration Register  
Channel-Setup Registers  
Reserved  
Reserved  
D7(MSB)  
D6  
D5  
CSRP2  
D4  
D3  
D2  
D1  
D0  
1
MC  
CSRP1  
CSRP0  
CC2  
CC1  
CC0  
BIT  
NAME  
VALUE FUNCTION  
D7  
Command Bit, C  
0
1
These commands are invalid if this bit is logic 0.  
Must be logic 1 for these commands.  
D6  
Multiple Conver-  
sions, MC  
0
1
Perform fully settled single conversions.  
Perform conversions continuously.  
D5-D3 Channel-Setup Reg-  
ister Pointer Bits,  
CSRP  
000  
...  
111  
These bits are used as pointers to the Channel-Setup registers. Either a single con-  
version or continuous conversions are performed on the channel setup register  
pointed to by these bits.  
D2-D0 Conversion/Calibra-  
tion Bits, CC2-CC0  
000  
001  
010  
011  
100  
101  
110  
111  
Normal Conversion  
Self-Offset Calibration  
Self-Gain Calibration  
Reserved  
Reserved  
System-Offset Calibration  
System-Gain Calibration  
Reserved  
DS289F5  
17  
CS5531/32/33/34-AS  
2.2.3. Command Register Descriptions  
READ/WRITE ALL OFFSET CALIBRATION REGISTERS  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
1
0
0
R/W  
0
0
1
Function:  
These commands are used to access the offset registers as arrays.  
R/W (Read/Write)  
0
1
Write to selected registers.  
Read from selected registers.  
READ/WRITE ALL GAIN CALIBRATION REGISTERS  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
1
0
0
R/W  
0
1
0
Function:  
These commands are used to access the gain registers as arrays.  
R/W (Read/Write)  
0
1
Write to selected registers.  
Read from selected registers.  
READ/WRITE ALL CHANNEL-SETUP REGISTERS  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
1
0
0
R/W  
1
0
1
Function:  
These commands are used to access the channel-setup registers as arrays.  
R/W (Read/Write)  
0
1
Write to selected registers.  
Read from selected registers.  
READ/WRITE INDIVIDUAL OFFSET REGISTER  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
CS1  
CS0  
R/W  
0
0
1
Function:  
These commands are used to access each offset register separately. CS1 - CS0 decode the  
registers accessed.  
R/W (Read/Write)  
0
1
Write to selected register.  
Read from selected register.  
CS[1:0] (Channel Select Bits)  
00  
01  
10  
11  
Offset Register 1 (All devices)  
Offset Register 2 (All devices)  
Offset Register 3 (CS5533/34 only)  
Offset Register 4 (CS5533/34 only)  
18  
DS289F5  
CS5531/32/33/34-AS  
READ/WRITE INDIVIDUAL GAIN REGISTER  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
CS1  
CS0  
R/W  
0
1
0
Function:  
These commands are used to access each gain register separately. CS1 - CS0 decode the reg-  
isters accessed.  
R/W (Read/Write)  
0
1
Write to selected register.  
Read from selected register.  
CS[1:0] (Channel Select Bits)  
00  
01  
10  
11  
Gain Register 1 (All devices)  
Gain Register 2 (All devices)  
Gain Register 3 (CS5533/34 only)  
Gain Register 4 (CS5533/34 only)  
READ/WRITE INDIVIDUAL CHANNEL-SETUP REGISTER  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
CS1  
CS0  
R/W  
1
0
1
Function:  
These commands are used to access each channel-setup register separately. CS1 - CS0 de-  
code the registers accessed.  
R/W (Read/Write)  
0
1
Write to selected register.  
Read from selected register.  
CS[1:0] (Channel Select Bits)  
00  
01  
10  
11  
Channel-Setup Register 1 (All devices)  
Channel-Setup Register 2 (All devices)  
Channel-Setup Register 3 (All devices)  
Channel-Setup Register 4 (All devices)  
READ/WRITE CONFIGURATION REGISTER  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
0
0
R/W  
0
1
1
Function:  
These commands are used to read from or write to the configuration register.  
R/W (Read/Write)  
0
1
Write to selected register.  
Read from selected register.  
DS289F5  
19  
CS5531/32/33/34-AS  
PERFORM CONVERSION  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
1
MC  
CSRP2  
CSRP1  
CSRP0  
0
0
0
Function:  
These commands instruct the ADC to perform either a single, fully-settled conversion or con-  
tinuous conversions on the physical input channel pointed to by the pointer bits (CSRP2 -  
CRSP0) in the channel-setup register.  
MC (Multiple Conversions)  
0
1
Perform a single conversion.  
Perform continuous conversions.  
CSRP [2:0] (Channel Setup Register Pointer Bits)  
000  
001  
010  
011  
100  
101  
110  
111  
Setup 1 (All devices)  
Setup 2 (All devices)  
Setup 3 (All devices)  
Setup 4 (All devices)  
Setup 5 (All devices)  
Setup 6 (All devices)  
Setup 7 (All devices)  
Setup 8 (All devices)  
20  
DS289F5  
CS5531/32/33/34-AS  
PERFORM CALIBRATION  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
1
0
CSRP2  
CSRP1  
CSRP0  
CC2  
CC1  
CC0  
Function:  
These commands instruct the ADC to perform a calibration on the physical input channel se-  
lected by the setup register which is chosen by the command byte pointer bits (CSRP2 -  
CSRP0).  
CSRP [2:0] (Channel Setup Register Pointer Bits)  
000  
001  
010  
011  
100  
101  
110  
111  
Setup 1 (All devices)  
Setup 2 (All devices)  
Setup 3 (All devices)  
Setup 4 (All devices)  
Setup 5 (All devices)  
Setup 6 (All devices)  
Setup 7 (All devices)  
Setup 8 (All devices)  
CC [2:0] (Calibration Control Bits)  
000  
001  
010  
011  
100  
101  
110  
111  
Reserved  
Self-Offset Calibration  
Self-Gain Calibration  
Reserved  
Reserved  
System-Offset Calibration  
System-Gain Calibration  
Reserved  
SYNC1  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
1
1
1
1
1
1
1
1
Function:  
Part of the serial port re-initialization sequence.  
SYNC0  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
1
1
1
1
1
1
1
0
Function:  
End of the serial port re-initialization sequence.  
NULL  
D7(MSB)  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
0
0
0
0
0
0
Function:  
This command is used to clear a port flag and keep the converter in the continuous conversion mode.  
DS289F5  
21  
CS5531/32/33/34-AS  
2.2.4. Serial Port Interface  
SCLK, Serial Clock, is the serial bit-clock which  
controls the shifting of data to or from the ADC’s  
serial port. The CS pin must be held low (logic 0)  
before SCLK transitions can be recognized by the  
port logic. To accommodate optoisolators SCLK is  
designed with a Schmitt-trigger input to allow an  
optoisolator with slower rise and fall times to di-  
rectly drive the pin. Additionally, SDO is capable  
of sinking or sourcing up to 5 mA to directly drive  
an optoisolator LED. SDO will have less than a 400  
mV loss in the drive voltage when sinking or sourc-  
ing 5 mA.  
The CS5531/32/33/34’s serial interface consists of  
four control lines: CS, SDI, SDO, SCLK. Figure 7  
details the command and data word timing.  
CS, Chip Select, is the control line which enables  
access to the serial port. If the CS pin is tied low,  
the port can function as a three-wire interface.  
SDI, Serial Data In, is the data signal used to trans-  
fer data to the converters.  
SDO, Serial Data Out, is the data signal used to  
transfer output data from the converters. The SDO  
output will be held at high impedance any time CS  
is at logic 1.  
CS  
SCLK  
LSB  
MSB  
SDI  
Command Time  
8 SCLKs  
Data Time 32 SCLKs  
Write Cycle  
CS  
SCLK  
SDI  
Command Time  
8 SCLKs  
LSB  
MSB  
SDO  
Data Time 32 SCLKs  
Read Cycle  
CS  
SCLK  
SDI  
t *  
d
MCLK /OWR  
Clock Cycles  
Command Time  
8 SCLKs  
MSB  
LSB  
SDO  
8 SCLKs Clear SDO Flag  
Data Time 32 SCLKs  
Data Conversion Cycle  
* td is the time it takes the ADC to perform a conversion. See the Single  
Conversion and Continuous Conversion sections of the data sheet for more  
details about conversion timing.  
Figure 7. Command and Data Word Timing  
22  
DS289F5  
CS5531/32/33/34-AS  
2.2.5. Reading/Writing On-Chip Registers  
2.3.1. Power Consumption  
The CS5531/32/33/34’s offset, gain, configuration, The CS5531/32/33/34 accommodate three power  
and channel-setup registers are readable and writ- consumption modes: normal, standby, and sleep.  
able while the conversion data register is read only.  
The default mode, “normal mode”, is entered after  
power is applied. In this mode, the  
CS5531/32/33/34 devices typically consume  
35 mW. The other two modes are referred to as the  
power-save modes. They power down most of the  
analog portion of the chip and stop filter convolu-  
tions. The power-save modes are entered whenever  
the power-down (PDW) bit of the configuration  
register is set to logic 1. The particular power-save  
mode entered depends on state of the PSS (Power  
Save Select) bit. If PSS is logic 0, the converter en-  
ters the standby mode reducing the power con-  
sumption to 4 mW. The standby mode leaves the  
oscillator and the on-chip bias generator for the an-  
alog portion of the chip active. This allows the con-  
verter to quickly return to the normal mode once  
PDW is set back to a logic 1. If PSS and PDW are  
both set to logic 1, the sleep mode is entered reduc-  
ing the consumed power to around 500 µW. Since  
this sleep mode disables the oscillator, approxi-  
mately a 20 ms oscillator start-up delay period is  
required before returning to the normal mode. If an  
external clock is used, there will be no delay. Fur-  
ther note that when the chips are used in the  
Gain = 1 mode, the PGIA is powered down. With  
the PGIA powered down, the power consumed in  
the normal power mode is reduced by approximate-  
ly 1/2. Power consumption in the sleep and standby  
modes is not affected by the amplifier setting.  
As shown in Figure 7, to write to a particular regis-  
ter the user must transmit the appropriate write  
command and then follow that command by 32 bits  
of data. For example, to write 0x80000000 (hexa-  
decimal) to physical channel one’s gain register,  
the user would first transmit the command byte  
0x02 (hexadecimal) followed by the data  
0x80000000 (hexadecimal). Similarly, to read a  
particular register the user must transmit the appro-  
priate read command and then acquire the 32 bits of  
data. Once a register is written to or read from, the  
serial port returns to the command mode.  
In addition to accessing the internal registers one at  
a time, the gain and offset registers as well as the  
channel setup registers can be accessed as arrays  
(i.e. the entire register set can be accessed with one  
command). In the CS5531/32, there are two gain  
and offset registers, and in the CS5533/34, there are  
four gain and offset registers. There are four chan-  
nel setup registers in all parts. As an example, to  
write 0x80000000 (hexadecimal) to all four gain  
registers in the CS5533, the user would transmit the  
command 0x42 (hexadecimal) followed by four it-  
erations of 0x80000000 (hexadecimal), (i.e. 0x42  
followed  
by  
0x80000000,  
0x80000000,  
0x80000000, 0x80000000). The registers are writ-  
ten to or read from in sequential order (i.e, 1, fol-  
lowed by 2, 3, and 4). Once the registers are written  
to or read from, the serial port returns to the com-  
mand mode.  
2.3.2. System Reset Sequence  
The reset system (RS) bit permits the user to per-  
form a system reset. A system reset can be initiated  
at any time by writing a logic 1 to the RS bit in the  
configuration register. After the RS bit has been  
set, the internal logic of the chip will be initialized  
to a reset state. The reset valid (RV) bit is set indi-  
cating that the internal logic was properly reset.  
The RV bit is cleared after the configuration regis-  
2.3. Configuration Register  
To ease the architectural design and simplify the  
serial interface, the configuration register is 32  
long, however, only eleven of the 32 bits are used.  
The following sections detail the bits in the config-  
uration register.  
DS289F5  
23  
CS5531/32/33/34-AS  
ter is read. The on-chip registers are initialized to buffer which reduces the dynamic current demand  
the following default states:  
of the external reference.  
The reference’s input buffer is designed to accom-  
modate rail-to-rail (common-mode plus signal) in-  
put voltages. The differential voltage between the  
VREF+ and VREF- can be any voltage from 1.0 V  
up to the analog supply (depending on how VRS is  
configured), however, the VREF+ cannot go above  
VA+ and the VREF- pin can not go below VA-.  
Note that the power supplies to the chip should be  
established before the reference voltage.  
Configuration Register:  
Offset Registers:  
Gain Registers:  
00000000(H)  
00000000(H)  
01000000(H)  
Channel Setup Registers: 00000000(H)  
After reset, the RS bit should be written back to  
logic 0 to complete the reset cycle. The ADC will  
return to the command mode where it waits for a  
valid command. Also, the RS bit is the only bit in  
the configuration register that can be set when ini-  
tiating a reset (i.e. a second write command is need-  
ed to set other bits in the Configuration Register  
after the RS bit has been cleared).  
2.3.6. Output Latch Pins  
The A1-A0 pins of the ADCs mimic the D21-  
D20/D5-D4 bits of the channel-setup registers if  
the output latch select (OLS) bit is logic 0 (default).  
If the OLS bit is logic 1, A1-A0 mimic the output  
latch bit settings in the configuration register.  
These two options give the user a choice of allow-  
ing the latch outputs to change anytime a different  
CSR is selected for a conversion, or to allow the  
latch bits to remain latched to a fixed state (deter-  
mined by the configuration register bit) for all CSR  
selections. In either case, A1-A0 can be used to  
control external multiplexers and other logic func-  
tions outside the converter. The A1-A0 outputs can  
sink or source at least 1 mA, but it is recommended  
to limit drive currents to less than 20 µA to reduce  
self-heating of the chip. These outputs are powered  
2.3.3. Input Short  
The input short bit allows the user to internally  
ground all the inputs of the multiplexer. This is a  
useful function because it allows the user to easily  
test the grounded input performance of the ADC  
and eliminate the noise effects due to the external  
system components.  
2.3.4. Guard Signal  
The guard signal bit is a bit that modifies the func-  
tion of A0. When set, this bit outputs the common  
mode voltage of the instrumentation amplifier on  
A0. This feature is useful when the user wants to  
connect an external shield to the common mode po-  
tential of the instrumentation amplifier to protect  
against leakage. Figure 8 illustrates a typical con-  
nection diagram for the guard signal.  
CS5531/32/33/34  
A 0/G U A R D  
+5 V A  
+
A IN +  
out p  
2.3.5. Voltage Reference Select  
The voltage reference select (VRS) bit selects the  
size of the sampling capacitor used to sample the  
voltage reference. The bit should be set based upon  
the magnitude of the reference voltage to achieve  
optimal performance. Figures 9 and 10 model the  
effects on the reference’s input impedance and in-  
put current for each VRS setting. As the models  
show, the reference includes a coarse/fine charge  
V
+
IN  
center  
x1  
Com m on M ode  
=
2.5  
V
V
-
IN  
A IN -  
out m  
Figure 8. Guard Signal Shielding Scheme  
24  
DS289F5  
CS5531/32/33/34-AS  
φ
Fine  
1
φ
Fine  
1
φ
Coarse  
2
φ
Coarse  
2
VREF  
VREF  
C = 7 pF  
C = 14pF  
V
16 mV  
= fV  
V
8 mV  
os  
= fV C  
os  
os  
i
i
C
n
os  
n
MCLK  
16  
MCLK  
16  
f =  
f =  
VRS = 0; 2.5 V < VREF VA+  
VRS = 1; 1 V VREF 2.5 V  
Figure 9. Input Reference Model when VRS = 1  
Figure 10. Input Reference Model when VRS = 0  
2.3.8. Filter Rate Select  
from VA+ and VA-. Their output voltage will be  
limited to the VA+ voltage for a logic 1 and VA-  
for a logic 0.  
The Filter Rate Select bit (FRS) modifies the output  
word rates of the converter to allow either 50 Hz or  
60 Hz rejection when operating from  
a
2.3.7. Offset and Gain Select  
4.9152 MHz crystal. If FRS is cleared to logic 0,  
the word rates and corresponding filter characteris-  
tics can be selected (using the Channel Setup Reg-  
isters) from 7.5, 15, 30, 60, 120, 240, 480, 960,  
1920, or 3840 Sps when using a 4.9152 MHz clock.  
If FRS is set to logic 1, the word rates and corre-  
sponding filter characteristics scale by a factor of  
5/6, making the selectable word rates 6.25, 12.5,  
25, 50, 100, 200, 400, 800, 1600, and 3200 Sps  
when using a 4.9152 MHz clock. When using other  
clock frequencies, these selectable word rates will  
scale linearly with the clock frequency that is used.  
The Offset and Gain Select bit (OGS) is used to se-  
lect the source of the calibration registers to use  
when performing conversions and calibrations.  
When the OGS bit is set to ‘0’, the offset and gain  
registers corresponding to the desired physical  
channel (CS1-CS0 in the selected Setup) will be ac-  
cessed. When the OGS bit is set to ‘1’, the offset  
and gain registers pointed to by the OG1-OG0 bits  
in the selected Setup will be accessed. This feature  
allows multiple calibration values (e.g. for different  
gain settings) to be used on a single physical chan-  
nel without having to re-calibrate or manipulate the  
calibration registers.  
DS289F5  
25  
CS5531/32/33/34-AS  
2.3.9. Configuration Register Descriptions  
D31(MSB) D30  
D29  
RS  
D13  
NU  
D28  
RV  
D12  
NU  
D27  
IS  
D11  
NU  
D26  
GB  
D10  
NU  
D25  
VRS  
D9  
D24  
A1  
D8  
D23  
A0  
D7  
D22  
OLS  
D6  
D21  
NU  
D5  
D20  
OGS FRS  
D4  
NU  
D19  
D18  
NU  
D2  
D17  
NU  
D1  
D16  
NU  
D0  
PSS  
D15  
NU  
PDW  
D14  
NU  
D3  
NU  
NU  
NU  
NU  
NU  
NU  
NU  
NU  
NU  
PSS (Power Save Select)[31]  
0
1
Standby Mode (Oscillator active, allows quick power-up).  
Sleep Mode (Oscillator inactive).  
PDW (Power Down Mode)[30]  
0
1
Normal Mode  
Activate the power save select mode.  
RS (Reset System)[29]  
0
1
Normal Operation.  
Activate a Reset cycle. See System Reset Sequence in the datasheet text.  
RV (Reset Valid)[28]  
0
1
Normal Operation  
System was reset. This bit is read only. Bit is cleared to logic zero after the configuration register is read.  
IS (Input Short)[27]  
0
1
Normal Input  
All signal input pairs for each channel are disconnected from the pins and shorted internally.  
GB (Guard Signal Bit)[26]  
0
1
Normal Operation of A0 as an output latch.  
A0’s output is modified to output the common mode output voltage of the instrumentation amplifier (typically  
2.5 V). The output latch select bit is ignored when the guard buffer is activated.  
VRS (Voltage Reference Select)[25]  
0
1
2.5 V < VREF [(VA+) - (VA-)]  
1 V VREF 2.5V  
A1-A0 (Output Latch bits)[24:23]  
The latch bits (A0 and A1) will be set to the logic state of these bits upon command word execution if the output  
latch select bit (OLS) is set. Note that these logic outputs are powered from VA+ and VA-.  
00  
01  
10  
11  
A0 = 0, A1 = 0  
A0 = 0, A1 = 1  
A0 = 1, A1 = 0  
A0 = 1, A1 = 1  
Output Latch Select, OLS[22]  
0
1
When low, uses the Channel-Setup Register as the source of A1 and A0.  
When set, uses the Configuration Register as the source of A1 and A0.  
NU (Not Used)[21]  
0
Must always be logic 0. Reserved for future upgrades.  
Offset and Gain Select OGS[20]  
0
1
Calibration registers used are based on the CS1-CS0 bits of the referenced Setup.  
Calibration registers used are based on the OG1-OG0 bits of the referenced Setup.  
26  
DS289F5  
CS5531/32/33/34-AS  
Filter Rate Select, FRS[19]  
0
1
Use the default output word rates.  
Scale all output word rates and their corresponding filter characteristics by a factor of 5/6.  
NU (Not Used)[18:0]  
0
Must always be logic 0. Reserved for future upgrades.  
2.4. Setting up the CSRs for a Measurement  
The CS5531/32/33/34 have four channel-setup reg- represented in more than one Setup with different  
isters (CSRs). Each CSR contains two 16-bit Setups output rates, gain ranges, etc. (i.e. each Setup is in-  
which are programmed by the user to contain data dependently defined). Refer to section 2.4.1 for  
conversion information such as: 1) which physical more details about the Channel Setup Registers.  
channel will be converted, 2) at what gain will the  
Each 32-bit CSR is individually accessible and  
channel be converted, 3) at what word rate will the  
contains two 16-bit Setups. As an example, to con-  
channel be converted, 4) will the output conversion  
figure Setup 1 in the CS5531/32/33/34 with the  
be unipolar or bipolar, 5) what will be the state of the  
write individual channel-setup register command  
output latch during the conversion, 6) will the con-  
(0x05 hexadecimal), bits 31 to 16 of CSR 1 con-  
verter delay the start of a conversion to allow time  
tains the information for Setup 1 and bits 15 to 0  
for the output latch to settle before the conversion is  
contain the information for Setup 2. Note that while  
begun, and 7) will the open circuit detect current  
reading/writing CSRs, two Setups are accessed in  
source be activated for that Setup. In addition, when  
pairs as a single 32-bit CSR register. Even if one of  
the OGS bit in the Configuration Register is set, the  
the Setups isn’t used, it must be written to or read.  
Setup selects which set of offset and gain registers to  
Examples detailing the power of the CSRs are pro-  
use when performing conversions or calibrations.  
vided in section 2.6.3.  
Note that a particular physical input channel can be  
DS289F5  
27  
CS5531/32/33/34-AS  
2.4.1. Channel-Setup Register Descriptions  
CSR  
#1  
Setup 1  
Setup 2  
Bits <127:112>  
Bits <111:96>  
#4  
Setup 7  
Setup 8  
Bits <31:16>  
Bits <15:0>  
D31(MSB) D30  
D29  
G2  
D13  
G2  
D28  
G1  
D12  
G1  
D27  
G0  
D11  
G0  
D26  
WR3 WR2 WR1 WR0 U/B  
D10 D9 D8 D7 D6  
WR3 WR2 WR1 WR0 U/B  
D25  
D24  
D23  
D22  
D21  
OL1 OL0  
D5 D4  
OL1 OL0  
D20  
D19  
DT  
D3  
D18  
OCD OG1 OG0  
D2 D1 D0  
OCD OG1 OG0  
D17  
D16  
CS1  
D15  
CS1  
CS0  
D14  
CS0  
DT  
CS1-CS0 (Channel Select Bits) [31:30] [15:14]  
00  
01  
10  
11  
Select physical channel 1 (All devices)  
Select physical channel 2 (All devices)  
Select physical channel 3 (CS5533/34 only)  
Select physical channel 4 (CS5533/34 only)  
G2-G0 (Gain Bits) [29:27] [13:11]  
For VRS = 0, A = 2; For VRS = 1, A = 1; Bipolar input span is twice the unipolar input span.  
Gain = 1, (Input Span = [(VREF+)-(VREF-)]/1*A for unipolar).  
Gain = 2, (Input Span = [(VREF+)-(VREF-)]/2*A for unipolar).  
Gain = 4, (Input Span = [(VREF+)-(VREF-)]/4*A for unipolar).  
Gain = 8, (Input Span = [(VREF+)-(VREF-)]/8*A for unipolar).  
Gain = 16, (Input Span = [(VREF+)-(VREF-)]/16*A for unipolar).  
Gain = 32, (Input Span = [(VREF+)-(VREF-)]/32*A for unipolar).  
Gain = 64, (Input Span = [(VREF+)-(VREF-)]/64*A for unipolar).  
000  
001  
010  
011  
100  
101  
110  
WR3-WR0 (Word Rate) [26:23] [10:7]  
The listed Word Rates are for continuous conversion mode using a 4.9152 MHz clock. All word rates will  
scale linearly with the clock frequency used. The very first conversion using continuous conversion mode  
will last longer, as will conversions done with the single conversion mode. See the section on Performing  
Conversions and Tables 1 and 2 for more details.  
Bit  
WR (FRS = 0)  
120 Sps  
60 Sps  
WR (FRS = 1)  
100 Sps  
50 Sps  
0000  
0001  
0010  
0011  
0100  
1000  
1001  
1010  
1011  
1100  
30 Sps  
25 Sps  
15 Sps  
12.5 Sps  
6.25 Sps  
3200 Sps  
1600 Sps  
800 Sps  
400 Sps  
200 Sps  
7.5 Sps  
3840 Sps  
1920 Sps  
960 Sps  
480 Sps  
240 Sps  
All other combinations are not used.  
28  
DS289F5  
CS5531/32/33/34-AS  
U/B (Unipolar / Bipolar) [22] [6]  
0
1
Select Bipolar mode.  
Select Unipolar mode.  
OL1-OL0 (Output Latch Bits) [21:20] [5:4]  
The latch bits will be set to the logic state of these bits upon command word execution when the output  
latch select bit (OLS) in the configuration register is logic 0. Note that the logic outputs on the chip are  
powered from VA+ and VA-.  
00  
01  
10  
11  
A0 = 0, A1 = 0  
A0 = 0, A1 = 1  
A0 = 1, A1 = 0  
A0 = 1, A1 = 1  
DT (Delay Time Bit) [19] [3]  
When set, the converter will wait for a delay time before starting a conversion. This allows settling time for  
A0 and A1 outputs before a conversion begins. The delay time will be 1280 MCLK cycles when FRS = 0,  
and 1536 MCLK cycles when FRS = 1.  
0
1
Begin Conversions Immediately.  
Wait 1280 MCLK cycles (FRS = 0) or 1536 MCLK cycles (FRS = 1) before starting conversion.  
OCD (Open Circuit Detect Bit) [18] [2]  
When set, this bit activates a 300 nA current source on the input channel (AIN+) selected by the channel  
select bits. Note that the 300nA current source is rated at 25°C. At -55°C, the current source doubles to  
approximately 600 nA. This feature is particularly useful in thermocouple applications when the user wants  
to drive a suspected open thermocouple lead to a supply rail.  
0
1
Normal mode.  
Activate current source.  
OG1-OG0 (Offset / Gain Register Pointer Bits) [17:16] [1:0]  
These bits are only used when OGS in the Configuration Register is set to ‘1’. They allow the user to select  
the offset and gain register to use while performing a conversion or calibration. When the OGS bit in the  
Configuration Register is set to ‘0’, the offset and gain register for the referenced physical channel (CS1-  
CS0 bits of the Setup) will be used.  
00  
01  
10  
11  
Use offset and gain register from physical channel 1  
Use offset and gain register from physical channel 2  
Use offset and gain register from physical channel 3  
Use offset and gain register from physical channel 4  
DS289F5  
29  
CS5531/32/33/34-AS  
2.5. Calibration  
tion of the input span (bipolar span is 2 times the  
unipolar span, gain register = 1.000...000 decimal).  
The MSB in the offset register determines if the  
offset to be trimmed is positive or negative (0 pos-  
itive, 1 negative). Note that the magnitude of the  
offset that is trimmed from the input is mapped  
through the gain register. The converter can typi-  
cally trim ±100% of the input span. As shown in the  
Gain Register section, the gain register spans from  
Calibration is used to set the zero and gain slope of  
the ADC’s transfer function. The CS5531/32/33/34  
offer both self-calibration and system calibration.  
Note:  
After the ADCs are reset, they are functional  
and can perform measurements without  
being calibrated (remember that the VRS bit  
in the configuration register must be properly  
configured). In this case, the converter will  
utilize the initialized values of the on-chip  
registers (Gain = 1.0, Offset = 0.0) to  
calculate output words. Any initial offset and  
gain errors in the internal circuitry of the chip  
will remain.  
-24  
0 to (64 - 2 ). The decimal equivalent meaning of  
the gain register is  
29  
5
4
3
–24  
(– 24 + i)  
D = b  
2
+ b  
2
+ b  
2
+ + b  
2
) =  
b
2
D29  
D28  
D27  
D0  
Di  
2.5.1. Calibration Registers  
i = 0  
The CS5531/32/33/34 converters have an individu-  
al offset and gain register for each channel input.  
The gain and offset registers, which are used during  
both self and system calibration, are used to set the  
zero and gain slope of the converter’s transfer func-  
tion. As shown in Offset Register section, one LSB  
where the binary numbers have a value of either  
zero or one (b is the binary value of bit D29).  
While gain register settings of up to 64 - 2 are  
available, the gain register should never be set to  
values above 40.  
D29  
-24  
-24  
in the offset register is 1.835007966 x 2 propor-  
2.5.2. Gain Register  
MSB D30  
D29  
D28  
D27  
D26  
D25  
D24  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
25  
24  
23  
22  
21  
20  
2-1  
2-2  
2-3  
2-4  
2-5  
2-6  
2-7  
2-8  
NU  
NU  
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
LSB  
2-9  
2-10  
2-11  
2-12  
2-13  
2-14  
2-15  
2-16  
2-17  
2-18  
2-19  
2-20  
2-21  
222  
2-23  
2-24  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-24  
The gain register span is from 0 to (64-2 ). After Reset D24 is 1, all other bits are ‘0’.  
2.5.3. Offset Register  
MSB D30  
D29  
D28  
D27  
D26  
D25  
D24  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
2-2  
2-3  
2-4  
2-5  
2-6  
2-7  
2-8  
2-9  
2-10  
2-11  
2-12  
2-13  
2-14  
2-15  
2-16  
Sign  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
LSB  
2-17  
2-18  
2-19  
2-20  
2-21  
2-22  
2-23  
2-24  
NU  
NU  
NU  
NU  
NU  
NU  
NU  
NU  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-24  
One LSB represents 1.835007966 X 2 proportion of the input span (bipolar span is 2 times unipolar span).  
Offset and data word bits align by MSB. After reset, all bits are ‘0’.  
The offset register is stored as a 32-bit, two’s complement number, where the last 8 bits are all 0.  
30  
DS289F5  
CS5531/32/33/34-AS  
2.5.4. Performing Calibrations  
effects from the previous calibration as only one  
offset and gain register is available per physical  
channel. Only one calibration is performed with  
each command byte. To calibrate all the channels,  
additional calibration commands are necessary.  
To perform a calibration, the user must send a com-  
mand byte with its MSB = 1, its pointer bits  
(CSRP2-CSRP0) set to address the desired Setup to  
calibrate, and the appropriate calibration bits (CC2-  
CC0) set to choose the type of calibration to be per-  
formed. Note that calibration assumes that the  
CSRs have been previously initialized because the  
information concerning the physical channel, its  
filter rate, gain range, and polarity, comes from the  
channel-setup register addressed by the pointer bits  
in the command byte. Once the CSRs are initial-  
ized, a calibration can be performed with one com-  
mand byte.  
2.5.5. Self-calibration  
The CS5531/32/33/34 offer both self-offset and  
self-gain calibrations. For the self-calibration of  
offset, the converters internally tie the inputs of the  
1x amplifier together and routes them to the AIN-  
pin as shown in Figure 11. For accurate self calibra-  
tion of offset to occur, the AIN pins must be at the  
proper common-mode voltage as specified in the  
Analog Characteristics section. Self-offset calibra-  
tion uses the 1x gain amplifier, and is therefore not  
valid in the 2x-64x gain ranges. A self-offset calibra-  
tion of these gain ranges can be performed by setting  
the IS bit in the configuration register to a ‘1’, and  
performing a system offset calibration. The IS bit  
must be returned to ‘0’ afterwards for normal opera-  
tion of the device.  
The length of time it takes to do a calibration is  
slightly less than the amount of time it takes to do  
a single conversion (see Table 1 for single conver-  
sion timing). Offset calibration takes 608 clock cy-  
cles less than a single conversion when FRS = 0,  
and 729 clock cycles less when FRS = 1. Gain cal-  
ibration takes 128 clock cycles less than a single  
conversion when FRS = 0, and 153 clock cycles  
less when FRS = 1.  
For self calibration of gain, the differential inputs  
of the modulator are connected to VREF+ and  
VREF- as shown in Figure 12. Self calibration of  
gain will not work with (VREF+ - VREF-) > 2.5V.  
Self calibration of gain is performed in the  
GAIN = 1x mode without regard to the setup regis-  
ter’s gain setting. Gain errors in the PGIA gain  
steps 2x to 64x are not calibrated as this would re-  
quire an accurate low-voltage source other than the  
reference voltage. A system calibration of gain  
should be performed if accurate gains are to be  
achieved on the ranges other than 1x, or when  
(VREF+ VREF-) > 2.5V.  
Once a calibration cycle is complete, SDO falls and  
the results are automatically stored in either the  
gain or offset register for the physical channel be-  
ing calibrated when the OGS bit in the Configura-  
tion Register is set to ‘0’. If the OGS bit is set to ‘1’,  
the results will be stored in the register specified by  
the OG1-OG0 bits of the selected Setup. See the  
OGS bit description for more details (Section  
2.3.7). SDO will remain low until the next com-  
mand word is begun. If additional calibrations are  
performed while referencing the same calibration  
registers, the last calibration results will replace the  
DS289F5  
31  
CS5531/32/33/34-AS  
2.5.6. System Calibration  
channels that are used at these rates should also be  
calibrated in one of these word rates, and channels  
used in the lower word rates (120 Sps and lower)  
should be calibrated at one of these lower rates.  
Since higher word rates result in conversion words  
with more peak-to-peak noise, calibration should  
be performed at the lowest possible output word  
rate for maximum accuracy. For the 7.5 Sps to 120  
Sps word rate settings, calibrations can be per-  
formed at 7.5 Sps, and for 240 Sps and higher, cal-  
ibration can be performed at 240 Sps. To minimize  
digital noise near the device, the user should wait  
for each calibration step to be completed before  
reading or writing to the serial port. Reading the  
calibration registers and averaging multiple cali-  
For the system calibration functions, the user must  
supply the converter’s calibration signals which rep-  
resent ground and full scale. When a system offset  
calibration is performed, a ground-referenced signal  
must be applied to the converters. Figure 13 illus-  
trates system offset calibration.  
As shown in Figure 14, the user must input a signal  
representing the positive full-scale point to perform  
a system gain calibration. In either case, the cali-  
bration signals must be within the specified calibra-  
tion limits for each specific calibration step (refer  
to the System Calibration Specifications).  
2.5.7. Calibration Tips  
Calibration steps are performed at the output word brations together can produce a more accurate cal-  
rate selected by the WR2-WR0 bits of the channel ibration result. Note that accessing the ADC’s  
setup registers. Due to limited register lengths in serial port before a calibration has finished may re-  
the faster word-rate filters (240 Sps and higher), sult in the loss of synchronization between the mi-  
OPEN  
AIN+  
AIN-  
+
-
+
-
+
AIN+  
AIN-  
+
XGAIN  
1X GAIN  
OPEN  
_
_
VREF+  
VREF-  
+
CLOSED  
CLOSED  
Reference  
-
Figure 12. Self-calibration of Gain  
Figure 11. Self-calibration of Offset  
External  
Connections  
External  
Connections  
+
-
+
-
+
+
-
AIN+  
AIN+  
+
+
-
0V  
XGAIN  
XGAIN  
Full Scale  
CM  
-
-
AIN-  
AIN-  
+
-
+
-
CM  
Figure 14. System Calibration of Gain  
Figure 13. System Calibration of Offset  
32  
DS289F5  
 
CS5531/32/33/34-AS  
crocontroller and the ADC, and may prematurely gain register can hold numbers all the way up to  
-24  
halt the calibration cycle.  
64 2 , gain register settings above a decimal  
value of 40 should not be used. With the convert-  
er’s intrinsic gain error, this minimum full-scale in-  
put signal may be higher or lower. In defining the  
minimum Full Scale Calibration Range (FSCR)  
under Analog Characteristics, margin is retained to  
accommodate the intrinsic gain error. Inversely, the  
input full-scale signal can be increased to a point in  
which the modulator reaches its 1’s density limit of  
86 percent, which under nominal conditions occurs  
when the full-scale input signal is 1.1 times the  
nominal full-scale value. With the chip’s intrinsic  
gain error, this maximum full-scale input signal  
maybe higher or lower. In defining the maximum  
FSCR, margin is again incorporated to accommo-  
date the intrinsic gain error.  
For maximum accuracy, calibrations should be per-  
formed for both offset and gain (selected by chang-  
ing the G2-G0 bits of the channel-setup registers).  
Note that only one gain range can be calibrated per  
physical channel when the OGS bit in the Configu-  
ration Register is set to ‘0’. Multiple gain ranges  
can be calibrated for a single channel by manipulat-  
ing the OGS bit and the OG1-OG0 bits of the se-  
lected Setup (see Section 2.3.7 for more details). If  
factory calibration of the user’s system is per-  
formed using the system calibration capabilities of  
the CS5531/32/33/34, the offset and gain register  
contents can be read by the system microcontroller  
and recorded in non-volatile memory. These same  
calibration words can then be uploaded into the off-  
set and gain registers of the converter when power  
is first applied to the system, or when the gain range  
is changed.  
2.6. Performing Conversions  
The CS5531/32/33/34 offers two distinctly differ-  
ent conversion modes. The three sections that fol-  
low detail the differences and provide examples  
illustrating how to use the conversion modes with  
the channel-setup registers.  
When the device is used without calibration, the  
uncalibrated gain accuracy is about ±1% and the  
gain tracking from range to range (2x to 64x) is ap-  
proximately ±0.3 percent.  
2.6.1. Single Conversion Mode  
Note that the gain from the offset register to the  
output is 1.83007966 decimal, not 1. If a user wants  
to adjust the calibration coefficients externally,  
they will need to divide the information to be writ-  
ten to the offset register by the scale factor of  
1.83007966. (This discussion assumes that the gain  
register is 1.000...000 decimal. The offset register  
is also multiplied by the gain register before being  
applied to the output conversion words).  
Based on the information provided in the channel-  
setup registers (CSRs), after the user transmits the  
conversion command, a single, fully settled con-  
version is performed. The command byte includes  
a pointer address to the Setup register to be used  
during the conversion. Once transmitted, the serial  
port enters data mode where it waits until the con-  
version is complete. When the conversion data is  
available, SDO falls to logic 0. Forty SCLKs are  
then needed to read the conversion data word. The  
first 8 SCLKs are used to clear the SDO flag. Dur-  
ing the first 8 SCLKs, SDI must be logic 0. The last  
32 SCLKs are needed to read the conversion result.  
Note that the user is forced to read the conversion  
in single conversion mode as SDO will remain low  
(i.e. the serial port is in data mode) until SCLK  
transitions 40 times. After reading the data, the se-  
2.5.8. Limitations in Calibration Range  
System calibration can be limited by signal head-  
room in the analog signal path inside the chip as  
discussed under the Analog Input section of this  
data sheet. For gain calibration, the full-scale input  
signal can be reduced to 3% of the nominal full-  
scale value. At this point, the gain register is ap-  
proximately equal to 33.33 (decimal). While the  
DS289F5  
33  
CS5531/32/33/34-AS  
rial port returns to the command mode, where it  
done, SDO falls to logic 0. Forty SCLKs are then  
waits for a new command to be issued. The single needed to read the conversion. The first 8 SCLKs  
conversion mode will take longer than conversions  
performed in the continuous conversion mode. The  
number of clock cycles a single conversion takes  
are used to clear the SDO flag. The last 32 SCLKs  
are needed to read the conversion result. If  
‘00000000’ is provided to SDI during the first 8  
for each Output Word Rate (OWR) setting is listed SCLKs when the SDO flag is cleared, the converter  
in Table 1. The ± 8 (FRS = 0) or ± 10 (FRS = 1) remains in this conversion mode and continues to  
clock ambiguity is due to internal synchronization convert the selected channel using the same CSR  
between the SCLK input and the oscillator.  
Setup. In continuous conversion mode, not every  
conversion word needs to be read. The user needs  
only to read the conversion words required for the  
application as SDO rises and falls to indicate the  
availability of new conversion data. Note that if a  
conversion is not read before the next conversion  
data becomes available, it will be lost and replaced  
by the new conversion data. To exit this conversion  
mode, the user must provide ‘11111111’ to the SDI  
pin during the first 8 SCLKs after SDO falls. If the  
user decides to exit, 32 SCLKs are required to  
clock out the last conversion before the converter  
returns to command mode. The number of clock  
cycles a continuous conversion takes for each Out-  
put Word Setting is listed in Table 2. The first con-  
version from the part in continuous conversion  
mode will be longer than the following conversions  
due to start-up overhead. The ± 8 (FRS = 0) or ± 10  
(FRS = 1) clock ambiguity is due to internal syn-  
chronization between the SCLK input and the os-  
cillator.  
Note:  
In the single conversion mode, more than one  
conversion is actually performed, but only the  
final, fully settled result is output to the  
conversion data register.  
Table 1. Conversion Timing Single Mode  
Clock Cycles  
(WR3-WR0)  
FRS = 0  
171448 ± 8  
335288 ± 8  
662968 ± 8  
1318328 ± 8  
2629048 ± 8  
7592 ± 8  
FRS = 1  
205738 ± 10  
402346 ± 10  
795562 ± 10  
1581994 ± 10  
3154858 ± 10  
9110 ± 10  
0000  
0001  
0010  
0011  
0100  
1000  
1001  
1010  
1011  
1100  
17848 ± 8  
28088 ± 8  
48568 ± 8  
89528 ± 8  
21418 ± 10  
33706 ± 10  
58282 ± 10  
107434 ± 10  
2.6.2. Continuous Conversion Mode  
Based on the information provided in the channel-  
setup registers (CSRs), continuous conversions are  
performed using the Setup register contents pointed  
to by the conversion command. The command byte  
includes a pointer address to the Setup register to  
be used during the conversion. Once transmitted,  
the serial port enters data mode where it waits until  
a conversion is complete. After the conversion is  
Note:  
When changing channels, or after performing  
calibrations and/or single conversions, the  
user must ignore the first three (for OWRs  
less than 3200 Sps, MCLK = 4.9152 MHz) or  
first five (for OWR 3200 Sps) conversions in  
continuous conversion mode, as residual  
filter coefficients must be flushed from the  
filter before accurate conversions are  
performed.  
34  
DS289F5  
CS5531/32/33/34-AS  
The examples that follow detail situations that a  
user might encounter when acquiring a conversion  
or calibrating the converter. These examples as-  
sume that the CSRs are programmed with the fol-  
lowing physical channel order: 4, 1, 1, 2, 4, 3, 4, 4.  
Table 2. Conversion Timing Continuous Mode  
FRS (WR3-WR0)  
Clock Cycles  
Clock Cycles  
(First Conversion) (All Other  
Conversions)  
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0000  
0001  
0010  
0011  
0100  
1000  
1001  
1010  
1011  
1100  
0000  
0001  
0010  
0011  
0100  
1000  
1001  
1010  
1011  
1100  
89528 ± 8  
171448 ± 8  
335288 ± 8  
662968 ± 8  
1318328 ± 8  
2472 ± 8  
40960  
81920  
163840  
327680  
655360  
1280  
A physical channel is defined as the actual input  
channel (AIN1 to AIN4) to which an external sig-  
nal is connected.  
Example 1: Single conversion using Setup 1. The  
command issued is ‘10000000’. This instructs the  
converter to perform a single conversion referenc-  
ing Setup 1 (CSRP2 - CSRP0 = ‘000’) In this ex-  
ample, Setup 1 points to physical channel 4. After  
the command is received and decoded, the ADC  
performs a conversion on physical channel 4 and  
SDO falls to indicate that the conversion is com-  
plete. To read the conversion, 40 SCLKs are then  
required. Once the conversion data has been read,  
the serial port returns to the command mode.  
12728 ± 8  
2560  
17848 ± 8  
5120  
28088 ± 8  
10240  
20480  
49152  
98304  
196608  
393216  
786432  
1536  
48568 ± 8  
107434 ± 10  
205738 ± 10  
402346 ± 10  
795562 ± 10  
1581994 ± 10  
2966 ± 10  
15274 ± 10  
21418 ± 10  
33706 ± 10  
58282 ± 10  
3072  
Example 2: Continuous conversions using Setup 3.  
The command issued is ‘11010000’. This instructs  
the converter to perform continuous conversions  
referencing Setup 3 (CSRP2 - CSRP0 = ‘010’). In  
this example, Setup 3 points to physical channel 1.  
After the command is received and decoded, the  
ADC performs a conversion on physical channel 1  
and SDO falls to indicate that the conversion is  
complete. The user now has three options. The user  
can acquire the conversion and remain in this  
mode, acquire the conversion and exit this mode, or  
ignore the conversion and wait for a new conver-  
sion at the next update interval, as detailed in the  
continuous conversion section.  
6144  
12288  
24576  
2.6.3. Examples of Using CSRs to Perform  
Conversions and Calibrations  
Any time a calibration or conversion command is  
issued (C, MC, and CC2-CC0 bits must be properly  
set), the CSRP2-CSRP0 bits in the command byte  
are used as pointers to address one of the Setups in  
the channel-setup registers (CSRs). Table 3 details  
the address decoding of the pointer the bits.  
Table 3. Command Byte Pointer  
(CSRP2-CSRP0) CSR Location  
Setup  
000  
1
CSR #1  
CSR #1  
CSR #2  
CSR #2  
CSR #3  
CSR #3  
CSR#4  
CSR #4  
Example 3: Calibration using Setup 4. This exam-  
ple assumes that the OGS bit in the Configuration  
Register is set to ‘0’. The command issued is  
‘10011001’. This instructs the converter to perform  
a self offset calibration referencing Setup 4  
(CSRP2 - CSRP0 = ‘011’). In this example, Setup  
4 points to physical channel 2. After the command  
is received and decoded, the ADC performs a self  
001  
2
3
4
5
6
7
8
010  
011  
100  
101  
110  
111  
DS289F5  
35  
CS5531/32/33/34-AS  
offset calibration on physical channel 2 and SDO An example of a synchronous system using two  
falls to indicate that the calibration is complete. To CS5532 parts is shown in Figure 15.  
perform additional calibrations, more commands  
must be issued.  
CS5532  
SDO  
SDI  
Note:  
The CSRs need not be written. If they are not  
initialized, all the Setups point to their default  
settings irrespective of the conversion or  
calibration mode (i.e conversions can be  
performed, but only physical channel 1 will be  
converted). Further note that filter  
convolutions are reset (i.e. flushed) if  
consecutive conversions are performed on  
two different physical channels. If  
consecutive conversions are performed on  
the same physical channel, the filter is not  
reset. This allows the ADCs to more quickly  
settle full-scale step inputs.  
SCLK  
CS  
OSC2  
µC  
CS5532  
SDO  
SDI  
SCLK  
CS  
OSC2  
CLOCK  
SOURCE  
2.7. Using Multiple ADCs Synchronously  
Figure 15. Synchronizing Multiple ADCs  
Some applications require synchronous data out-  
puts from multiple ADCs converting different ana-  
log channels. Multiple CS5531/32/33/34 parts can  
be synchronized in a single system by using the fol-  
lowing guidelines:  
2.8. Conversion Output Coding  
The CS5531/33 output 16-bit data conversion  
words and the CS5532/34 output 24-bit data con-  
version words. To read a conversion word the user  
must read the conversion data register. The conver-  
sion data register is 32 bits long and outputs the  
conversions MSB first. The last byte of the conver-  
sion data register contains data monitoring flags.  
The channel indicator (CI) bits keep track of which  
physical channel was converted and the overrange  
flag (OF) monitors to determine if a valid conver-  
sion was performed. Refer to the Conversion Data  
Output Descriptions section for more details.  
1) All of the ADCs in the system must be operated  
from the same oscillator source.  
2) All of the ADCs in the system must share com-  
mon SCLK and SDI lines.  
3) A software reset must be performed at the same  
time for all of the ADCs after system power-up (by  
selecting all of the ADCs using their respective CS  
pins, and writing the reset sequence to all parts, us-  
ing SDI and SCLK).  
4) A start conversion command must be sent to all  
of the ADCs in the system at the same time. The ±8  
clock cycles of ambiguity for the first conversion  
(or for a single conversion) will be the same for all  
ADCs, provided that they were all reset at the same  
time.  
The CS5531/32/33/34 output data conversions in  
binary format when operating in unipolar mode and  
in two's complement format when operating in bi-  
polar mode. Tables 4 and 5 show the code mapping  
for both unipolar and bipolar mode. VFS in the ta-  
bles refers to the positive full-scale voltage range of  
the converter in the specified gain range, and -VFS  
refers to the negative full-scale voltage range of the  
converter. The total differential input range (be-  
tween AIN+ and AIN-) is from 0 to VFS in unipo-  
lar mode, and from -VFS to VFS in bipolar mode.  
5) Conversions can be obtained by monitoring  
SDO on only one ADC, (bring CS high for all but  
one part) and reading the data out of each part indi-  
vidually, before the next conversion data words are  
ready.  
36  
DS289F5  
CS5531/32/33/34-AS  
Table 5. Output Coding for 24-bit CS5532 and CS5534  
Table 4. Output Coding for 16-bit CS5531 and CS5533  
Unipolar Input Offset  
Voltage Binary  
Bipolar Input  
Voltage  
Two's  
Complement  
Unipolar Input Offset  
Voltage Binary  
Bipolar Input  
Voltage  
Two's  
Complement  
>(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB)  
VFS-1.5 LSB FFFFFF  
7FFFFF  
>(VFS-1.5 LSB) FFFF >(VFS-1.5 LSB)  
7FFF  
7FFFFF  
------  
7FFFFE  
VFS-1.5 LSB  
FFFF  
------  
7FFF  
------  
7FFE  
------  
VFS-1.5 LSB  
VFS-1.5 LSB  
-0.5 LSB  
FFFFFE  
FFFE  
VFS/2-0.5 LSB 800000  
000000  
------  
FFFFFF  
VFS/2-0.5 LSB 8000  
0000  
------  
FFFF  
------  
-0.5 LSB  
------  
7FFFFF  
7FFF  
+0.5 LSB  
000001  
------  
000000  
800001  
------  
800000  
+0.5 LSB  
0001  
------  
0000  
8001  
------  
8000  
-VFS+0.5 LSB  
-VFS+0.5 LSB  
<(+0.5 LSB)  
000000 <(-VFS+0.5 LSB)  
800000  
<(+0.5 LSB)  
0000 <(-VFS+0.5 LSB)  
8000  
2.8.1. Conversion Data Output Descriptions  
CS5531/33 (16-BIT CONVERSIONS)  
D31(MSB) D30  
D29  
13  
D13  
0
D28  
12  
D12  
0
D27  
11  
D11  
0
D26  
10  
D10  
0
D25  
9
D9  
0
D24  
8
D8  
0
D23  
7
D7  
0
D22  
6
D6  
0
D21  
5
D5  
0
D20  
4
D4  
0
D19  
3
D3  
0
D18  
2
D2  
OF  
D17  
1
D1  
CI1  
D16  
LSB  
D0  
MSB  
D15  
0
14  
D14  
0
CI0  
CS5532/34 (24-BIT CONVERSIONS)  
D31(MSB) D30  
D29  
21  
D13  
5
D28  
20  
D12  
4
D27  
19  
D11  
3
D26  
18  
D10  
2
D25  
17  
D9  
1
D24  
16  
D8  
D23  
15  
D7  
0
D22  
14  
D6  
0
D21  
13  
D5  
0
D20  
12  
D4  
0
D19  
11  
D3  
0
D18  
10  
D2  
OF  
D17  
9
D1  
CI1  
D16  
8
D0  
CI0  
MSB  
D15  
7
22  
D14  
6
LSB  
Conversion Data Bits [31:16 for CS5531/33; 31:8 for CS5532/34]  
These bits depict the latest output conversion.  
NU (Not Used) [15:3 for CS5531/33; 7:3 for CS5532/34]  
These bits are masked logic zero.  
OF (Over-range Flag Bit) [2]  
0
1
Bit is clear when over-range condition has not occurred.  
Bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar  
mode) or when the input is more negative than the negative full scale (bipolar mode).  
CI (Channel Indicator Bits) [1:0]  
These bits indicate which physical input channel was converted.  
Physical Channel 1  
00  
01  
10  
11  
Physical Channel 2  
Physical Channel 3  
Physical Channel 4  
DS289F5  
37  
CS5531/32/33/34-AS  
2.9. Digital Filter  
(MCLK = 4.9152 MHz) rate. The Z-transforms of  
the two filters are shown in Figure 19. For the Sinc  
filter, “D” is the programmable decimation ratio,  
which is equal to 3840/OWR when FRS = 0 and  
3200/OWR when FRS = 1.  
3
The CS5531/32/33/34 have linear phase digital fil-  
ters which are programmed to achieve a range of  
output word rates (OWRs) as stated in the Channel-  
Setup Register Descriptions section. The ADCs use  
5
a Sinc digital filter to output word rates at 3200  
The converter’s digital filters scale with MCLK.  
For example, with an output word rate of 120 Sps,  
the filter’s corner frequency is at 31 Hz. If MCLK  
is increased to 5.0 MHz, the OWR increases by  
1.0175% and the filter’s corner frequency moves to  
31.54 Hz. Note that the converter is not specified to  
run at MCLK clock frequencies greater than  
5 MHz.  
Sps and 3840 Sps (MCLK = 4.9152 MHz). Other  
output word rates are achieved by using the Sinc  
filter followed by a Sinc filter with a programma-  
ble decimation rate. Figure 16 shows the magnitude  
response of the 60 Sps filter, while Figures 17 and  
18 show the magnitude and phase response of the  
filter at 120 Sps. The Sinc is active for all output  
word rates except for the 3200 Sps and 3840 Sps  
5
3
3
180  
90  
0
-40  
-80  
0
-90  
-180  
-120  
0
60  
Frequency (Hz)  
90  
120  
30  
0
60  
120  
180  
240  
300  
Frequency (Hz)  
Figure 18. 120 Sps Filter Phase Plot to 120 Hz  
Figure 16. Digital Filter Response (WR = 60 Sps)  
0
Flatness  
Frequency  
dB  
2
-0.01  
-0.05  
-0.11  
-0.19  
-0.30  
-0.43  
-0.59  
-0.77  
-1.09  
-3.13  
-40  
-80  
4
6
8
5
3
2
3
(1 – z–80  
)
)
(1 – z–16  
)
(1 – z–4  
)
)
(1 – z–2  
)
10  
12  
14  
16  
19  
32  
Sinc5  
=
=
×
×
×
------------------------- ------------------------- ----------------------- -----------------------  
5
3
2
3
(1 – z–16  
(1 – z–4  
)
(1 – z–2  
(1 – z–1  
)
-120  
3
(1 – zD  
(1 – z–1  
)
Sinc3  
------------------------  
3
)
0
40  
80  
120  
3
Note:  
See the text regarding the Sinc filter’s  
decimation ratio “D”.  
Frequency (Hz)  
Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz  
Figure 19. Z-Transforms of Digital Filters  
38  
DS289F5  
CS5531/32/33/34-AS  
2.10. Clock Generator  
2.11. Power Supply Arrangements  
The CS5531/32/33/34 include an on-chip inverting The CS5531/32/33/34 are designed to operate from  
amplifier which can be connected with an external single or dual analog supplies and a single digital  
crystal to provide the master clock for the chip. Fig-  
supply. The following power supply connections  
ure 20 illustrates the on-chip oscillator. It includes are possible:  
loading capacitors and a feedback resistor to form  
VA+ = +5V; VA- = 0V; VD+ = +3V to +5V  
a Pierce oscillator configuration. The chips are de-  
signed to operate using a 4.9152 MHz crystal;  
VA+ = +2.5V; VA- = -2.5V; VD+ = +3V to +5V  
however, other crystals with frequencies between VA+ = +3V; VA- = -3V; VD+ = +3V  
1 MHz to 5 MHz can be used. One lead of the crys-  
A VA+ supply of +2.5 V, +3.0 V, or +5.0 V should  
tal should be connected to OSC1 and the other to  
OSC2. Lead lengths should be minimized to reduce  
stray capacitance. Note that while using the on-chip  
oscillator, neither OSC1 or OSC2 is capable of di-  
rectly driving any off-chip logic. When the on-chip  
oscillator is used, the voltage on OSC2 is typically  
0.5 V peak-to-peak. This signal is not compatible  
with external logic unless additional external cir-  
cuitry is added. The OSC2 output should be used if  
the on-chip oscillator output is used to drive other  
circuitry.  
be maintained at ±5% tolerance. A VA- supply of  
-2.5 V or -3.0 V should be maintained at ±5% tol-  
erance. VD+ can extend from +2.7 V to +5.5 V  
with the additional restriction that:  
[(VD+) - (VA-)] < 7.5 V.  
Figure 21 illustrates the CS5532 connected with a  
single +5.0 V supply to measure differential inputs  
relative to a common mode of 2.5 V. Figure 22 il-  
lustrates the CS5532 connected with ±2.5 V bipo-  
lar analog supplies and a +3 V to +5 V digital  
supply to measure ground referenced bipolar sig-  
nals. Figures 23 and 24 illustrate the CS5532 con-  
nected with ±3 V analog supplies and a +3 V  
digital supply to measure ground-referenced bipo-  
lar signals.  
The designer can use an external CMOS-compati-  
ble oscillator to drive OSC2 with a 1 MHz to  
5 MHz clock for the ADC. The external clock into  
OSC2 must overdrive the 60 µA output of the on-  
chip amplifier. This will not harm the on-chip cir-  
cuitry. In this scheme, OSC1 should be left uncon-  
nected.  
Figure 25 illustrates alternate bridge configurations  
which can be measured with the converter. Voltage  
V1 can be measured with the PGIA gain set to 1x  
as the input amplifier on this gain setting can go  
rail-to-rail. Voltage V2 should be measured with  
the PGIA gain set at 2x or higher as the instrumen-  
1 MΩ  
~
~60 µA  
VTH  
-
MCLK  
+
NOTE: 20 pF capacitors are on  
chip and should not be added  
externally.  
20 pF  
20 pF  
OSC1  
OSC2  
Figure 20. On-chip Oscillator Model  
DS289F5  
39  
 
CS5531/32/33/34-AS  
tation amplifier used on these gain ranges achieves  
lower noise.  
10 Ω  
+5 V  
Analog  
0.1 µF  
Supply  
0.1 µF  
5
15  
VD+  
VA+  
Optional  
Clock  
Source  
9
OSC2  
18  
VREF+  
17  
3
VREF-  
C1  
4.9152 MHz  
10  
OSC1  
22 nF  
-
+
CS5532  
4
C2  
14  
13  
CS  
SDI  
1
2
20  
AIN1+  
AIN1-  
AIN2+  
AIN2-  
A0  
Serial  
Data  
Interface  
12  
11  
SDO  
SCLK  
19  
7
8
A1  
VA -  
DGND  
16  
6
Figure 21. CS5532 Configured with a Single +5 V Supply  
40  
DS289F5  
CS5531/32/33/34-AS  
+2.5 V  
Analog  
Supply  
+3 V ~ +5 V  
Digital  
0.1 µF  
18  
0.1 µF  
Supply  
5
15  
VD+  
VA+  
Optional  
Clock  
Source  
9
OSC2  
VREF+  
17  
3
VREF-  
C1  
4.9152 MHz  
10  
OSC1  
22 nF  
-
+
CS5532  
4
C2  
14  
13  
CS  
SDI  
1
2
20  
AIN1+  
AIN1-  
AIN2+  
AIN2-  
A0  
Serial  
Data  
Interface  
12  
11  
SDO  
SCLK  
19  
7
8
A1  
VA -  
DGND  
16  
6
-2.5 V  
Analog  
Supply  
Figure 22. CS5532 Configured with ±2.5 V Analog Supplies  
10 Ω  
+3 V  
Analog  
Supply  
0.1 µF  
0.1 µF  
5
15  
VD+  
VA+  
Optional  
Clock  
9
18  
OSC2  
VREF+  
Source  
4.9152 MHz  
17  
3
VREF-  
C1  
10  
OSC1  
22 nF  
-
+
CS5532  
4
C2  
14  
13  
CS  
SDI  
1
2
20  
AIN1+  
AIN1-  
AIN2+  
AIN2-  
A0  
Serial  
Data  
Interface  
12  
11  
SDO  
SCLK  
19  
7
8
A1  
VA -  
DGND  
16  
6
-3 V  
Analog  
Supply  
Figure 23. CS5532 Configured with ±3 V Analog Supplies  
DS289F5  
41  
CS5531/32/33/34-AS  
10  
+3 V  
Analog  
Supply  
0.1 µF  
0.1 µF  
5
15  
VD+  
VA+  
1
Optional  
Clock  
9
AIN1+  
OSC2  
Source  
4.9152 MHz  
2
3
AIN1-  
C1  
10  
OSC1  
CS5532  
22 nF  
4
C2  
14  
13  
18  
CS  
SDI  
2.5V  
VREF+  
Serial  
Data  
Interface  
17  
20  
VREF-  
AIN2+  
AIN2-  
A0  
A1  
VA -  
12  
11  
SDO  
SCLK  
Cold  
Junction  
19  
7
8
DGND  
16  
6
-3 V  
Analog  
Supply  
Figure 24. CS5532 Configured for Thermocouple Measurement  
V+  
V+  
V 1  
V 2  
V 1  
V 2  
(a)  
(b)  
Figure 25. Bridge with Series Resistors  
42  
DS289F5  
CS5531/32/33/34-AS  
2.12. Getting Started  
magnitude of the reference voltage between the  
VREF+ and the VREF- pins.  
This A/D converter has several features. From a  
software programmer’s prospective, what should  
be done first? To begin, a 4.9152 MHz or  
4.096 MHz crystal takes approximately 20 ms to  
start. To accommodate for this, it is recommended  
that a software delay of approximately 20 ms start  
the processor’s ADC initialization code. Next,  
since the CS5531/32/33/34 do not provide a power-  
on-reset function, the user must first initialize the  
ADC to a known state. This is accomplished by re-  
setting the ADC’s serial port with the Serial Port  
Initialization sequence. This sequence resets the se-  
rial port to the command mode and is accomplished  
by transmitting 15 SYNC1 command bytes (0xFF  
hexadecimal), followed by one SYNC0 command  
(0xFE hexadecimal). Once the serial port of the  
ADC is in the command mode, the user must reset  
all the internal logic by performing a system reset  
sequence (see 2.3.2 System Reset Sequence). The  
next action is to initialize the voltage reference  
mode. The voltage reference select (VRS) bit in the  
configuration register must be set based upon the  
After this, the channel-setup registers (CSRs) should  
be initialized, as these registers determine how cali-  
brations and conversions will be performed. Once  
the CSRs are initialized, the user has three options in  
calibrating the ADC: 1) don’t calibrate and use the  
default settings; 2) perform self or system calibra-  
tions; or 3) upload previously saved calibration re-  
sults to the offset and gain registers. At this point,  
the ADC is ready to perform conversions.  
2.13. PCB Layout  
For optimal performance, the CS5531/32/33/34  
should be placed entirely over an analog ground  
plane. All grounded pins on the ADC, including the  
DGND pin, should be connected to the analog  
ground plane that runs beneath the chip. In a split-  
plane system, place the analog-digital plane split  
immediately adjacent to the digital portion of the  
chip.  
DS289F5  
43  
CS5531/32/33/34-AS  
3. PIN DESCRIPTIONS  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIFFERENTIAL ANALOG INPUT  
AIN1+  
AIN1-  
C1  
AIN2+  
AIN2-  
VREF+  
VREF-  
DGND  
VD+  
DIFFERENTIAL ANALOG INPUT  
DIFFERENTIAL ANALOG INPUT  
VOLTAGE REFERENCE INPUT  
VOLTAGE REFERENCE INPUT  
DIGITAL GROUND  
DIFFERENTIAL ANALOG INPUT  
AMPLIFIER CAPACITOR CONNECT  
AMPLIFIER CAPACITOR CONNECT  
POSITIVE ANALOG POWER  
CS5531/2  
C2  
VA+  
VA-  
POSITIVE DIGITAL POWER  
NEGATIVE ANALOG POWER  
LOGIC OUTPUT (ANALOG)/GUARD  
A0  
CS  
CHIP SELECT  
LOGIC OUTPUT (ANALOG)  
MASTER CLOCK  
A1  
SDI  
SERIAL DATA INPUT  
SERIAL DATA OUT  
OSC2  
SDO  
SCLK  
MASTER CLOCK  
OSC1  
SERIAL CLOCK INPUT  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
AIN2+  
AIN1+  
AIN1-  
DIFFERENTIAL ANALOG INPUT  
DIFFERENTIAL ANALOG INPUT  
DIFFERENTIAL ANALOG INPUT