CS74IC贸易商引脚图技术参数全新原装-中国IC网-芯三七

CS7410

CD/MP3/WMA Audio Controller

Features

Description

l Super on-chip Integration for low cost and low count bill of

The CS7410 is a true system-on-a-chip for the CD-

based digital audio market. With a powerful RISC pro-

cessor, one DSP, integrated audio DS modulator, large

internal SRAM and program ROM, and glueless inter-

face to popular CD chip sets, the CS7410 is a complete

single chip low-power programmable audio decoder.

This powerful architecture is easily capable of MP3,

WMA, and other future audio formats. The CS7410’s

flexible architecture and low power consumption make it

an ideal low-cost solution for a wide range of player ap-

plications. For portable audio systems, the memory

interface can be used to add DRAM or SRAM for Elec-

tronic Shock Protection (ESP). A flexible set of interfaces

are available for end-user I/O such as a keypad and LCD

control for use in mass market CD players, boom boxes,

and shelf-top systems.

materials

l 32-Bit RISC Processor performs audio decode and system

management functions

l 16-bit DSP for audio special effects

l 80 Kbytes internal SRAM, and 256 Kbytes internal ROM

l Interfaces to external SDRAM or EDO DRAM (for shock

protection), and to external ROM/FLASH (for custom

program storage)

l CD serial interface with advanced pattern matching and

software error handling

l Integrated DAC functionality

l Simultaneous 4 channels PCM audio output and IEC-958

output.

l Large number of GPIO pins for servo control, key scan, LCD

control, etc.

l Three serial control/status ports

l Sophisticated clock management and low power

consumption

l Supports ISO9660 and multi-session write methods

l Low power 0.18 micron technology

l 100-pin MQFP package

l 100-pin LQFP package

ORDERING INFORMATION

CS7410-CM 0° to 70° C 100-pin MQFP

CS7410-CQ 0° to 70° C 100-pin LQFP

RISC-32

DSP-16

Audio

Interface

Data

Cache

Instruction

Cache

X,Y Data

memory

Instruction

Cache

DS Modulator

PCM Out

CPU

MAC

CPU / MAC

IEC-958

CD

Interface

System Miscellaneous

Register

Bank

Clock

Control

PLL

80 KB

Control

Internal

SRAM

FIFO

Timers

Get Bits

External Interface

Memory Controller

2-Wire Debug Interface

256 KB

Internal

ROM

Mini

DMA

ROM/SRAM

Control

3/4 Wire Serial

Programmable I/O

PWM Out

Flash

DRAM

Control

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

Cirrus Logic, Inc.

Copyright ã Cirrus Logic, Inc. 2002

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

JUL ‘02

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CS7410

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5

1.1 AC and DC Parametric Specifications ............................................................................... 5

1.1.1 Absolute Maximum Rating .................................................................................... 5

1.1.2 Recommended Operating Conditions ................................................................... 5

1.1.3 Electrical Specifications ........................................................................................ 5

1.1.4 DC Characteristics ................................................................................................ 7

1.1.4.1 SDRAM Interface .................................................................................. 7

1.1.4.2 Serial Interface .................................................................................... 11

1.1.4.3 EDO DRAM interface .......................................................................... 12

1.1.4.4 FLASH / ROM Interface ...................................................................... 15

1.1.4.5 Audio Output Interface ........................................................................ 17

1.1.4.6 CD Interface ........................................................................................ 18

1.1.4.7 Miscellaneous Timings ........................................................................ 20

2. CS7410 SUMMARY ................................................................................................................ 21

2.1 CS7410 Typical Application ............................................................................................. 21

2.2 CS7410 Block Summaries .............................................................................................. 21

2.2.1 RISC-32 .............................................................................................................. 21

2.2.2 DSP-16 ................................................................................................................ 21

2.2.3 System Controls .................................................................................................. 21

2.2.4 Memory System .................................................................................................. 22

2.2.5 CD Interface ........................................................................................................ 22

2.2.6 Audio Interface .................................................................................................... 22

2.2.7 External Interface ................................................................................................ 22

2.2.8 System Functions ................................................................................................ 22

3. FUNCTIONAL DESCRIPTION ............................................................................................... 23

3.1 RISC-32 Processor .......................................................................................................... 23

3.2 DSP-16 Processor ........................................................................................................... 23

3.3 Memory Control ............................................................................................................... 23

3.4 CD Interface ..................................................................................................................... 23

3.5 System Control Functions ................................................................................................ 23

3.6 Audio Output .................................................................................................................... 24

4. PIN DESCRIPTION ................................................................................................................. 25

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE

“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. “Advance” product infor-

mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the infor-

mation contained in this document is accurate and reliable. However, the information is subject to change without notice and isprovided “AS IS” without warranty

of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being

relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this

information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus

and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or

other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only

for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying

for general distribution, advertising or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-

terial and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be

obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign

Trade Law and is to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE

PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT-

ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS

IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-

marks or service marks of their respective owners.

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CS7410

4.1 Pin Identification .............................................................................................................. 25

4.2 Miscellaneous Pins .......................................................................................................... 30

4.3 Serial Interface Pins ........................................................................................................ 30

4.4 SDRAM / DRAM Interface ............................................................................................... 31

4.5 ROM/NVRAM Interface ................................................................................................... 32

4.6 Digital Audio Output Interface .......................................................................................... 33

4.7 DS Modulator Interface .................................................................................................... 33

4.8 CD Interface .................................................................................................................... 34

4.9 General Purpose Input/Output (GPIO) ............................................................................ 35

4.10 Power and Ground ........................................................................................................ 36

5. 100-PIN MQFP PACKAGE SPECIFICATIONS (20X14X2.85MM) ....................................... 38

6. 100-PIN LQFP PACKAGE SPECIFICATIONS (14X14X1.4MM) ........................................... 39

LIST OF FIGURES

Figure 1. SDRAM Timing ................................................................................................................ 7

Figure 2. SDRAM Load Mode......................................................................................................... 8

Figure 3. SDRAM Burst Write ......................................................................................................... 9

Figure 4. SDRAM Burst Read......................................................................................................... 9

Figure 5. SDRAM Refresh ............................................................................................................ 10

Figure 6. Serial Interface Timing Diagram .................................................................................... 11

Figure 7. EDO Page Write Timing Diagram.................................................................................. 13

Figure 8. EDO Page Read Timing Diagram.................................................................................. 13

Figure 9. EDO Refresh Timing Diagram ....................................................................................... 14

Figure 10. FLASH/ROM Read ...................................................................................................... 15

Figure 11. FLASH/ROM Write....................................................................................................... 16

Figure 12. Audio Output Timing .................................................................................................... 17

Figure 13. CD Interface Timing..................................................................................................... 18

Figure 14. CD Interface Timing Diagrams..................................................................................... 19

Figure 15. Miscellaneous Timings................................................................................................. 20

Figure 16. CS7410 Application ..................................................................................................... 21

Figure 17. CS7410 Pin Identification............................................................................................. 25

Figure 18. 100-Pin MQFP Package (20x14x2.85mm) .................................................................. 38

Figure 19. 100-Pin LQFP Package (14X14X1.4mm).................................................................... 39

LIST OF TABLES

Table 1. SDRAM Characterization Data ......................................................................................... 7

Table 2. Serial Interface Characterization Data ............................................................................ 11

Table 3. EDO DRAM Characterization Data................................................................................. 12

Table 4. FLASH/ROM Read Characterization Data...................................................................... 15

Table 5. Audio Output Interface Symbols and Characterization Data........................................... 17

Table 6. Pin Type and Direction Legend....................................................................................... 25

Table 7. Pin Assignments ............................................................................................................. 26

Table 8. Miscellaneous Interface Pins .......................................................................................... 30

Table 9. Serial Interface Pins........................................................................................................ 30

Table 10. SDRAM Interface .......................................................................................................... 31

Table 11. EDO DRAM Interface.................................................................................................... 31

Table 12. ROM/NVRAM Interface................................................................................................. 32

Table 13. Audio Output Interface .................................................................................................. 33

Table 14. DS Output Interface....................................................................................................... 33

Table 15. CD Interface.................................................................................................................. 34

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CS7410

Table 16. Dedicated General Purpose I/O Pins ............................................................................ 35

Table 17. Redefined General Purpose Pins.................................................................................. 35

Table 18. Power and Ground ........................................................................................................ 36

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1. CHARACTERISTICS AND SPECIFICATIONS

1.1 AC AND DC PARAMETRIC SPECIFICATIONS

(AGND, DGND=0V, all voltages with respect to 0V)

1.1.1 Absolute Maximum Rating

Symbol

VDD_IO

Description

Min.

Max.

Unit

Power Supply Voltage on I/O ring

-0.5

4.6

Volts

VDD_CORE

V_I

Power Supply Voltage on core logic and PLL

Digital Input Applied Voltage (power applied)

Digital Input Forced Current

-0.5

-10

-50

2.5

5.5

10

Volts

mA

I_I

I_O

Digital Output Forced Current

50

mA

^oC

T_SOL

T_VSOL

T_STOR

T_AMB

P_TOT

Lead Soldering Temperature

260

235

125

70

Vapor Phase Soldering Temperature

Storage Temperature (no power applied)

Ambient Temperature (power applied)

Power consumption

-40

0

^oC

W

1

CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to

the device. Cirrus Logic recommends that CS7410 devices operate at the settings described in the next ta-

ble.

1.1.2

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

3.0

1.62

0

Typ

3.3

Max

3.6

Units

Volts

^oC

Supply Voltage, IO

V_DD

Supply Voltage, core and PLL

1.8V

25

1.98

70

Ambient Temperature (power applied)

T_AMB

1.1.3 Electrical Specifications

(TA = 0 to 70 ^oC)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Power Supply

Supply Current, IO

I_DD

Normal Operating

13

70

mA

Supply Current, core and PLL

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CS7410

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Digital Pins

Input Voltage, High

Input Voltage, Low

Input Current

V_IH

2.0

Volts

V_IL

I_IN

0.8

+1

V_IN= V_DDor V_SS

-1

2.4

-1

mA

Input Pull up/down resistor

Output Voltage, High

Output Voltage, Low

High-Z-state Leakage

R_I

75

KW

V_OH

V_OL

I_OZ

@ buffer rating

V_OUT= V_SSor V_DD

Volts

0.4

+1

mA

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CS7410

1.1.4 DC CHARACTERISTICS

(TA= 25°C; VDD_PLL=VDD_CORE=1.8V±10%, VDD_IO=3.3V±10%)

1.1.4.1 SDRAM Interface

Symbol

^tmper

Description

DR_CKO Period

Min

22

Typ

Max

Unit

ns

^tmco

Output Delay from DR_CKO active edge

M_D[15:0] delay from DR_CKO

M_D[15:0] valid time after DR_CKO

M_D[15:0] setup to DR_CKO

19

ns

t

mdow

^tmhw

^tmsur

^tmhr

5

13

0

M_D[15:0] hold time after DR_CKO

Table 1. SDRAM Characterization Data

t_mper

DR_CKO

t_mco

t_mdow

t_mhr

M_WE_L

M_A

DR_RAS_L

DR_CAS_L

t_mhw

M_D

(write)

t_msur

M_D

(read)

Figure 1. SDRAM Timing

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CS7410

DR_CKO

DR_RAS_L

DR_CAS_L

M_A

M_D

M_WE_L

Figure 2. SDRAM Load Mode

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CS7410

DR_CKO

DR_RAS_L

DR_CAS_L

M_A

M_D

ADCAS

D0

ADRAS

D1

...

Dn

M_WE_L

Figure 3. SDRAM Burst Write

DR_CKO

DR_RAS_L

DR_CAS_L

M_A

ADRAS

ADCAS

M_D

D1

D2

...

Dn

M_WE_L

Figure 4. SDRAM Burst Read

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CS7410

DR_CKO

DR_RAS_L

DR_CAS_L

M_A

M_D

M_WE_L

Figure 5. SDRAM Refresh

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1.1.4.2 Serial Interface

Symbol

Description

Min

66

Typ

Max

Unit

ns

^tclk_per

^tDMs

^tDMh

^tDSs

Clock period

Master-mode data setup

Master-mode data hold

Slave-mode data setup

Master chip select to clock setup

Slave mode data hold

28

15

28

0

ns

^tCMs

^tDSh

Table 2. Serial Interface Characterization Data

t_{clk_per}

SER2_CLK

(CPOL=0)

t_CMs

SER2_CLK

(CPOL=1)

t_DMs

t_DMh

SER2_DO

(master)

MSB

LSB

t_DSs

MSB

t_DSh

SER2_DI

LSB

(slave)

SER2_CS

Figure 6. Serial Interface Timing Diagram

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CS7410

1.1.4.3 EDO DRAM interface

Symbol

Description

Min

72

Typ

Max

Unit

ns

^tRAS

RAS low time

^tRP

RAS high pulse time

RAS fall to CAS fall

40

38

30

15

29

10

18

ns

^tRCL

^tCAS

^tCPN

^tCAH

^tASR

^tRAH

^tASC

^tAA

CAS low time

CAS high time

CAS fall to address row

Address row to RAS fall

RAS fall to address column

second address column (burst) to CAS fall 10

Column address to data setup

CAS fall to data setup

35

^tCAC

^tCSR

^tCHR

^tCRH

^tWDS

^tWDH

^tWS

17

CAS fall to RAS fall

19

18

6

RAS fall to CAS rise

CAS rise to RAS rise

Write data setup to CAS fall

Write data hold to CAS fall

Write enable setup to CAS fall

Write enable hold to CAS fall

RAS fall to OE fall

12

29

13

20

-5

0

^tWH

^tROE

^tOER

^tDCH

5

RAS rise to OE rise

Read data hold to CAS rise

Table 3. EDO DRAM Characterization Data

Note:Values shown are for minimum internal clock period (11ns) and all programmed wait states enabled.

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CS7410

t_RAS

DR_RAS_L

DR_CAS_L

t_RP

t_RCL

t_CRH

t_CAS

t_CPN

t_CAH

t_ASR

t_RAH

t_ASC

M_A

M_D

ADRAS

ADCAS

DATA

ADCAS

t_WDS

t_WDH

DATA

t_WS

t_WH

M_AP_WE

Figure 7. EDO Page Write Timing Diagram

t_ROE

M_AP_OE

t_OER

t_RAS

DR_RAS_L

t_RP

t_CRH

t_RCL

t_CAS

DR_CAS_L

t_CPN

t_CAH

t_ASR

t_RAH

t_ASC

M_A

M_D

ADRAS

ADCAS

DATA

ADCAS

t_CAC

t_DCH

t_AA

DATA

Figure 8. EDO Page Read Timing Diagram

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CS7410

t_RAS

DR_RAS_L

DR_CAS_L

t_CSR

t_CHR

Figure 9. EDO Refresh Timing Diagram

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CS7410

1.1.4.4 FLASH / ROM Interface

Symbol

^tCSpw

Description

Min

135

Typ

Max

Unit

ns

CE low period

^tRDd1

^tRDd2

^tADs

CE fall to output enable fall

CE rise to output enable rise

Address setup to CE fall

5

ns

-5

-10

5

10

28

^tDAs

Data setup after address¹

All outputs setup before WE

^tWRSU

^tWRPW

^tWRH

95

WE pulse width

170

95

All outputs hold after WE

Table 4. FLASH/ROM Read Characterization Data

1._{Value shown for 3 programmed wait states.}

Note:Values shown are for minimum internal clock period (11ns) and no programmed wait states.

t_CSpw

NVM_CE_L

M_WE_L

t_RDd1

t_RDd2

M_AP_OE

M_A

t_ADs

t_DAS

M_D

Figure 10. FLASH/ROM Read

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CS7410

NVM_CE_L

M_A

M_D

t_WRPW

t_WRSU

t_WRH

M_WE_L

M_AP_OE

Figure 11. FLASH/ROM Write

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CS7410

1.1.4.5 Audio Output Interface

Symbol

^taxch

^taxcl

^taxper

^taoper

^tsdmo

^tsdmi

Description

Min

Typ

50

Max

Units

%

PCM_XCLK High Time (PCM_XCLK is Input/Output)

42

55

%

PCM_XCLK Low Time (PCM_XCLK is Input/Output

PCM_XCLK period (Input/Output)

ns

440

PCM_BCK period (Output)

PCM_BCK delay from PCM_XCLK output transition¹

PCM_BCK delay from PCM_XCLK input transition¹

PCM_LRCK delay from PCM_BCK transition¹

PCM_D[3:0] delay from PCM_BCK transition¹

5

15

5

ns

^tlrds

^tadsm

5

Table 5. Audio Output Interface Symbols and Characterization Data

1. _{Active clock edge is programmable. Timing is referenced from the active edge.}

t

axper

PCM_XCK(Input/Output)

PCM_BCK(Output)

t

axcl

axch

sdmi

sdmo

t

t _aoper

PCM_BCK(Output)

t

lrds

PCM_LRCK(Output)

t _adsm

PCM_DO[1:0] (Output)

Figure 12. Audio Output Timing

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CS7410

1.1.4.6 CD Interface

Symbol

^tslri

^tsdi

^thsdi

Description

CD_LRCK setup to CD_BCK active edge

Min

Typ

Max

Units

ns

7

3

CD_DATA and CD_C2P0 setup to CD_BCK active edge

CD_DATA and CD_C2P0 hold time after CD_BCK active edge

ns

Note:Active edge of CD_BCLK is programmable

CD_BCK(Input)*

t_slri

CD_LRCK(Input)

CD_DO (Input)

t_sdi

t_hsdi

CD_C2PO (Input)

Figure 13. CD Interface Timing

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CS7410

CD_BCK

CD_LRCK

DATA

Left Channel

MSB

Right Channel

MSB

LSB

0

LSB

0

Invalid

1

Invalid

1

9

6

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Lower (Left Channel)

Upper (Left Channel)

Lower (Right Channel)

Upper (Right Channel)

C2P0

32-bit BCK, MSB First, Right Channel Low, C2P0 LSB First, Data latch timing high

CD_BCK

CD_LRCK

DATA

Right Channel

MSB

Left Channel

LSB

0

MSB

LSB

0

Invalid

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Upper (Right Channel)

Lower (Right Channel)

Upper (Left Channel)

Lower (Left Channel)

C2P0

32-bit BCK, MSB First, Left Channel Low, C2P0 MSB First, Data latch timing low

CD_BCK

CD_LRCK

DATA

Left Channel

Right Channel

Left Channel

MSB

LSB

0

MSB

15 14 13 12 11 10

LSB

0

Invalid

1

Invalid

1

Invalid

15 14 13 12 11 10

9

8

7

6

5

4

3

2

9

8

7

6

5

4

3

2

15 14 13 12 11 10

8

7

8

7 6

5

10

5

Upper (Left Channel)

Lower (Left Channel)

Upper (Right Channel)

Lower (Right Channel)

Upper (Left Channel)

C2P0

24-bit BCK, MSB First, Right Channel Low, C2P0 MSB First, Data latch timing high

CD_BCK

CD_LRCK

DATA

Left Channel

Right Channel

Left Channel

LSB

0

MSB

10 11 12 13 14 15

LSB

0

MSB

LSB

0

Invalid

1

2

1

2

3

4

5

6

7

8

9

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15

3

4

5

8 9

Upper (Left Channel)

Lower (Left Channel)

Upper (Right Channel)

Lower (Right Channel)

Upper (Left Channel)

C2P0

24-bit BCK, LSB First, Right Channel Low, C2P0 MSB First, Data latch timing low

CD_BCK

CD_LRCK

DATA

Left Channel

Right Channel

Left Channel

MSB

LSB

0

MSB

15 14 13 12 11 10

LSB

0

1

2

Invalid

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Invalid

9

8

7

6

5

4

3

Invalid

15 14 13 12 11 10

9

7 6

24-bit BCK, MSB First, Right Channel Low, Data latch timing high (Note: no C2P0 for this format)

CD_BCK

CD_LRCK

DATA

Right Channel

Left Channel

Right Channel

Left Channel

MSB

15 14 13 12 11 10

LSBMSB

15 14 13 12 11 10

LSBMSB

15 14 13 12 11 10

LSBMSB

15 14 13 12 11 10

LSBMSB

15 14 13

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

Lower (Right Channel)

Upper (Right Channel)

Lower (Left Channel)

Upper (Left Channel)

Lower (Right Channel)

Upper (Right Channel)

Lower (Left Channel)

Upper (Left Channel)

C2P0

16-bit BCK, MSB First, Left Channel Low, C2P0 LSB First, Data latch timing high

Figure 14. CD Interface Timing Diagrams

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CS7410

1.1.4.7 Miscellaneous Timings

Symbol

Description

Min

Typ

Max

Unit

^txclper¹

XTLCLK period

59.05

ns

^trstl

^tgph

^tgpl

RST_N Low Pulse Width

1000

ns

GPIO PW High

GPIO PW Low

50

1._{Value represents typical application with 16.934 MHz crystal}

xccper

t

XTLCLOCK

RESET-N

t^rst

l

t^gp

tgph

l

GPIO

Figure 15. Miscellaneous Timings

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2. CS7410 SUMMARY

2.1

CS7410 Typical Application

Figure 16 shows an example of a complete audio player using the CS7410.

Speakers/Headphones

(2 or 4 channel)

IEC-958

4 Chan.

2 Chan.

Servo

DSP/Rd

Channel

Optical

Driver

PCM

DACs

OP-AMPs

CD

Interface

DAC

Out

Digital Audio Out

Debug

Serial

Interface

CS7410

Memory

Interface

GPIO

LCD

Controller/

Display

DRAM

EDO/SDRAM

(optional)

0-8 MB

For shock protection

ROM/FLASH

(optional)

0-2 MB

Keypad

Matrix

For new code

Serial

EEPROM

(optional)

IR

receiver

Figure 16. CS7410 Application

•

16-bit fixed point logic, with 36 bit accumula-

tor.

2.2

CS7410 Block Summaries

2.2.1 RISC-32

Single-cycle throughput, 2-cycle latency multi-

ply accumulate, 16-bit simple integer logic

•

Powerful 32-bit RISC processor

Comprehensive development tool support

Big or little endian data formats supported

512 byte instruction cache, 8 Kbyte program

visible local memory

32x32 (64-bit result) MAC, 2 cycles / multiply

with C support

•

Single cycle instructions, runs up to 90 MHz

DSP MAC is pipelined, 1 cycle / multiply

•

4 Kbyte instruction cache, 2 Kbyte data cache

Single cycle instructions, runs up to 90 MHz

2.2.3 System Controls

•

Includes 32 hardware lockable semaphore reg-

isters

2.2.2 DSP-16

Powerful 16-bit DSP processor

•

Two general-purpose registers for inter-proces-

DS553PP1

21

CS7410

sor communication

•

Integrated sigma-delta (DS) stereo audio mod-

ulator

•

Three 32-bit timers for I/O and other uses, with

programmable interval rates

2.2.7 External Interface

“Getbits” module accelerates peripheral stream

parsing

•

2-wire serial slave port, used for debug

3- or 4-wire synchronous serial master/slave

port for external controller or slave peripheral

Both hardware and software interrupts on data

or debug

•

Separate synchronous serial master port opti-

mized for receiving CD sub-codes

2.2.4 Memory System

•

Large internal SRAM (80 Kbyte) and internal

program ROM (256 Kbyte)

Up to 29 programmable bi-directional I/O

(GPIO) and up to 9 output only (GPO) pins

(some multiplexed with other peripherals)

Supports both Synchronous and EDO DRAM

(256 KBytes to 8 MBytes) for ESP

•

All pins defined as GPIOs can be used to re-

ceive edge or level detection interrupts.

Supports one bank of FLASH and ROM (up to

2 MBytes) for nonvolatile storage

Pulse-width modulated (PWM) output pin can

be used to create simple ADC using low-cost

comparator (i.e., for battery voltage monitor)

4-, 8-, or16-bit data bus for DRAM, 8-bit data

bus for ROM

2.2.8 System Functions

2.2.5 CD Interface

•

Internal oscillator uses external crystal, or re-

ceives clock (i.e. 16.9 MHz) from CD servo

•

Glueless interfaces to CD servo chip set, sup-

porting all standard CD formats

Internal PLL generates any system clock fre-

quency, chip can run up to 90 MHz

•

Includes pattern matching hardware to support

fast ESP recovery

Includes clock divider and clock shutoff cir-

cuits for low power/sleep modes

2.2.6 Audio Interface

2

•

Supports 4 channels PCM, I S connectivity at

Advanced 0.18 micron CMOS technology,

runs off 1.8 V and 3.3 V

up to 24 bits

Flexible audio clocking scheme using internal

PLL and dividers, or external pins

•

All I/O pins are 3.3 V, with 5 V tolerance

100-pin MQFP package

Simultaneous IEC-958 output with program-

mable channel status and user data

100-pin LQFP package

22

DS553PP1

CS7410

memory. This arbitration and scheduling guaran-

tees the allocation of sufficient bandwidth to the

various clients. An optimal application will use

only internal ROM and SRAM for code and data

storage, which results in the best timing and lowest

power consumption.

3. FUNCTIONAL DESCRIPTION

3.1 RISC-32 Processor

The CS7410 includes a powerful, proprietary 32-

bit RISC processor backed by powerful software

development tools. The RISC-32 has a MAC en-

gine which performs multiply/accumulate in 2 cy-

cles with C support, effectively achieving single

cycle throughput.

External DRAM may be used for runtime code

storage or for ESP RAM. In both of these applica-

tions, the data throughput requirement is low, and

the Memory Controller acts as a DMA engine to

move data between external and internal memory

with minimal power consumption. The internal

ROM contains most of the code required for audio

decoding and system functions.

There are other instructions that are designed to

help with performing audio decoding. The RISC

processor coordinates on-chip multi-threaded

tasks, as well as supervises system activities such

as keypad and front panel display control.

Additional code can be stored in external ROM

(managed by the Memory Controller) or a small se-

rial ROM (controlled by GPIOs). The CS7410 also

supports code storage in external FLASH with in-

system write capability for customer code updates.

Future firmware releases will provide a complete

solution requiring no external ROM.

3.2

DSP-16 Processor

The CS7410 contains a proprietary digital signal

processor (DSP) called DSP-16, which is opti-

mized for audio and sound applications. In the

CS7410, the DSP-16 assists with audio decoding

and provides added functions such as surround

sound and equalization. The DSP performs 16-bit

simple integer operations, and has a 16-bit fixed

point logic unit with a 32-bit accumulator.

3.4

CD Interface

The CD Interface receives compressed or uncom-

pressed (direct audio) data from the CD servo/read

channel chip, performs descrambling and CRC

checking, and writes the data to an internal FIFO.

Additional C3 error decoding is done in software.

The CD interface is compatible with all commonly

used CD formats.

There are 24 general-purpose registers, and eight

independent address generation registers, featur-

ing: post-increment ALU, linear and circular buffer

operations, bit reverse ALU operations, and dual

operand read from memory. The multiply-accumu-

lator has single-cycle throughput, with two cycle

latency. The DSP is optimized for bit packing and

unpacking operations. The interface to main mem-

ory is designed for bursting flexible block sizes and

skip counts.

The CS7410 contains a hardware pattern matching

circuit to scan the incoming CD data for a pattern

of up to 64 bytes. This circuit is used to assist the

Electronic Shock Protection function by quickly lo-

cating and matching the incoming data with data

stored in the ESP RAM.

3.3

Memory Control

The Memory Controller performs the arbitration

functions for all the other modules in the CS7410,

allowing access to internal ROM and SRAM, and

to external ROM and DRAM. The Memory Con-

troller services and arbitrates a number of clients

and stores their code and/or data within the local

3.5

System Control Functions

The system control functions are used to coordinate

the activities of the multiple processors, and to pro-

vide the supporting system operations. Two 32-bit

communication registers are available for inter-

DS553PP1

23

CS7410

processor communication, and 32 semaphore reg- channels of PCM data to external audio DACs, plus

isters are used for resource locking. Three timers an independent IEC-958 encoded output. The IEC-

are available for general-purpose functions, as well

958 output has fully programmable channel status

as more specialized functions, such as watchdog (commercial), and provides a flexible solution to

timers and performance monitoring.

support all IEC-958 modes for user data. The audio

output circuit contains an auto-mute detect circuit,

which can generate internal or external mute con-

trols

The large number of general purpose I/Os offers

flexibility in system configurations. Three separate

synchronous serial interfaces, conforming to indus-

try-standard protocols, are available for a variety of PCM FIFO data up to 18 bits can also be output by

system interface functions. Four general purpose the on-board sigma-delta stereo modulator. The

software interrupts and twelve hardware interrupts sigma-delta modulator yields a typical 85 dB sig-

help reduce peripheral overhead and improve UI nal-to-noise ratio with few external components re-

responsiveness. Power-down control of the internal

quired, resulting in a low-cost, low parts count

clocks is also possible. An internal PLL is used to analog front end. The modulator has a 32x upsam-

generate the internal system and memory clocks as pling filter, followed by a 32x interpolator, and fi-

th

well as audio clocks for all supported sample rates. nally a 5 -order Sigma-Delta modulator. The

auto-mute circuit also works on the modulator out-

3.6

Audio Output

put, and there are separate programmable attenua-

tors for the modulator output and both PCM

outputs.

Decoded audio data is written into an output FIFO

in 16-, 18-, 20- or 24-bit PCM format. A flexible

audio output stage can simultaneously output 4

24

DS553PP1

CS7410

4. PIN DESCRIPTION

4.1 Pin Identification

Figure 17 shows the CS7410 pins grouped by function, also showing the number of pins in each group.

Figure 17. CS7410 Pin Identification

Table 6 lists the conventions used to identify the pin type and direction.pin assignments.

I: Input

S: Schmitt trigger on input

U: Pull up resistor

O: Output

O4: Output – 4mA drive

T4: High Z output – 4mA drive

B: Bi-direction

B4: Bi-direction – 4mA drive

D4: Bi-direction with 4mA open drain output

Table 6. Pin Type and Direction Legend

DS553PP1

25

CS7410

Pwr: +2.5V or +3.3V power supply voltage

Gnd: Power supply ground

Name_N: Low active

Name_L: Low active

Table 6. Pin Type and Direction Legend (Continued)

Table 7 lists the pin number, pin name, and pin type for the 100-pin CS7410 package. For signal pins, the

pin direction after reset is shown. The primary function and pin direction is shown for all signal pins. For

some signal pins, a secondary function and direction are also shown.

1

Name

PLL_GND

PLL_1V8

M_D_15

Type Reset

Function #1

PLL Ground

Dir

Function #2

Dir Note

Gnd

Pwr

2

PLL Power

3

B4

I

DRAM Data[15]

B

NVMem

O

Address[19]

4

M_D_14

M_D_13

M_D_12

M_D_11

M_D_10

M_D_9

DRAM Data[14]

DRAM Data[13]

DRAM Data[12]

DRAM Data[11]

DRAM Data[10]

DRAM Data[9]

DRAM Data[8]

NVMem

Address[18]

O

B

5

NVMem

Address[17]

6

NVMem

Address[16]

7

NVMem

Address[15]

8

NVMem

Address[14]

9

NVMem

Address[13]

10

M_D_8

NVMem

Address[12]

11

12

13

14

15

16

17

M_D_7

B4

DRAM Data[7]

Core Power

NVMem Data[7]

NVMem Data[6]

NVMem Data[5]

CORE_1V8

M_D_6

Pwr

B4

I

DRAM Data[6]

Core Ground

B

O

B

CORE_GND Gnd

M_D_5

B4

Pwr

O

I

DRAM Data[5]

I/O Power

IO_3V3

XTLCLK_O

O

Oscillator Out

Table 7. Pin Assignments

26

DS553PP1

CS7410

18

19

20

21

22

23

24

25

Name

XTLCLK_I

IO_GND

M_D_4

Type Reset

Function #1

Oscillator In

Dir

Function #2

Dir Note

I

Gnd

B4

I/O Ground

I

DRAM Data[4]

DRAM Data[3]

DRAM Data[2]

DRAM Data[1]

DRAM Data[0]

DRAM Address[11]

B

O

NVMem Data[4]

NVMem Data[3]

NVMem Data[2]

NVMem Data[1]

NVMem Data[0]

B

M_D_3

M_D_2

M_D_1

M_D_0

M_A_11

NVMem

Address[11]

O

1

26

27

28

29

30

31

32

33

34

35

36

M_A_10

M_A_9

M_A_8

M_A_7

M_A_6

M_A_5

M_A_4

M_A_3

M_A_2

M_A_1

M_A_0

B4

T4

I

DRAM Address[10]

DRAM Address[19]

DRAM Address[8]

DRAM Address[7]

DRAM Address[6]

DRAM Address[5]

DRAM Address[4]

DRAM Address[3]

DRAM Address[2]

DRAM Address[1]

DRAM Address[0]

O

NVMem

Address[10]

1

NVMem

Address[9]

1

NVMem

Address[8]

1

NVMem

Address[7]

1, 3

3

NVMem

Address[6]

NVMem

Address[5]

NVMem

Address[4]

NVMem

Address[3]

NVMem

Address[2]

NVMem

Address[1]

3

NVMem

Address[0]

3

37

38

39

DR_RAS_L

CORE_1V8

DR_CAS_L

T4

DRAM RAS_L

Core Power

Pwr

T4

I

DRAM CAS_L

O

Table 7. Pin Assignments (Continued)

DS553PP1

27

CS7410

40

41

42

43

44

45

46

Name

Type Reset

Function #1

Core Ground

Dir

O

Function #2

Dir Note

CORE_GND Gnd

M_WE_L

IO_GND

DR_CKO

IO_3V3

T4

I

DRAM WE_L

I/O Ground

NVM_WE_L

Gnd

T4

SDRAM CKO

I/O Power

O

Pwr

T4

DR_CKE

DR_BS_L

I

SDRAM CKE

SDRAM BS_L

O

B4

NVMem

Address[20]

1

47

M_AP_OE

B4

I

SDRAM AP, EDO DRAM

OE_L

O

NVM_ OE_L

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

NVM_CE_L

KP_IN_0

T4

I

NVM_CE_L

GPIO[19]

O

B

B4U

B4

KP_IN_1

GPIO[20]

KP_IN_2

GPIO[21]

KP_IN_3

GPIO[22]

KP_IN_4

GPIO[23]

KP_OUT_0

KP_OUT_1

KP_OUT_2

KP_OUT_3

KP_OUT_4

IR_IN

GPIO[24]

B4

GPIO[25]

B4

GPIO[26]

B4

GPIO[27]

B4

GPIO[28]

B4S

D4S

B4S

Gnd

B4

GPIO[4]

SER1_CLK

SER1_DAT

SER4_CLK

SER4_DAT

IO_GND

Debug Port Clock

Debug Port Data

GPIO[5]

GPIO[6]

I/O Ground

SER2_CLK

SER2_DI

I

Serial2 Clock

Serial2 Data In

Serial2 Data Out

Table 7. Pin Assignments (Continued)

B

GPIO[7]

GPIO[8]

GPIO[9]

B

B4

SER2_DO

B4

28

DS553PP1

CS7410

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

Name

SER2_CS

SER3_CLK

SER3_DO

CORE_1V8

SER3_DI

Type Reset

Function #1

Serial2 Chip Select

Serial3 Clock

Dir

B

Function #2

GPIO[10]

Dir Note

B4

Pwr

B4

I

B

O

GPIO[11]

Serial3 Data Out

Core Power

O

GPIO[12]

I

Serial3 Data In

Core Ground

I

GPIO[13]

GPIO[14]

B

CORE_GND Gnd

SER3_SS0

IO_3V3

B4

Pwr

B4

Serial3 Chip Select0

I/O Power

O

SER3_SS1

SERVOCK

PCM_XCK

I

Serial3 Chip Select1

Servo Clock In

PCM_XCK

O

I

GPIO[15]

GPIO[17]

B

I

B

O

I

PCM_MUTE B4

I

PCM_MUTE

GPO[4]

O

B

1

CD_C2P0

CD_BCLK

CD_LRCK

CD_DATA

DAC_LP

B4

IS

I

CD_C2P0

GPIO[16]

I

CD_BCLK

I

CD_LRCK

I

CD_DATA

I

O4

Gnd

O4

Pwr

O4

IS

O

DS DAC Left Positive Out

DS DAC Left Negative Out

I/O Ground

O

GPO[5]

GPO[6]

O

DAC_LN

IO_GND

DAC_RP

DAC_3V3

DAC_RP

RST_N

O

DS DAC Right Positive Out

DS DAC I/O Power

DS DAC Right Negative Out

Reset_L

O

GPO[7]

GPO[8]

O

I

O

I

TEST

I

Manufacturing Test

PCM_BCK

I

PCM_BCK

PCM_LRCK

PCM_DO_0

PCM_DO_1

IEC958_O

GPIO_0

B4

O

I

O

B

GPO[0]

GPO[1]

GPO[2]

GPO[3]

GPIO[18]

O

B

1

2

1

PCM_LRCK

PCM_Dout[0]

PCM_Dout[1]

IEC-958 Out

I

GPIO[0]

Table 7. Pin Assignments (Continued)

DS553PP1

29

CS7410

98

Name

GPIO_1

GPIO_2

Type Reset

Function #1

Dir

B

Function #2

Dir Note

B4

I

GPIO[1]

GPIO[2]

GPIO[3]

PWM_Out

O

99

B

100 GPIO_3

B

Table 7. Pin Assignments (Continued)

1. Optional pull up or pull down resistor may be connected to configure internal ROM program

2. Required external resistor required to select processor boot from internal ROM (pull down) or external

ROM (pull up).

3. Drives for a short time after reset, then reverts to high impedance

4.2

Miscellaneous Pins

These pins described in Table 8 are used for used for basic functions such as clocking, reset and infrared

receiver interface. The main system clock can be derived from an external crystal connected between the

XTLCLK_I and XTLCLK_O pins, or can be received from the CD servo chip via the XTLCLK_I pin. The

CS7410 can accommodate a variety of input frequencies, such as 44.1 KHz x 256, x 384, or x 512.

17

18

90

91

Signal Name

XTLCLK_O

XTLCLK_I

RST_N

Type

Description

O

I

Crystal output

Crystal input, or oscillator input

Asynchronous reset input, active low

Manufacturing test, tie to ground

I

TEST

I

Table 8. Miscellaneous Interface Pins

4.3

Serial Interface Pins

The CS7410 Serial Interface pins are described in Table 9. CS7410 has three dedicated serial ports, each

with different protocols. The 2-wire serial port (SER1) supports industry standard protocols. This port is typ-

ically used for debug, with the CS7410 as the slave. The slave chip select address is programmable, and

defaults to a 7-bit value of 0x1B. A second serial controller (SER2) supports industry standard 3-wire and

4-wire protocols. In master mode, this interface can control a front panel or a small non-volatile memory. In

slave mode, it can operate under control of an external processor, for example, in a combination unit. The

third serial port (SER3) is a 5-wire master device optimized for reading CD subcodes from the servo chip,

and can also be used a general-purpose serial port.

60

61

65

Signal Name

SER1_CLK

SER1_DAT

SER2_CLK

Type

Description

B

Debug port serial clock

Debug port serial data

Clock for 4-wire serial port (output for master mode, input

for slave mode)

66

67

SER2_DI

SER2_DO

I

Input data for 4-wire serial port

B

Output data for 4-wire serial port – may function as bidi-

rectional data in 3-wire mode.

Table 9. Serial Interface Pins

30

DS553PP1

CS7410

68

SER2_CS

B

Chip select for 4-wire serial port (output if master, input if

slave mode). Can also be used as bidirectional ready line.

69

70

72

74

76

SER3_CLK

SER3_DO

SER3_DI

O

I

Clock output

Data output – up to 32 bits per transfer.

Data input – up to 96 bits per transfer.

Slave select for first peripheral (programmable polarity)

SER3_SS0

SER3_SS1

O

Slave select for second peripheral (programmable polar-

ity)

Table 9. Serial Interface Pins (Continued)

4.4

SDRAM / DRAM Interface

These pins are used to interface the CS7410 with external synchronous or EDO DRAMs. Data widths of 4

to 16 bits are supported. The CS7410 supports word or block transfers (partial word transfers are not re-

quired). Table 10 gives instructions on how to interface to any particular configuration of SDRAM. Table 11

gives pin definitions for interfacing to EDO DRAM.

Signal Name

DRAM

Type

Description

3, 4, 5, 6, 7, 8, 9,

10, 11, 13, 15, 20,

21, 22, 23, 24

B

Memory Data Bus.

Data[15..0]

25, 26, 27, 28,

29, 30, 31, 32,

33, 34, 35, 36

DRAM

Address[11..0]

O

Memory Address Bus. Connect in order starting with

DR_Addr[0] to all RAM address pins not already connected

to DR_BS_L or DR_AP.

37

39

41

43

45

46

47

DR_RAS_L

DR_CAS_L

M_WE_L

O

Memory Row Address Strobe

Memory Column Address Strobe

Memory Write Enable

DR_CKO

DR_CKE

SDRAM Clock

SDRAM Clock Enable

DR_BS_L

M_AP_OE

Bank Selection. Always connect to RAM BS or BS0 pin.

Memory Auto Pre-charge. Always connect to RAM AP pin.

Table 10. SDRAM Interface

Signal Name

Type

Description

3, 4, 5, 6,

9, 10,

7, 8, DRAM

B

Memory Data Bus.

11, 13,

Data[15..0]

15, 20, 21, 22,

23, 24

Table 11. EDO DRAM Interface

DS553PP1

31

CS7410

Signal Name

DRAM

Type

Description

25, 26, 27, 28,

29, 30, 31, 32,

33, 34, 35, 36

O

Memory Address Bus.

Address[11..0]

37

39

41

47

DR_RAS_L

DR_CAS_L

M_WE_L

O

Memory Row Address Strobe

Memory Column Address Strobe

Memory Write Enable

M_AP_OE

Memory Output Enable

Table 11. EDO DRAM Interface (Continued)

4.5

ROM/NVRAM Interface

The ROM/NVRAM Interface pins are described in Table 12. This interface connects to the non-volatile

memory that contains the firmware. The memory could be ROM, NVRAM (FLASH), EEPROM, or any com-

bination of these memory types. This interface can also connect to SRAM that would emulate a ROM on a

development system. The bus width is always 8 bits. Most of these pins are shared with the DRAM interface,

which operates simultaneously with the ROM/NVRAM interface. A number of pins are defined to accept con-

figuration input at power-up (see Table 7), allowing different branches to be taken in the firmware. A config-

uration resistor is required on pin PCM_DO_0 to select whether the processor will boot from internal or

external ROM.

Signal Name

Type

Description

11, 13, 15, 20,

21, 22, 23, 24

NVMem Data[7..0]

B

Memory Data Bus (shared with bits [7:0] of DRAM data

bus).

25, 26, 27, 28,

29, 30, 31, 32,

33, 34, 35, 36

NVM_Addr[11..0]

NVM_Addr[19..12]

O

Memory Address Bus[11..0] (shared with DRAM address

bus)

3, 4, 5, 6, 7, 8, 9,

10

Memory Address Bus[19..12] (shared with bits [15..8] of

DRAM data bus).

46

41

47

48

NVM_Addr[20]

NVM_WE_L

NVM_OE_L

NVM_CE_L

O

Memory Address Bus[20] (DRAM BS_L pin).

NVRAM Write Enable (shared with DRAM WE_L pin)

ROM/NVRAM Chip Enable.

Table 12. ROM/NVRAM Interface

32

DS553PP1

CS7410

4.6

Digital Audio Output Interface

The Digital Audio Output Interface pins are described in Table 13. This is the audio PCM interface that con-

nects to an audio PCM DAC. The sample rate and the size of the samples are programmable to accommo-

date any commercially available DAC. The CS7410 has two data output pins, for up to 4 channels of PCM

output, and a separate output pin to simultaneously output IEC-958 encoded data (either compressed or

uncompressed).

Signal Name

Type

Description

78

77

PCM_XCK

B

Audio 256x/384x/512x Clock input or output to Serial DAC.

When output, it’s generated from CS7410 internal PLL.

SERVOCK

I

Optional source of Audio 256x/384x/512x Audio Clock. May

be used for CD direct audio to match input and output

clocks.

79

92

PCM_MUTE

PCM_BCK

O

Audio Mute control to external DAC. Polarity is programma-

ble and is three-stated at power up.

Audio Bit Clock output to serial DAC. Polarity is programma-

ble.

93

94

95

96

PCM_LRCK

PCM_DO_0

PCM_DO_1

IEC958_O

O

Audio Out Left/Right Clock to serial DAC.

Audio Serial PCM Data Out[0].

Audio Serial PCM Data Out[1].

IEC-958 Output

Table 13. Audio Output Interface

4.7

DS Modulator Interface

The DS Interface pins are described in Table 14. The CS7410 contains a stereo Delta-Sigma (DS) modula-

tor, which outputs two differential digital signals on four pins. These outputs are design to drive an external

op-amp based integrator circuit (contact Cirrus Logic Applications Engineering for details).

84

85

87

89

Signal Name

DAC_LP

Type

O

Description

DS left channel, positive output

DAC_LN

DAC_RP

O

DS left channel, negative output

DS right channel, positive output

O

DAC_RN

O

Table 14. DS Output Interface

DS553PP1

33

CS7410

4.8

CD Interface

The CD Interface pins are described in Table 15. This interface is used to read serial CD data from a CD

servo/read channel chip. The interface supports all standard formats, including 16 MHz, 24 MHz and 32

MHz clocks per container. Control of the CD servo chip is done by the RISC processor using GPIOs, and

CD subcode data is read using the dedicated serial interface (SER3).

81

82

83

80

Signal Name

CD_BCLK

CD_LRCK

CD_DATA

CD_C2P0

Type

Description

CD clock input – polarity is programmable

CD left-right clock input

I

CD serial data input

CD error signaling input

Table 15. CD Interface

34

DS553PP1

CS7410

4.9

General Purpose Input/Output (GPIO)

The CS7410 provides a number of General Purpose Input/Output (GPIO) pins, each with individual output

three-state controls, and a number of General Purpose Output (GPO) pins. Table 16 shows the 17 dedicat-

ed GPIO pins. A naming scheme for these pins was chosen to encourage system designers to adhere to

standardized pin usage. Table 17 shows the GPIO and GPO pins that can be redefined from other functions.

For redefined pins, mode control register bits select the normal function or GPIO/GPO function for the pins.

Table 17 also indicates which mode bit controls each pin.

Signal Name

GPIO[3:0]

KP_IN[4:0]

KP_OUT[4:0]

IR_IN

Type

B

Description

4 General purpose I/O on dedicated pins

5 General purpose I/O on dedicated pins

General purpose I/O on dedicated pin

100, 99, 98, 97

53, 52, 51, 50, 49

B

58, 57, 56, 55, 54

B

59

62

63

B

SER4_CLK

SER4_DAT

B

Table 16. Dedicated General Purpose I/O Pins

65

67

68

66

69

70

72

74

76

80

77

92

93

94

95

79

84

Signal Name

Type

B

Description

SER2_CLK

SER2_DO

SER2_CS

SER2_DI

GPIO controlled by Mode bit 2

GPIO controlled by Mode bit 3

GPIO controlled by Mode bit 4

GPIO controlled by Mode bit 5

GPIO controlled by Mode bit 6

GPIO controlled by Mode bit 7

GPO controlled by Mode bit 8

GPO controlled by Mode bit 9

GPO controlled by Mode bit 10

GPO controlled by Mode bit 11

GPO controlled by Mode bit 12

GPO controlled by Mode bit 13

B

SER3_CLK

SER3_DO

SER3_DI

B

SER3_SS0

SER3_SS1

CD_C2P0

SERVOCK

PCM_BCK

PCM_LRCK

PCM_DO_0

PCM_DO_1

PCM_MUTE

DAC_LP

B

O

Table 17. Redefined General Purpose Pins

DS553PP1

35

CS7410

85

87

89

96

Signal Name

DAC_LN

Type

O

Description

GPO controlled by Mode bit 13

GPIO controlled by Mode bit 14

DAC_RP

O

DAC_RN

O

IEC958_O

B

Table 17. Redefined General Purpose Pins (Continued)

4.10 Power and Ground

Table 18 describes the power and ground pins. The CS7410 requires 3 different types of power supplies for

the PLLs, internal logic, and IO pins. The PLLs and internal logic use 1.8 V supply voltage. The IO pins use

3.3 V supply voltage. An optional separate supply can be used to provide clean 3.3 V to the Sigma-Delta

DACs digital output pads. It is recommended that you use good layout techniques to provide isolation be-

tween the supply types on the board. Contact Cirrus Logic applications engineering for layout guidelines.

Signal Name

PLL_GND

PLL_1V8

Type

Description

Ground for internal PLLs

1

2

1.8V for internal PLLs

14, 40, 73

12, 38, 71

19, 42, 64, 86

16, 44, 75

88

CORE_GND

CORE_1V8

IO_GND

Ground for internal core logic

1.8V for internal core logic

Ground for Digital I/Os

IO_3V3

3.3V for Digital I/Os

DAC_3V3

3.3V for Sigma Delta DAC Digital I/Os

Table 18. Power and Ground

36

DS553PP1

CS7410

DS553PP1

37

CS7410

5. 100-PIN MQFP PACKAGE SPECIFICATIONS (20X14X2.85mm)

±

23.200 0.250

±

20.000 0.100

81

50

31

100

±

0.310 0.050

0.650 0.150

A

°

0~8

±

0.800 0.150

Note: Measurement Units = mm

DETAIL A

±

1.600 0.150

Figure 18. 100-Pin MQFP Package (20x14x2.85mm)

38

DS553PP1

CS7410

6. 100-PIN LQFP PACKAGE SPECIFICATIONS (14X14X1.4mm)

Figure 19. 100-Pin LQFP Package (14X14X1.4mm)

DS553PP1

39

型号:	CS7410-CM
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Active
IHS 制造商：	CIRRUS LOGIC INC
零件包装代码：	QFP
包装说明：	QFP, QFP100,.7X.9
针数：	100
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
风险等级：	5.67
商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0
长度：	20 mm
功能数量：	1
端子数量：	100
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP
封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR
封装形式：	FLATPACK
峰值回流温度（摄氏度）：	225
电源：	1.8,3.3 V
认证状态：	Not Qualified
座面最大高度：	3.3 mm
子类别：	Other Consumer ICs
最大供电电压 (Vsup)：	1.98 V
最小供电电压 (Vsup)：	1.62 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	14 mm
Base Number Matches：	1

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