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产品型号CS8401A-CS的概述

芯片CS8401A-CS的概述 CS8401A-CS是一款由Cirrus Logic公司设计和生产的音频数字接口转换器。该芯片主要用于将数字音频信号从多个接口形式转换为I2S格式,常用于各种音频设备如数字音频播放机、音频处理器及车载音响系统中。CS8401A-CS的设计目标是提供高质量音频信号传输、低延迟以及广泛的兼容性,以适应现代音频设备的需求。 该芯片在音频系统中发挥着重要作用,支持多种数字音频信号格式的转换,包括但不限于PCM(脉冲编码调制)、DSD(直接流数字)及自适应流媒体。它在音频数字化和数字音频传输中的高效率使得其成为音频工程师和设计师所青睐的组件之一。 芯片CS8401A-CS的详细参数 CS8401A-CS的参数较为丰富,以下是其主要技术参数: 1. 电源电压(Vcc): 3.3V±10% 2. 功耗: 最小功耗设计,在待机模式下功耗低于10mW。 3...

产品型号CS8401A-CS的Datasheet PDF文件预览

CS8401A CS8402A  
Semiconductor Corporation  
Digital Audio Interface Transmitter  
Features  
General Description  
The CS8401/2A are monolithic CMOS devices which  
encode and transmit audio data according to the  
AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 interface  
standards. The CS8401/2A accept audio and digital  
data, which is then multiplexed, encoded and driven  
onto a cable. The audio serial port is double buffered  
and capable of supporting a wide variety of formats.  
Monolithic Digital Audio Interface  
Transmitter  
Supports: AES/EBU, IEC 958,  
S/PDIF, & EIAJ CP-340  
Professional and Consumer Formats  
The CS8401A has a configurable internal buffer mem-  
ory, loaded via a parallel port, which may be used to  
buffer channel status, auxiliary data, and/or user data.  
Host Mode and Stand Alone Modes  
Generates CRC Codes and Parity Bits  
The CS8402A multiplexes the channel, user, and valid-  
ity data directly from serial input pins with dedicated  
input pins for the most important channel status bits.  
On-Chip RS422 Line Driver  
Configurable Buffer Memory (CS8401A)  
Transparent Mode Allows Direct  
Connection of CS8402A and CS8412  
or CS8401A and CS8411A  
ORDERING INFORMATION:  
TABLE OF CONTENTS:  
page 30  
page 31  
INT  
MCK  
5
CS8401A  
15  
6
SCK  
Audio  
7
Prescaler  
FSYNC  
Serial Port  
8
SDATA  
20  
17  
TXP  
TXN  
14  
MUX  
RS422 Driver  
CS  
Configurable  
Buffer  
16  
RD/WR  
A4 - A0  
Memory  
5
8
D7- D0  
M2 M1 M0  
MCK  
5
RST  
16  
CS8402A  
22  
23  
21  
6
7
8
SCK  
FSYNC  
SDATA  
Audio  
Serial Port  
20  
17  
TXP  
TXN  
MUX  
RS422 Driver  
10  
11  
9
C
U
V
7
Registers  
15  
CBL  
24  
Dedicated Channel  
Status Bits  
TRNPT  
Crystal Semiconductor Corporation  
P.O. Box 17847, Austin, TX 78760  
(512) 445-7222 FAX: (512) 445-7581  
NOV ’93  
DS60F1  
1
CS8401A CS8402A  
ABSOLUTE MAXIMUM RATINGS (GND = 0V, all voltages with respect to ground.)  
Parameter  
Symbol  
Min  
Max  
Units  
DC Power Supply  
VD+  
6.0  
V
Input Current, Any Pin Except Supply  
Digital Input Voltage  
Note 1  
I
-
±10  
VD+  
125  
150  
mA  
V
in  
V
-0.3  
-55  
-65  
IND  
Ambient Operating Temperature (power applied)  
Storage Temperature  
T
A
°C  
°C  
T
stg  
Notes:  
1. Transient currents of up to 100 mA will not cause SCR latch-up.  
WARNING: Operation at or beyond these limits may result in permanent damage to the device.  
Normal operation is not guaranteed at these extremes.  
RECOMMENDED OPERATING CONDITIONS  
(GND = 0V; all voltages with respect to ground)  
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
DC Voltage  
VD+  
4.5  
5.0  
5.5  
5
V
Supply Current  
Note 2  
I
1.5  
25  
mA  
DD  
Ambient Operating Temperature: CS8401/2A-CP or -CS Note 3  
CS8401/2A-IP or -IS  
T
A
0
70  
85  
°C  
°C  
-40  
Power Consumption  
Notes:  
Note 2  
P
D
7.5  
25  
mW  
2. Drivers open (unloaded). The majority of power is used in the load connected to the drivers.  
3. The ’-CP’ and ’-CS’ parts are specified to operate over 0 to 70 °C but are tested at 25 °C only.  
The ’-IP’ and ’-IS’ parts are tested over the full -40 to 85 °C temperature range.  
DIGITAL CHARACTERISTICS  
(T = 25 °C for suffixes ’CP’ & ’CS’, T = -40 to 85 °C for ’IP’ & ’IS’; VD+ = 5V ± 10%)  
A
A
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
High-Level Input Voltage  
Low-Level Input Voltage  
V
2.0  
V
+0.3  
V
IH  
DD  
V
-0.3  
+0.8  
V
V
IL  
High-Level Output Voltage  
Low-Level Output Voltage  
Input Leakage Current  
(I = 200µA)  
V
V
-1.0  
DD  
O
OH  
(I = 3.2mA)  
O
V
0.4  
10  
V
OL  
I
1.0  
µA  
in  
Master Clock Frequency:  
CS8401A  
CS8402A  
Note 4  
Note 4  
MCK  
22  
MHz  
MHz  
7.1  
Master Clock Duty Cycle  
CS8401/2A  
40  
60  
%
Notes: 4. MCK for the CS8401 must be 128, 192, 256, or 384× the input word rate based on M0 and M1 in control  
register 2. MCK for the CS8402A must be 128× the input word rate, except in Transparent Mode where MCK is  
256x the input word rate.  
Specifications are subject to change without notice.  
2
DS60F1  
CS8401A CS8402A  
DIGITAL CHARACTERISTICS - RS422 DRIVERS  
(TXP, TXN pins only; VD+ = 5V ±10%)  
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
Output High Voltage  
Output Low Voltage  
I
= -30 mA  
= 30 mA  
V
VD+- 0.7 VD+ - 0.4  
0.4  
V
OH  
OH  
I
V
0.7  
V
OL  
OL  
SWITCHING CHARACTERISTICS - CS8401A PARALLEL PORT  
(T = 25 °C for suffixes ’-CP’ and ’-CS’; T = -40 to 85 °C for suffixes ’-IP’ and ’-IS’)  
A
A
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
ADDRESS valid to CS low  
CS high to ADDRESS invalid  
RD/WR valid to CS low  
CS low to RD/WR invalid  
CS low  
t
13.5  
ns  
adcss  
t
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
csadh  
t
10  
35  
35  
32  
0
rwcss  
t
csrwi  
t
csl  
DATA valid to CS rising  
CS high to DATA invalid  
CS falling to DATA valid  
CS rising to DATA Hi-Z  
RD/WR low (writing)  
RD/WR low (writing)  
RD/WR high (reading)  
RD/WR high (reading)  
t
dcssw  
t
csdhw  
t
35  
csddr  
t
5
csdhr  
A4 - A0  
t
t
adcss  
csadh  
CS  
t
csl  
t
t
csrwi  
rwcss  
RD/WR  
Writing  
t
t
csdhw  
dcssw  
D7 - D0  
RD/WR  
t
Reading  
D7 - D0  
t
csddr  
csdhr  
CS8401A Parallel Port Timing  
DS60F1  
3
CS8401A CS8402A  
SWITCHING CHARACTERISTICS - SERIAL PORTS  
(T = 25 °C for suffixes ’-CP’ and ’-CS’; T = -40 to 85 °C for suffixes ’-IP’ and ’-IS’;  
A
A
Inputs: Logic 0 = GND, logic 1 = VD+; C = 20 pF)  
L
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
SCK Frequency  
Master Mode  
Slave Mode  
Notes 5,6  
Note 6  
t
IWR×64  
Hz  
sckf  
12.5  
MHz  
SCK Pulse Width Low  
Slave Mode  
Slave Mode  
Note 6  
Note 6  
t
25  
25  
20  
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
sckl  
SCK Pulse Width High  
t
sckh  
SCK rising to FSYNC edge delay  
SCK rising to FSYNC edge setup  
SDATA valid to SCK rising setup  
SCK rising to SDATA hold time  
Notes 6,7  
Notes 6,7  
Note 7  
t
sfds  
t
sfs  
t
sss  
Note 7  
t
ssh  
C, U, V valid to SCK rising setup CS8402A  
non-CD Mode  
CS8402A  
non-CD mode  
Notes, 7,8  
t
0
ns  
css  
SCK rising to C, U, V hold time  
Notes 7, 8  
t
50  
0
ns  
ns  
ns  
ns  
scs  
U valid to SBC rising setup  
SBC rising to U hold time  
RST Pulse Width  
CS8402A, CD mode Note 8  
CS8402A, CD mode Note 8  
CS8402A  
t
uss  
t
80  
150  
suh  
Notes:  
5. The input word rate, IWR, refers to the frequency at which stereo audio input samples are input to  
the part. (A stereo pair is two audio samples.) Therefore, in Master mode, there are always  
32 SCK periods in one audio sample.  
6. Master mode is defined as SCK and FSYNC being outputs. In Slave mode they are inputs. In the  
CS8401A, control reg. 3 bit 1, MSTR, selects master. In the CS8402A, only format 0 is master.  
7. The table above assumes data is output on the falling edge and latched on the rising edge. In both  
parts the edge is selectable. The table is defined for the CS8401A with control reg. 3 bit 0, SCED, set to  
one, and for the CS8402A in formats 4 through 7. For the other formats, the table and figure edges  
must be reversed (ie. "rising" to "falling" and vice versa).  
8. The diagrams show SBC rising coincident with the first rising edge of SCK after FSYNC transitions.  
This is true for all modes except FSF0 & 1 both equal 1 in the CS8401A, and format 4 in the CS8402A.  
In these modes SBC is delayed one full SCK period.  
FSYNC  
t
sfs  
t
sfds  
t
t
sckh  
sckl  
SCK  
t
t
ssh  
sss  
SDATA  
Serial Input Timing - Slave Mode  
4
DS60F1  
CS8401A CS8402A  
FSYNC  
t
t
sfds  
sfs  
t
sckf  
SCK  
t
t
sss  
ssh  
SDATA  
C,U,V  
CS8402A  
non-CD mode  
t
t
t
css  
uss  
sch  
suh  
U
CD mode  
t
SBC  
Serial Input Timing - Master Mode & C, U, V Port  
External  
Clock  
+5V  
+5V  
5
5 k  
19  
MCK  
VD+  
7
6
8
FSYNC  
SCK  
Audio  
0.1 uF  
Data  
18  
Processor  
GND  
SDATA  
15  
14  
16  
Audio  
INT  
CS8401A  
Data  
Processor  
CS  
RD/WR  
A0 - A4  
20  
17  
or  
TXP  
TXN  
Transmitter  
Circuit  
Micro-  
controller  
See Appendix B  
D0 - D7  
Figure 1. CS8401A Typical Connection Diagram  
DS60F1  
5
CS8401A CS8402A  
External  
Clock  
+5V  
0.1 uF  
5
19  
VD+  
GND  
MCK  
7
6
8
18  
24  
FSYNC  
Audio  
TRNPT  
Data  
Processor  
SCK  
SDATA  
23  
M2  
M1  
M0  
15  
10  
11  
9
22  
21  
Serial Port  
CBL  
Mode Select  
CS8402A  
Micro-  
controller  
C
U
or  
20  
TXP  
TXN  
unused  
V
Transmitter  
Circuit  
See Appendix B  
16  
RST  
17  
Channel  
Status Bits  
Control  
8 Dedicated C.S. Bits  
Figure 2. CS8402A Professional & Consumer Modes Typical Connection Diagram  
External  
Clock  
+5V  
0.1 uF  
5
19  
7
6
8
MCK  
VD+  
FSYNC  
SCK  
Audio  
18  
GND  
Data  
Processor  
SDATA  
9
10  
11  
15  
23  
V
M2  
M1  
M0  
22  
21  
Serial Port  
Decoder  
Subcode  
Port  
SBF  
Mode Select  
CS8402A  
U
SBC  
20  
17  
TXP  
TXN  
16  
Transmitter  
Circuit  
See Appendix B  
Reset  
Control  
RST  
Channel  
Status Bits  
Control  
8 Dedicated C.S. Bits  
Figure 3. Consumer CD Submode Typical Connection Diagram  
6
DS60F1  
CS8401A CS8402A  
CS8401A DESCRIPTION  
GENERAL DESCRIPTION  
The CS8401A/2A are monolithic CMOS circuits  
that encode and transmit audio and digital data  
according to the AES/EBU, IEC 958 (S/PDIF),  
and EIAJ CP-340 interface standards. Both chips  
accept audio and control data separately; multi-  
plex and biphase-mark encode the data  
internally; and drive it, directly or through a  
transformer, to a transmission line. The CS8401A  
is fully software programmable through a paral-  
lel port and contains buffer memory for control  
data, while the CS8402A has dedicated pins for  
the most important control bits and a serial input  
port for the C, U, and V bits.  
The CS8401A accepts 16- to 24-bit audio samples  
through a configurable serial port, and channel status,  
user, and auxiliary data through an 8-bit parallel port.  
The parallel port allows access to 32 bytes of internal  
memory which is used to store control information  
and buffer channel status, user, and auxiliary data.  
This data is multiplexed with the audio data from the  
serial port, the parity bit is generated, and the bit  
stream is biphase-mark encoded and driven through  
an RS422 line driver. A block diagram of the  
CS8401A is shown in Figure 4. In accordance with  
the professional definition of channel status, the  
CRCC code (C.S. byte 23) can be internally gener-  
ated.  
Familiarity with the AES/EBU and IEC 958  
specifications are assumed throughout this data  
sheet. Many terms such as channel status, user  
data, auxiliary data, professional mode, etc. are  
not defined. The Application Note, Overview of  
AES/EBU Digital Audio Interface Data Struc-  
tures, provides an overview of the AES/EBU and  
IEC 958 specifications and is included for clar-  
ity; however, it is not meant to be a complete  
reference, and the complete standards should be  
obtained from the Audio Engineering Society or  
ANSI for the AES/EBU document, and the Inter-  
national Electrotechnical Commission for the  
IEC document.  
Parallel Port  
The parallel port accesses one status register, three  
control registers, and 28 bytes of dual port buffer  
memory. The address bus, and RD/WR line must be  
valid when CS goes low. If RD/WR is low, the value  
on the data bus will be written into the buffer mem-  
ory at the specified address. If RD/WR is high, the  
value in the buffer memory, at the specified address,  
is placed on the data bus. The detailed timing for  
reading and writing the CS8401A can be found in  
the Digital Switching Characteristics table. The  
memory space is allocated as shown in Figure 5.  
There are three defined buffer memory modes select-  
able by two bits in control register 2.  
Line Drivers  
The RS422 line drivers for both the CS8401A  
and CS8402A are low skew, low impedance, dif-  
ferential outputs capable of driving 110  
transmission lines with a 4 volt peak-to-peak sig-  
nal when configured as shown in Appendix A.  
To prevent possible short circuits, both drivers  
are set to ground when no master clock (MCK)  
is provided. They can also be disabled by reset-  
ting the device (RST = low). Appendix A  
contains more information on the line drivers. A  
0.1 µF capacitor, with short leads, should be  
placed as close as possible to the VD+ and GND  
pins.  
Status and Control Registers  
Upon power up the CS8401A control registers  
contain all zeros. Therefore, the part is initially  
in reset and is muted. One’s must be written to  
control register 2, bits RST and MUTE, before  
the part will transmit data. The remaining regis-  
ters are not initialized on power-up and may  
contain random data.  
The first register, shown in Figure 6, is the status  
register in which only three bits are valid. The lower  
three bits contain flags indicating the position of the  
transmit pointer in the buffer memory. These flags  
DS60F1  
7
CS8401A  
8
6
7
SDATA  
SCK  
Audio  
Aux  
Serial  
Port  
Logic  
FSYNC  
20  
Biphase  
Mark  
Encoder  
21-24, 1-4  
9-13  
TXP  
TXN  
Line  
Driver  
D0-D7  
A4-A0  
C Bits  
Mux  
17  
14  
CRC  
CS  
Control  
and Flags  
4 X 8  
16  
RD/WR  
U Bits  
15 Interrupt  
Control  
INT  
Validity  
Preamble  
Parity  
Timing  
Buffer  
Memory  
28 X 8  
Read  
IMCK  
Address  
Generator  
Prescaler  
5
MCK  
Figure 4. CS8401A Block Diagram  
may be used to avoid contention between the  
transmit pointer reading the data and the user up-  
dating the buffer memory. Besides indicating the  
byte location being transmitted, the flags indicate  
the block of memory the part is currently ad-  
dressing, thereby telling the user which block is  
free to be written to. Each flag has a correspond-  
ing mask bit (control register 1) which, when set,  
allows a transition on the flag to generate a pulse  
on the interrupt pin. Flag 0 and flag 1 cause in-  
terrupts on both edges whereas flag 2 causes an  
interrupt only on the rising edge. Timing and  
further explanation of the flags can be found in  
the buffer memory section.  
is set so that three frame delays occur from the  
input of the CS8411 to the output of the  
CS8401A. In Transparent Mode, 32 SCK’s are  
required per subframe.  
Channel status block alignment between the  
CS8411 and the CS8401A is accomplished by  
setting BKST high at the occurrence of the Flag  
2 rising edge of the CS8411. If FSYNC is a  
left/right signal, BKST is sampled once per  
frame; if FSYNC is a word clock, BKST is sam-  
pled once per subframe. A low to high transition  
of BKST (based on two successive internal sam-  
ples) resets the channel status block boundary to  
the beginning.  
The two most significant bits of control register 1,  
BKST and TRNPT, are used for Transparent Mode  
operation of the CS8401A. Transparent Mode is used  
for those applications where it is useful to maintain  
frame alignment between the received and transmitted  
audio data signals. In Transparent Mode  
(TRNPT = "1") the MCK, FSYNC, SCK and  
SDATA inputs of the CS8401A can be connected to  
their corresponding outputs of the CS8411. In Trans-  
parent Mode, FSYNC synchronizes the transmitter  
and the receiver. The data delay through the CS8401A  
Control register 2, shown in Figure 8, contains  
various system level functions. The two most  
significant bits, M1 and M0, select the frequency  
at the MCK pin as shown in Table 1. As an ex-  
ample, if the audio sample frequency is 44.1 kHz  
and M0 and M1 are both zero, MCK would then  
be 128× the audio sample rate or 5.6448 MHz. The  
next bit (5) in control register 2, V, indicates the valid-  
ity of the current audio sample. According to the  
8
DS60F1  
CS8401A  
digital audio specifications, V = 0 signifies the  
audio signal is suitable for conversion to analog.  
B1 and B0 select one of three modes for the  
buffer memory. The different modes are shown  
in Figure 5 and the bit combinations in Table 2.  
More information on the different modes can be  
found in the Buffer Memory section. Bit 2, CRCE, is  
the channel status CRCC enable and should only be  
used in professional mode. When CRCE is high, the  
7
6
5
4
3
2
1
0
FLAG2 FLAG1 FLAG0  
X:00  
FLAG2: High for first four bytes of channel status  
FLAG1: Memory mode dependent - See figure 11  
FLAG0: High for last two bytes of user data.  
Figure 6. Status Register  
7
6
5
4
3
2
1
0
BKST  
TRNPT  
MASK2 MASK1 MASK0  
X:01  
BKST: Causes realignment of data block when set to "1".  
TRNPT: Selects Transparent Mode appropriately setting data  
delay through device  
0
Status register 0  
MASK2: Interrupt mask for FLAG2. A "1" enables the interrupt.  
MASK1: Interrupt mask for FLAG1.  
MASK0: Interrupt mask for FLAG0.  
1
2
Control Register 1  
Control Register 2  
Control Register 3  
3
4
Figure 7. Control Register 1  
5
User Data  
6
7
6
5
4
3
2
1
0
7
U
N
D
E
F
I
N
E
D
M1  
M0  
V
B1  
B0  
CRCE  
MUTE  
RST  
X:02  
8
1st Four  
Bytes of  
Left C. S.  
Data  
1st Four  
Bytes of  
C. S. Data  
1st Four  
Bytes of  
C. S. Data  
9
M1: with M0, selects MCK frequency.  
M0: with M1, selects MCK frequency.  
V: Validity bit of current sample.  
A
B
B1: with B0, selects the buffer memory mode.  
B0: with B1, selects the buffer memory mode.  
C
Left  
C. S.  
Data  
A
D
D
R
E
S
S
D
C. S.  
Data  
CRCE: Channel status CRC Enable. Professional mode only.  
MUTE: When clear, transmitted audio data is set to zero.  
E
Last  
20 Bytes  
Channel  
Status  
F
RST: When clear, drivers are disabled, frame counters cleared.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
1st Four  
Bytes of  
Right  
Figure 8. Control Register 2  
Data  
C. S. Data  
M1  
M0  
MCLK  
Right  
C. S.  
Data  
0
0
1
1
0
1
0
1
128× Input Word Rate  
192× Input Word Rate  
256× Input Word Rate  
384× Input Word Rate  
Auxiliary  
Data  
Table 1. MCLK Frequencies  
B1  
B0  
Mode  
Buffer Memory Contents  
0
0
1
1
0
1
0
1
0
1
2
3
Channel Status  
Auxiliary Data  
Independent Channel Status  
Reserved  
0
1
2
3
Memory Mode  
Figure 5. CS8401A Buffer Memory Modes  
Table 2. Buffer Memory Modes  
DS60F1  
9
CS8401A  
channel status data cyclic redundancy check  
characters are generated independently for chan-  
nels A and B and are transmitted at the end of the  
channel status block. When MUTE (bit 1) is low,  
the transmitted audio data is forced to zero. Both  
RST and MUTE are set to zero upon power up.  
of the formats delineate each channel’s data and  
do not indicate the particular channel. The other  
two formats also indicate the specific channel.  
The formats are shown in Figure 10. Bit 1,  
MSTR, determines whether FSYNC and SCK  
are inputs, MSTR low, or outputs, MSTR high.  
Bit 0, serial clock edge select, SCED, selects the  
edge that audio data gets latched on. When  
SCED is low, the falling edge of SCK latches  
data in the chip and when SCED is high, the ris-  
ing edge is used.  
When RST is low, the differential line drivers are  
set to ground and the block counters are reset to the  
beginning of the first block. In order to properly  
synchronize the rest of the CS8401A to the audio  
serial port, the transmit timing counters, which in-  
clude the flags in the status register, are not enabled  
after RST is set high until eight and one half SCK  
periods after the active edge (first edge after reset is  
exited) of FSYNC.  
The multitude of combinations allow for a zero  
glue logic interface to almost all DSP’s, encoder  
chips, and standard serial data formats.  
Serial Port  
When FSYNC is configured as a left/right signal  
(FSF1 = 1), the counters and flags are not en-  
abled until the right sample is being entered  
(during which the previous left sample is being  
transmitted). This guarantees that channel A is  
left and Channel B is right as per the digital  
audio interface specs.  
The serial port is used to enter audio data and  
consists of three pins: SCK, SDATA, and  
FSYNC. The serial port is double buffered with  
SCK clocking in the data from SDATA, and  
FSYNC delineating audio samples and may de-  
fine the particular channel, left or right.  
Control register 3, shown in Figure 9, configures  
the serial port. All the various formats are illus-  
trated in Figure 10. When FSF1 is low, FSYNC  
only delineates audio samples. When FSF1 is  
high, it delineates audio samples and specifies  
the channel. When FSF1 is low and the port is a  
master (MSTR = 1), FSYNC is a square wave  
output. When FSF1 is low and the port is a slave  
(input), FSYNC can be a square wave or a pulse  
provided the active edge, as defined in Fig-  
ure 10, is properly positioned with respect to  
SDATA.  
Control register 3 contains format information for  
the serial audio input channel. The MSB is unused  
and the next three bits, SDF2-SDF0, select the for-  
mat for the serial input data with respect to  
FSYNC. There are five valid combinations of these  
bits as shown in Figure 10. The next two bits,  
FSF1 and FSF0, select the format of FSYNC. Two  
7
6
5
4
3
2
1
0
SDF2  
SDF1  
SDF0  
FSF1  
FSF0  
MSTR  
SCED  
X:03  
SDF2: with SDF0 & SDF1, select serial data format.  
SDF1: with SDF0 & SDF2, select serial data format.  
SDF0: with SDF1 & SDF2, select serial data format.  
FSF1: with FSF0, select FSYNC format.  
Bits 4, 5, and 6, SDF0-SDF2, define the format  
of SDATA and is also described in Figure 10.  
The five allowable formats are MSB first, MSB  
last, 16-bit LSB last, 18-bit LSB last, and 20-bit  
LSB last. The MSB first and MSB last formats  
accept any word length from 16 to 24 bits. The  
word length is controlled by providing trailing  
zeros in MSB first mode and leading zeros in  
FSF0: with FSF1, select FSYNC format.  
MSTR: When set, SCK and FSYNC are outputs.  
SCED: When set, rising edge of SCK latches data.  
When clear, falling edge of SCK latches data.  
Figure 9. Control Register 3  
10  
DS60F1  
CS8401A  
SDF  
Right Sample  
24 bits, incl. Aux  
Left Sample  
24 bits, incl. Aux  
Name  
210 (bit)  
000  
001  
010  
100  
110  
MSB First  
MSB  
LSB  
MSB  
LSB  
MSB  
MSB  
MSB Last  
MSB  
LSB  
LSB  
LSB  
LSB  
24 bits, incl. Aux  
MSB  
LSB  
LSB  
LSB  
LSB  
24 bits, incl. Aux  
16 Bits  
16 Bits  
LSB Last 16  
LSB Last 18  
LSB Last 20  
MSB  
MSB  
LSB  
18 Bits  
18 Bits  
MSB  
MSB  
LSB  
20 Bits  
20 Bits  
MSB  
MSB  
LSB  
FSF MSTR  
10 (bit)  
00  
01  
10  
11  
0
0
0
0
FSYNC Input  
FSYNC Input  
FSYNC Input  
FSYNC Input  
00  
01  
10  
11  
1
1
1
1
FSYNC Output  
FSYNC Output  
FSYNC Output  
FSYNC Output  
16 Clocks  
16 Clocks  
16 Clocks  
16 Clocks  
32 Clocks  
32 Clocks  
32 Clocks  
32 Clocks  
Figure 10. CS8401A Serial Port SDATA and FSYNC Timing  
MSB last mode, or by restricting the number of  
SCK periods between samples to the sample  
word length. The 16-, 18-, and 20-bit LSB-last  
modes require at least 16, 18, or 20 SCK periods  
per sample respectively. As a master, 32 SCK pe-  
riods are output per sample.  
respectively, and the user data is buffered in lo-  
cations 4-7. The parallel port can access any  
location in the user data buffer at any time; how-  
ever, care must be taken not to modify a location  
when that location is being read internally. This  
internal reading is done through the second port  
of the buffer and is done in a cyclic manner.  
FSYNC must be derived from MCK via a DSP  
using the same clock or by external counters. If  
FSYNC moves (jitters) with respect to MCK by  
more than 4 MCK periods, the CS8401A may  
reset the channel status block and flags. Appen-  
dix C contains more information on the  
relationship of FSYNC and MCK.  
Reset initializes the internal pointer to  
04H (Hex). Data is read from this location and  
stored in an 8-bit shift register which is shifted  
once per audio sample. (An audio sample is de-  
fined as a single channel, not a stereo pair.) The  
byte is transmitted LSB first, D0 being the first  
bit. After transmitting 8 samples, i.e. 8 user bits,  
the address pointer is incremented and the next  
byte of user data is loaded into the shift register.  
After transmitting all four bytes, 32 audio sam-  
Buffer Memory  
In all buffer modes, the status register and con-  
trol registers are located at addresses 0-3  
DS60F1  
11  
CS8401A  
ples, the user read pointer is reset to 04H (Hex)  
and the cycle repeats.  
Flag 1 is mode dependent, changing with buffer  
memory configuration, and is discussed in the  
individual buffer mode sections.  
Flag 0 in the status register monitors the position  
of the internal user data read pointer. When the  
first byte, location 04H, is read, flag 0 is set low  
and when the third byte, location 06H, is read,  
flag 0 is set high. If mask 0 in control register 1  
is set, a transition of flag 0 will generate a low  
pulse on the interrupt pin. The value of flag 0  
indicates which two bytes the part will read next,  
thereby indicating which two bytes are free to be  
updated.  
Flag 2 is set high when byte 0 of the channel  
status, address 08H, is read, and set low when  
byte 4, address 0BH, is read. Therefore, flag 2  
high indicates the part is reading the first four  
bytes of channel status, and the last 20 bytes are  
free to update. If the interrupt mask bit for flag 2  
is set, the rising edge will cause an interrupt in-  
dicating the beginning of a channel status block  
as shown in Figure 11. Although a falling edge  
Block  
(384 Audio Samples)  
Flag 2  
Flag 1  
Mode 0  
Flag 1  
Modes 1 & 2  
Flag 0  
23  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
Channel Status Byte  
0
1
(Expanded)  
Frame  
A 0  
B 0  
A 1  
B 1  
A 2  
B 2  
A 7  
B 7  
(Expanded)  
Sub-frame  
Audio Data  
bit  
0
3
4
Aux Data  
7
8
27 28 29 30 31  
MSB  
Preamble  
LSB  
V
U
C
P
Validity  
User Data  
See figure 15  
Channel Status Data  
Parity Bit  
Figure 11. CS8401A Status Register Flag Timing  
12  
DS60F1  
CS8401A  
on flag 0 and flag 1 may cause an interrupt, the  
falling edge of flag 2 will not.  
reads this buffer in a cyclic non-destructive man-  
ner and stores the byte in an 8-bit shift register  
that is shifted once per two transmitted audio  
samples (once per frame).  
Figure 11 illustrates the flag timing for an entire  
channel status block which includes 24 bytes of  
channel status data and 384 audio samples. (This  
figure assumes the channel status bit is the same  
for the audio pair.) The lower portion of Fig-  
ure 11 expands the first byte of channel status  
showing eight pairs of data with a pair defined  
as a frame. This is further expanded showing the  
first sub-frame (A0) to contain 32 bits as per the  
AES/EBU specifications (see Appendix A).  
When transmitting stereo, channel A is left and  
channel B is right. The preamble at the bottom  
of Figure 11 is expanded in Figure 15 to show  
the exact timing between flags, the interrupt pin,  
and internal buffer-read timing.  
Flag 1 in the status register can be used to moni-  
tor the channel status buffer. In mode 0, flag 1 is  
set low when byte 0, location 08H, is read, and  
set high when byte 16, location 18H, is read. If  
mask 1 in control register 1 is set, a transition on  
flag 1 will generate a pulse on the interrupt pin.  
Figure 12 illustrates the memory read sequence  
for buffer mode 0 along with the flag timing.  
The arrows on the flags indicate an interrupt if  
the appropriate mask bit is set. Flag 0 can cause  
an interrupt on either edge, which is shown only  
in the expanded portion of the Figure for clarity.  
The expanded section also shows that the user  
buffer is reread when location 0AH of the chan-  
nel status is read.  
Buffer Mode 0  
In buffer mode 0, in addition to the user-data  
buffer previously discussed, one entire block of  
channel status data is buffered in 24 memory lo-  
cations from address 08H to 1FH. This block  
will be transmitted in both channel A and chan-  
nel B, one bit per frame. Like the user-data  
buffer, the parallel port can access any location  
in this buffer at any time. The transmitter section  
Buffer Mode 1  
In buffer mode 1, eight bytes are allocated for  
channel status data and 16 bytes for auxiliary  
data as shown in Figure 5. The channel status  
buffer, locations 08H to 0FH, is divided into two  
sections. The first four locations always contain  
the first four bytes of channel status, identical to  
Block  
(384 Audio Samples)  
Flag 2  
Flag 1  
Flag 0  
C.S. Byte  
0
1
2
3
4
5
6
7
8
9
10  
11 12  
13  
14 15 16 17  
18  
19  
20  
21 22 23  
0
1
C.S. Address  
08  
0B 0C  
1F 08  
(Expanded)  
Flag 0  
C.S. Address  
User Address  
08  
04  
09  
06  
0A  
04  
0B  
06  
(Addresses are in Hex)  
05  
07  
05  
07  
Figure 12. CS8401A Buffer Memory Read Sequence - MODE 0  
DS60F1  
13  
CS8401A  
mode 0, and are read once per channel status  
block. The second four locations, addresses 0CH  
to 0FH, provide a cyclic buffer for the last 20  
bytes of channel status data.  
buffer; however, four auxiliary data bits are  
transmitted per audio sample (sub-frame). Since  
the auxiliary buffer must be read four times as  
often as the user data buffer and is four times as  
large, flag 0 can be used to monitor both.  
Similar to mode 0, transmitted channel status  
data will be the same for channel A and chan-  
nel B (one channel status bit per frame). Flag 1  
and flag 2 can be used to monitor this buffer.  
Flag 1 is set low when byte 0 of channel status  
data, location 08H, is read and is toggled when  
every other byte is read. As shown in Figure 13,  
flag 2 is set high when byte 0, location 08H, is  
read and set low when byte 4, location 0CH, is  
read. Flag 2 determines whether the channel  
status pointer is reading the first four-byte sec-  
tion or the second four-byte section, while flag 1  
indicates which two bytes of the section are free  
to update.  
Buffer Mode 2  
In buffer mode 2, two 8-byte buffers are avail-  
able for buffering both channel A and channel B  
channel status data independently. Both buffers  
are identical to the channel status buffer in  
mode 1 except that each channel can have  
unique channel status data. The two buffers are  
read simultaneously with locations 08H to 0FH  
transmitted in channel A and locations 10H to  
17H transmitted in channel B. Figure 5 contains  
the buffer memory modes and Figure 14 illus-  
trates the buffer read sequence for mode 2.  
The auxiliary data buffer, locations 10H to 1FH,  
is read in a cyclic manner similar to the data  
Block  
(384 Audio Samples)  
Flag 2  
Flag 1  
Flag 0  
C.S. Byte  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13 14 15  
16  
17 18 19  
20  
21  
22 23  
0
1
C.S. Address  
08  
0B 0C  
0F 0C  
0F 0C  
0F 0C  
0F 0C  
0F 08  
(Addresses are in Hex)  
(Expanded)  
Flag 1  
Flag 0  
C.S. Address  
08  
09  
0A  
0B  
06  
17 18  
User Address  
Aux. Address  
04  
10  
05  
13,14  
06  
07  
04  
05  
07  
17 18  
1B,1C  
1F 10  
13,14  
1B,1C  
1F  
Figure 13. CS8401A Buffer Memory Read Sequence - MODE 1  
14  
DS60F1  
CS8401A  
Block  
(384 Audio Samples)  
Flag 2  
Flag 1  
Flag 0  
C.S. Byte  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
0
1
Left C.S. Ad.  
08  
0B 0C  
13 14  
0F 0C  
17 14  
0F 0C  
17 14  
0F 0C  
17 14  
0F 0C  
17 14  
0F 08  
Right C.S. Ad.  
10  
14 10  
(Addresses are in Hex)  
(Expanded)  
Flag 1  
Flag 0  
Left C.S. Ad.  
08  
10  
04  
09  
0A  
12  
04  
0B  
13  
06  
Right C.S. Ad.  
User Address  
11  
06  
05  
07  
05  
07  
Figure 14. CS8401A Buffer Memory Read Sequence - MODE 2  
Buffer-Read and Interrupt Timing  
reading of the buffer for transmission. The mas-  
ter clock IMCK is shown as 128×Fs. Other  
MCK frequencies are initially divided to obtain  
128×Fs, defined as IMCK (internal MCK),  
which is then used for all internal timing, so the  
timing in Figure 15 is valid for all MCK fre-  
quencies. When the parity bit (P) is transmitted, a  
transition on a flag causes INT to go low if the  
appropriate mask bit is set. Concurrently, the part  
starts reading from the internal buffer. Writing to  
the buffer ram location being read by the part  
should be avoided while the internal "ram read"  
signal is high.  
As mentioned previously in the buffer mode sec-  
tions, conflicts between externally writing to the  
buffer ram and the CS8401A internally reading  
bytes of ram for transmission may be averted by  
using the flag levels to avoid the section cur-  
rently being addressed by the part. Interrupts  
occur at flag edges indicating the exact byte that  
the part is currently reading. Utilizing INT along  
with the flags, the byte currently being read by the  
part can be avoided allowing access to all other  
bytes instead of just a section. Figure 15 illustrates  
the timing between flags, INT, and the internal  
IMCK (128Fs)  
Flags 0 & 1  
Flag 2  
INT  
RAM Read  
TXP  
C
P
TXN  
Transmit Preamble  
Figure 15. RAM/Buffer-Read and Interrupt Timing  
DS60F1  
15  
CS8401A  
PIN DESCRIPTIONS  
CS8401A  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
DATA BUS BIT 4  
DATA BUS BIT 5  
DATA BUS BIT 6  
DATA BUS BIT 7  
MASTER CLOCK  
D4  
D5  
D6  
D7  
MCK  
SCK  
D3  
D2  
D1  
D0  
TXP  
VD+  
GND  
TXN  
DATA BUS BIT 3  
DATA BUS BIT 2  
DATA BUS BIT 1  
DATA BUS BIT 0  
TRANSMIT POSITIVE  
POWER  
2
3
4
5
6
SERIAL DATA CLOCK  
FRAME SYNC FSYNC  
SERIAL INPUT DATA SDATA  
ADDRESS BUS BIT 4  
ADDRESS BUS BIT 3  
ADDRESS BUS BIT 2  
ADDRESS BUS BIT 1  
7
GROUND  
TRANSMIT NEGATIVE  
8
9
A4  
A3  
A2  
A1  
RD/WR READ/WRITE SELECT  
10  
11  
12  
INT  
CS  
A0  
INTERRUPT  
CHIP SELECT  
ADDRESS BUS BIT 0  
Power Supply Connections  
VD+ - Positive Digital Power, PIN 19.  
Positive supply for the digital section. Nominally +5 volts.  
GND - Ground, PIN 18.  
Ground for the digital section.  
Audio Input Interface  
SCK - Serial Clock, PIN 6.  
Serial clock for SDATA pin which can be configured (via control register 3) as an input or  
output, and can sample data on the rising or falling edge. As an output, SCK will contain 32  
clocks for every audio sample. As an input, it does not need to be continuous and can be up to  
15 MHz.  
FSYNC - Frame Sync, PIN 7.  
Delineates the serial data and may indicate the particular channel, left or right. Also, FSYNC  
may be configured as an input or output. The format is based on bits in control register 3.  
SDATA - Serial Data, PIN 8.  
Audio data serial input pin.  
Parallel Interface  
CS - Chip Select, PIN 14.  
This input is active low and allows access to the 32 bytes of internal memory. The address bus  
and RD/WR must be valid while CS is low.  
16  
DS60F1  
CS8401A  
RD/WR - Read/Write, PIN 16.  
If RD/WR is low when CS goes active (low), the data on the data bus is written to internal  
memory. If RD/WR is high when CS goes active, the data in the internal memory is placed on  
the data bus.  
A4-A0 - Address Bus, PINS 9-13.  
Parallel port address bus that selects the internal memory location to be read from or written to.  
D0-D7 - Data Bus, PINS 21-24, 1-4.  
Parallel port data bus used to check status, write control words, or write internal buffer memory.  
INT - Interrupt, PIN 15.  
Open drain output that can signal the state of the internal buffer memory. A 5kresistor to  
VD+ is typically used to support logic gates. All bits affecting INT are maskable allowing total  
control over the interrupt mechanism.  
Transmitter Interface  
MCK - Master Clock, PIN 5.  
Clock input which defines the transmit timing. It can be configured, via control register 2, for  
128, 192, 256, or 384 times the sample rate.  
TXP, TXN - Differential Line Drivers, PINS 20, 17.  
RS422 compatible line drivers. Drivers are pulled low when part is in reset state.  
DS60F1  
17  
CS8402A  
2
CS8402A DESCRIPTION  
with the I S standard. Formats 5 and 6 make  
the CS8402A look similar to existing 16- and  
18-bit DACs, and interpolation filters. For-  
mat 7 is an MSB-last format and is conducive  
to serial arithmetic. SCK and FSYNC are  
outputs in Format 0 and inputs in all other  
formats. In Format 2, the rising edge of  
FSYNC delineates samples and the falling  
edge must occur a minimum of one bit period  
before or after the rising edge. In all formats  
except 2, FSYNC contains left/right informa-  
tion requiring both edges of FSYNC to  
delineate samples. Formats 5 and 6 require a  
minimum of 16- or 18-bit audio words re-  
spectively. In all formats other than 5 and 6,  
the CS8402A can accept any word length  
from 16 to 24 bits by adding leading zeros in  
format 7 and trailing zeros in the other for-  
mats, or by restricting the number of SCK  
periods between active edges of FSYNC to  
the sample word length.  
The CS8402A accepts 16- to 24-bit audio samples  
through a serial port configured in one of seven for-  
mats; provides several pins dedicated to particular  
channel status bits; and allows all channel status,  
user, and validity bits to be serially input through  
port pins. This data is multiplexed, the parity bit is  
generated, and the bit stream is biphase-mark en-  
coded and driven through an RS422 line driver.  
The CS8402A operates as a professional or con-  
sumer interface transmitter selectable by pin 2,  
PRO. As a professional interface device, the dedi-  
cated channel status input pins are defined according  
to the professional standard, and the CRC code (C.S.  
byte 23) can be internally generated.  
As a consumer device, the dedicated channel  
status input pins are defined according to the  
consumer standard. A submode provided under  
the consumer mode is compact disk, CD, mode.  
When transmitting data from a compact disk, the  
CD subcode port can accept CD subcode data,  
extract channel status information from it, and  
transmit it as user data.  
FSYNC must be derived from MCK, either  
through a DSP using the same clock, or using  
counters. If FSYNC moves (jitters) with respect  
to MCK by four MCK periods, the internal  
counters and CBL may be reset. Appendix B  
contains more information on the relationship  
between FSYNC and MCK.  
The master clock, MCK, controls timing for the en-  
tire chip and must be 128×Fs. As an example, if  
stereo data is input to the CS8402A at 44.1 kHz,  
MCK input must be 128 times that or 5.6448 MHz.  
Audio Serial Port  
The audio serial port is used to enter audio data  
and consist of three pins: SCK, SDATA, and  
FSYNC. SCK clocks in SDATA, which is double  
buffered, while FSYNC delineates the audio sam-  
ples and may indicate the particular channel, left or  
right. To support many different interfaces, M2,  
M1, and M0 select one of seven different formats  
for the serial port. The coding is shown in Table 3  
while the formats are shown in Figure 16. Format 0  
and 1 are designed to interface with Crystal ADCs.  
Format 2 communicates with Motorola and TI  
DSPs. Format 3 is reserved. Format 4 is compatible  
M2  
M1  
M0  
Format  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 - FSYNC & SCK Output  
1 - Left/Right, 16-24 Bits  
2 - Word Sync, 16-24 Bits  
3 - Reserved  
4 - Left/Right, I2S Compatible  
5 - LSB Justified, 16 Bits  
6 - LSB Justified, 18 Bits  
7 - MSB Last, 16-24 Bits  
Table 3. CS8402A Audio Port Modes  
18  
DS60F1  
CS8402A  
FORMAT 0:  
FSYNC (out)  
SCK (out)  
Left  
Right  
Right  
SDATA (in)  
MSB  
LSB  
MSB  
LSB  
MSB  
FORMAT 1:  
FORMAT 2:  
FSYNC (in)  
SCK (in)  
Left  
Left  
SDATA (in)  
MSB  
MSB  
LSB  
LSB  
MSB  
MSB  
LSB  
LSB  
MSB  
MSB  
FSYNC (in)  
SCK (in)  
Right  
SDATA (in)  
FORMAT 3:  
FORMAT 4:  
(RESERVED)  
FSYNC (in)  
SCK (in)  
Left  
Right  
SDATA (in)  
MSB  
LSB  
MSB  
LSB  
MSB  
FORMAT 5:  
FORMAT 6:  
FORMAT 7:  
FSYNC (in)  
SCK (in)  
Left  
Right  
SDATA (in)  
LSB  
LSB  
MSB  
MSB  
LSB  
LSB  
MSB  
MSB  
LSB  
16 Bits  
16 Bits  
18 Bits  
FSYNC (in)  
Left  
Right  
SCK (in)  
SDATA (in)  
MSB  
MSB  
LSB  
18 Bits  
FSYNC (in)  
Left  
Right  
SCK (in)  
SDATA (in)  
LSB  
LSB  
MSB  
Arrows indicate where C, U, and V bits are latched  
Figure 16. CS8402A Audio Serial Port Formats  
DS60F1  
19  
CS8402A  
C, U, V Serial Port  
RST and CBL (TRNPT is low)  
The serial input pins for channel status (C), user  
(U), and validity (V) are sampled during the first  
bit period after the active edge of FSYNC for all  
formats except Format 4, which is sampled dur-  
ing the second bit period (coincident with the  
MSB). In Figure 16, the arrows on SCK indicate  
when the C, U, and V bits are sampled. The C,  
U, and V bits are transmitted with the audio  
sample entered before the FSYNC edge that  
sampled it. The V bit, as defined in the audio  
standards, is set to zero to indicate the audio data  
is suitable for conversion to analog. Therefore,  
when the audio data is errorred, or the data is  
not audio, the V bit should be set high. The  
channel status serial input pin (C) is not avail-  
able in consumer mode when the CD subcode  
port is enabled (FC1 = FC0 = high). Any chan-  
nel status data entered through the channel status  
serial input (C) is logically OR’ed with the data  
entered through the dedicated pins or internally  
generated.  
When RST goes low, the differential line drivers  
are set to ground and the block counters are reset  
to the beginning of the first block. In order to  
properly synchronize the CS8402A to the audio  
serial port, the transmit timing counters, which  
include CBL, are not enabled after RST goes  
high until eight and one half SCK periods after  
the active edge (first edge after reset is exited) of  
FSYNC. When FSYNC is configured as a  
left/right signal (all defined formats except 2),  
the counters and CBL are not enabled until the  
right sample is being entered (during which the  
previous left sample is being transmitted). This  
guarantees that channel A is left and channel B  
is right as per the digital audio interface specs.  
As shown in Figure 17, CBL, channel block start  
output, can assist in serially inputting the C, U  
and V bits as CBL goes high one bit period be-  
fore the first bit of the preamble of the first  
sub-frame of the channel status block is trans-  
TRNPT high  
CBL  
TRNPT low  
SDATA  
FSYNC  
Left 0  
Right 0  
Left 1  
Left 128  
Right 128  
Left 0  
Right 0  
C bits from Cpin  
CUV0R  
CUV1R  
CUV1L  
TRNPT high  
C,U,V  
CUV0L  
CUVIL  
CUV128R  
CUV128L  
CUV0L  
CUV0R  
CUV0L  
TRNPT low  
CUV191R  
CUV0L  
CUV0R  
CUV191R  
C bits OR'ed w/  
PRO pin  
C bit OR'ed w/  
C1 pin  
Bit 0 of C.S.  
Block Byte 16  
TXP  
TXN  
Right 191  
Left 0  
Right 0  
Left 128  
Right 128  
VUCP191R  
Preamble Y  
VUCP0L  
Preamble Z  
VUCP0R  
Preamble Y  
VUCP127R  
VUCP128L  
Preamble X  
Preamble Y  
bit  
0
3
4
7
8
27 28 29 30 31  
MSB V0 U0 C0 P0  
Preamble Z  
Aux Data  
LSB  
Left 0 - Audio Data  
Sub-frame  
Figure 17. CBL and Transmitter Timing  
20  
DS60F1  
CS8402A  
mitted. This sub-frame contains channel status  
byte 0, bit 0. CBL returns low one bit period be-  
fore the start of the frame that contains bit 0 of  
channel status byte 16. CBL is the exact inverse  
of flag 1 in mode 0 on the CS8401 (see Fig-  
ure 11). CBL is not available when the CD  
subcode port is enabled.  
Transparent Mode  
In certain applications it is desirable to receive  
digital audio data with the CS8412 and retrans-  
mit it with the CS8402A. In this case, channel  
status, user and validity information must pass  
through unaltered. For studio environments, AES  
recommends that signal timing synchronization  
be maintained throughout the studio. Frame syn-  
chronization of digital audio signals input to and  
output from a piece of equipment must be within  
±5%.  
Figure 17 illustrates timing for stereo data input  
on the audio port. Notice how CBL rises while  
the right channel data (Right 0) is input, but the  
previous left channel data (Left 0) is being trans-  
mitted as the first sub-frame of the channel  
status block (starting with preamble Z). The C,  
U, and V input ports only need to be valid for a  
short period after FSYNC changes. A sub-frame  
includes one audio sample while a frame in-  
cludes a stereo pair. A channel status (C.S.)  
block contains 24 bytes of channel status and  
384 audio samples (or 192 stereo pairs, or  
frames, of samples).  
The transparent mode of the CS8402A is se-  
lected by setting TRNPT, pin 24, high. In this  
mode, the CBL pin becomes an input, allowing  
direct connection of the outputs of the CS8412  
to the inputs of the CS8402A as shown in Fig-  
ure 18. The transmitter and receiver are  
synchronized by the FSYNC signal. CBL speci-  
fies the start of a new channel status block  
boundary, allowing the transmit block structure  
to be slaved to the block structure of the re-  
ceiver. In the transparent mode, C, U, and V are  
now transmitted with the current audio sample as  
shown in Figure 17 (TRNPT high), and the dedi-  
cated channel status pins are ignored. When in  
the transparent mode, the propagation delay of  
data through the CS8402A is set so that the total  
propagation delay from the receive inputs of the  
CS8412 to the transmit outputs of the CS8402A  
is three frames.  
Figure 17 shows the CUV ports as having left  
and right bits (e.g. CUV0L, CUV0R). Since the  
C.S. block is defined as 192 bits, or one bit per  
frame, there are actually 2 C.S. blocks, one for  
channel A (left) and one for channel B (right).  
When inputting stereo audio data, both blocks  
normally contain the same information, so C0L  
and C0R from the input port pin are both chan-  
nel status bit 0 of byte 0, which is defined as  
professional/consumer. These first two bits from  
the port, C0L and C0R, are logically OR’ed with  
the inverse of PRO, since PRO is a dedicated  
channel status pin defined as C.S. bit 0. Also, if  
in professional mode, C1, C6, C7 and C9 are  
dedicated C.S. pins. The inverse of C1 is logi-  
cally OR’ed with channel status input port bits  
C1L and C1R. In similar fashion, C6, C7 and C9  
are OR’ed with their respective input bits. Also,  
the C bits in CUV128L and CUV128R are both  
channel status block bit 128, which is bit 0 of  
channel status byte 16.  
V+  
MCK  
CBL  
TRNPT  
C
U
RXP  
RXN  
TXP  
TXN  
V
FSYNC  
SCK  
SDATA  
CS8412  
CS8402A  
Data  
Processing  
Figure 18. Transparent Mode Interface  
DS60F1  
21  
CS8402A  
When FSYNC is a word clock (Format 2), CBL  
is sampled when left C,U,V are sampled. When  
FSYNC is Left/Right, CBL is sampled when left  
C,U,V are sampled. The channel status block  
boundary is reset when CBL transitions from  
low to high (based on two successive samples of  
CBL). MCK for the CS8402A is normally ex-  
pected to be 128 times the sample frequency, in  
the transparent mode MCK must be 256 Fs.  
shown in Table 4. The dedicated channel status  
pins are read at the appropriate time and are  
logically OR’ed with data input on the channel  
status port, C. In Transparent Mode, these dedi-  
cated channel status pins are ignored; and  
channel status bits are input at the C pin.  
The channel status data cyclic redundancy check  
character (C.S. byte 23) is always generated in-  
dependently for channels A and B and is  
transmitted at the end of the channel status  
block.  
Professional Mode  
Setting PRO low places the CS8402A in profes-  
sional mode as shown in Figure 19. In  
professional mode, channel status bit 0 is trans-  
mitted as a one and bits 1, 2, 3, 4, 6, 7, and 9  
can be controlled via dedicated pins. The pins  
are actually the inverse of the identified bit. For  
example, tying the C1 pin low places a one in  
channel status bit 1. As shown in the Application  
Note, Overview of AES/EBU Digital Audio In-  
terface Data Structures, C1 indicates  
audio/non-audio; C6 and C7 determine the sam-  
ple frequency; and C9 allows the encoded  
channel mode to be stereophonic. EM1 and EM0  
determine emphasis and encode C2, C3, C4 as  
Data should not be input through the channel status  
port, C, during the CRCC byte time frame, since in-  
puts on C are logically OR’ed with internally  
generated data.  
Consumer Mode  
Setting PRO high places the CS8402A in consumer  
mode which redefines the pins as shown in Fig-  
ure 20. In consumer mode, channel status bit 0 is  
transmitted as a zero and channel status bits 2, 3, 8,  
9, 15, 24, and 25 are controlled via dedicated pins.  
The pins are actually the inverse of the bit so if pin  
M2 M1 M0  
23 22 21  
8
SDATA  
Audio  
Serial  
Port  
6
SCK  
Aux  
Logic  
7
FSYNC  
20  
Biphase  
Mark  
Encoder  
TXP  
Line  
Driver  
C Bits  
Mux  
TXN  
RST  
10  
11  
9
17  
16  
C
U
CRC  
U Bits  
Registers  
Validity  
Preamble  
Parity  
V
Timing  
TRNPT  
24  
2
14 13  
3
4
1
12  
15  
5
CBL MCK  
PRO  
EM0 EM1 C1 C6 C7 C9  
Figure 19. CS8402A Block Diagram - Professional Mode  
22  
DS60F1  
CS8402A  
C2 is tied high, channel status bit 2 will be trans-  
mitted as a zero. Also, FC0 and FC1 are encoded  
versions of channel status bits 24 and 25, which  
define the sample frequency. When FC0 and FC1  
are both high, the part is placed in a CD sub-  
mode which activates the CD subcode port. This  
submode is described in detail in the next sec-  
tion. Table 5 describes the encoding of C24 and  
C25 through the FC1 and FC0 pins. According  
to AES/EBU standards, C2 is copy prohibit/per-  
mit, C3 specifies pre-emphasis, C8 and C9  
define the category code, and C15 identifies the  
generation status of the transmitted material (i.e..  
first generation, second generation).  
setting both FC1 and FC0 high. This mode rede-  
fines some of the pins for a CD subcode port as  
shown in Figure 21. The CD subcode port pins,  
SBF and SBC, replace the C and CBL pins respec-  
tively. The user data input, U, becomes the CD  
subcode input. Figure 22 describes the timing for  
the CD subcode port. When SBF is low, SBC be-  
comes active, clocking in the subcode bits. SBF  
goes high for one SCK period, one half SCK pe-  
riod after the active edge of FSYNC for all formats  
(except format 4, which will be one and a half  
SCK periods after the active edge of FSYNC). SBF  
high for more than 16 SBC periods indicates the  
start of a subcode block. The first, third, and fourth  
Q bits after the start of a subcode block become  
channel status bits 5, 2, and 3 respectively. Chan-  
nel status bits are set by the dedicated pins; the  
category code is forced to CD.  
Consumer - CD Submode  
The consumer CD submode is invoked by plac-  
ing the part in consumer mode (PRO = high) and  
EM1  
EM0  
C2  
C3  
C4  
FC1  
FC0  
C24  
C25  
Comments  
44.1 kHz  
0
0
1
1
0
1
0
1
1
1
1
0
1
1
0
0
1
0
0
0
0
0
1
1
0
1
0
1
0
0
1
0
0
1
1
0
48.0 kHz  
32.0 kHz  
44.1 kHz, CD Mode  
Table 4. Emphasis Encoding  
M2 M1 M0  
Table 5. Sample Frequency Encoding  
23 22 21  
8
6
7
SDATA  
SCK  
Audio  
Serial  
Port  
Aux  
Logic  
FSYNC  
20  
17  
Biphase  
Mark  
Encoder  
TXP  
TXN  
Line  
Driver  
C Bits  
10  
11  
9
Mux  
C
U
V
Registers  
U Bits  
Validity  
Preamble  
Parity  
16  
Timing  
RST  
+5V  
2
3
24  
4
1
13 14 12  
15  
5
CBL MCK  
PRO FC0 FC1 C2 C3 C8 C9 C15  
Figure 20. CS8402A Block Diagram - Consumer Mode  
DS60F1  
23  
CS8402A  
M2 M1 M0  
23 22 21  
Audio  
Aux  
8
6
7
SDATA  
SCK  
Serial  
Port  
20  
Logic  
FSYNC  
Biphase  
Mark  
Encoder  
TXP  
Line  
Driver  
C Bits  
Mux  
TXN  
10  
11  
Subcode  
Port  
SBF  
U
17  
16  
15  
SBC  
U Bits  
Validity  
Preamble  
Parity  
Register  
9
Timing  
RST  
V
+5V  
2
3
24  
4
1
13 14 12  
5
MCK  
PRO FC0 FC1  
C2 C3 C8 C9 C15  
Figure 21. CS8402A Block Diagram - Consumer Mode, CD Submode  
SBF  
U
SBC  
(Expanded)  
Data latched on rising edge  
SBF  
U
P
Q
R
S
T
U
V
W
SBC  
Figure 22. CD Subcode Port Timing  
24  
DS60F1  
CS8402A  
PIN DESCRIPTIONS  
CS8402A  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CS BIT 7 / CS BIT 3  
C7/C3  
PRO  
C1/FC0  
C6/C2  
MCK  
TRNPT/FC1 TRANSPARENT / FREQ. CTRL 1  
2
PROFESSIONAL MODE  
CS BIT 1 / FREQ. CTRL. 0  
CS BIT 6 / CS BIT 2  
M2  
M1  
M0  
TXP  
VD+  
GND  
TXN  
RST  
SERIAL PORT MODE SELECT 2  
SERIAL PORT MODE SELECT 1  
SERIAL PORT MODE SELECT 0  
TRANSMIT POSITIVE  
POWER  
GROUND  
TRANSMIT NEGATIVE  
MASTER RESET  
3
4
5
MASTER CLOCK  
SERIAL DATA CLOCK  
FRAME SYNC FSYNC  
SERIAL INPUT DATA SDATA  
6
SCK  
7
8
9
VALIDITY INPUT  
CS SERIAL IN / SC FRAME CLOCK  
USER DATA INPUT  
V
C/SBF  
U
10  
11  
12  
CBL/SBC CS BLOCK OUT / SC BIT CLOCK  
EM0/C9  
EM1/C8  
EMPHASIS 0 / CS BIT 9  
EMPHASIS 1 / CS BIT 8  
CS BIT 9 / CS BIT 15 C9/C15  
Power Supply Connections  
VD+ - Positive Digital Power, PIN 19.  
Positive supply for the digital section. Nominally +5 volts.  
GND - Ground, PIN 18.  
Ground for the digital section.  
Audio Input Interface  
SCK - Serial Clock, PIN 6.  
Serial clock for SDATA pin which can be configured (via the M0, M1, and M2 pins) as an  
input or output, and can sample data on the rising or falling edge. As an output, SCK will  
contain 32 clocks for every audio sample. As an input, it does not need to be continuous and  
can be up to 15 MHz.  
FSYNC - Frame Sync, PIN 7.  
Delineates the serial data and may indicate the particular channel, left or right, and may be an  
input or output. The format is based on M0, M1, and M2 pins.  
SDATA - Serial Data, PIN 8.  
Audio data serial input pin.  
M0, M1, M2 - Serial Port Mode Select, PINS 21, 22, 23.  
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA.  
Control Pins  
RST - Master Reset, PIN 16.  
When low, all internal counters are reset and the line drivers are disabled, pulling low.  
DS60F1  
25  
CS8402A  
V - Validity, PIN 9.  
Validity bit serial input port. This bit is defined according to the digital audio standards wherein  
V = 0 signifies the audio signal is suitable for conversion to analog. V = 1 signifies the audio  
signal is not suitable for conversion to analog, i.e. invalid. V is sampled once per subframe  
U - User Bit, PIN 11.  
User bit serial input port is sampled once per subframe.  
PRO - Professional/Consumer Select, PIN 2.  
Selects between professional mode (PRO low) and consumer mode (PRO high). This pin  
defines the functionality of the next seven pins. PRO must be low for Transparent Mode, but  
will have no effect on the channel status bits.  
C9/C15 - Channel Status Bit 9 / Channel Status Bit 15, PIN 12.  
In professional mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). In consumer  
mode, C15 is the inverse of channel status bit 15 (bit 7 of byte 1). C9/C15 are ignored in  
Transparent Mode.  
EM0/C9 - Emphasis 0 / Channel Status Bit 9, PIN 14.  
In professional mode, EM0 and EM1 encode channel status bits 2, 3, and 4. In consumer mode,  
C9 is the inverse of channel status bit 9 (bit 1 or byte 1). EMO/C9 are ignored in Transparent  
Mode.  
EM1/C8 - Emphasis 1 / Channel Status Bit 8, PIN 13.  
In professional mode, EM0 and EM1 encode channel status bits 2, 3, and 4. In consumer mode,  
C8 is the inverse of channel status bit 8 (bit 0 of byte 1). EM1/C8 are ignored in Transparent  
Mode.  
C7/C3 - Channel Status Bit 7 / Channel Status Bit 3, PIN 1.  
In professional mode, C7 is the inverse of channel status bit 7. In consumer mode, C3 is the  
inverse of channel status bit 3. C7/C3 are ignored in Transparent Mode.  
C6/C2 - Channel Status Bit 6 / Channel Status Bit 2, PIN 4.  
In professional mode, C6 is the inverse of channel status bit 6. In consumer mode, C2 is the  
inverse of channel status bit 2. C6/C2 are ignored in Transparent Mode.  
C1/FC0 - Channel Status Bit 1 / Frequency Control 0, PIN 3.  
In professional mode, C1 is the inverse of channel status bit 1. In consumer mode, FC0 and  
FC1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When FC0  
and FC1 are both high, CD mode is selected. C1/FC0 are ignored in Transparent Mode.  
26  
DS60F1  
CS8402A  
TRNPT/FC1 - Transparent Mode / Frequency Control 1, PIN 24.  
In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting  
TRNPT high, allows the CS8402A to be connected directly to a CS8412. In transparent mode,  
CBL is an input & MCK must be at 256 Fs.  
In consumer mode, FC0 and FC1 are encoded versions of channel status bits 24 and 25. When  
FC0 and FC1 are both high, CD mode is selected.  
C/SBF - Channel Status Serial Input / Subcode Frame Clock, PIN 10.  
In professional and consumer modes this pin is the channel status serial input port. In CD mode  
this pin inputs the CD subcode frame clock.  
CBL/SBC - Channel Status Block Output / Subcode Bit Clock, PIN 15.  
In professional and consumer modes, the channel status block output is high for the first 16  
bytes of channel status. In CD mode, this pin outputs the subcode bit clock.  
Transmitter Interface  
MCK - Master Clock, PIN 5.  
Clock input at 128× Fs the sample frequency which defines the transmit timing. In transparent  
mode, MCK must be 256× Fs.  
TXP, TXN - Differential Line Drivers, PINS 20, 17.  
RS422 compatible line drivers. Drivers are pulled to low when part is in reset state.  
DS60F1  
27  
CS8401A CS8402A  
Appendix A: RS422 Driver Information  
CS8401/2A  
TXP  
The RS422 drivers on the CS8401A and CS8402A  
are designed to drive both the professional and con-  
sumer interfaces. The AES/EBU specification for  
professional/broadcast use calls for a 110source  
impedance and a balanced drive capability. Since the  
transmitter impedance is very low, a 110resistor  
should be placed in series with one of the transmit  
pins. (A 110resistor in parallel with the trans-  
former would, with the receiver impedance of 110,  
provide a 55load to the part which is too low.)  
The specifications call for a balanced output drive of  
2-7 volts peak-to-peak into a 110load with no ca-  
ble attached. Using the circuit in Figure A1, the  
output of the transformer is short-circuit protected,  
has the proper source impedance, and provides a  
5 volt peak-to-peak signal into a 110load. Lastly,  
the two output pins should be attached to an XLR  
connector with male pins and a female shell, and  
with pin 1 of the connector grounded.  
TTL or  
CMOS Gate  
TXN  
Figure A3. TTL/CMOS Output Circuit  
shown in Figure A2 only uses the TXP pin and  
provides the proper output impedance and drive  
level using standard 1% resistors. The connector  
for consumer would be an RCA phono socket.  
This circuit is also short circuit protected.  
The TXP pin may be used to drive TTL or  
CMOS gates as shown in Figure A3. This circuit  
may be used for optical connectors for digital  
audio since they are usually TTL compatible.  
This circuit is also useful when driving multiple  
digital audio outputs since RS422 line drivers  
have TTL interfaces.  
The transformer should be capable of operating  
from 1.5 to 7 MHz, which is the audio data rate  
of 25 kHz to 55 kHz after biphase-mark encod-  
ing. Transformers provide isolation from ground  
loops, 60 Hz noise, and common mode noise  
and interference. One of the important considera-  
tions when choosing transformers is minimizing  
shunt capacitance between primary and secon-  
dary windings. The higher the shunt capacitance,  
the lower the isolation between primary and sec-  
ondary, and the more coupling of high frequency  
energy. This energy appears in the form of com-  
mon mode noise on the receive side ground and  
has the potential to degrade analog performance.  
Therefore, for best performance, shielded trans-  
formers optimized for minimum shunt  
capacitance should be used. The following are a  
few typical transformers:  
CS8401/2A  
110  
TXP  
XLR  
TXN  
1
Figure A1. Professional Output Circuit  
In the case of consumer use, the specifications  
call for an unbalanced drive circuit with an out-  
put impedance of 75and a output drive level  
of 0.5 volts peak-to-peak ±20% when measured  
across a 75load using no cable. The circuit  
CS8401/2A  
374  
TXP  
RCA  
Phono  
90.9  
Pulse Engineering  
Telecom Products Group  
7250 Convoy Ct.  
TXN  
San Diego, CA 92111  
Figure A2. Consumer Output Circuit  
28  
DS60F1  
CS8401A CS8402A  
(619) 268-2400  
Part Number: PE65612  
All internal timing is derived from MCK. On the  
CS8402A, MCK is always 128×Fs. On the  
CS8401A, the external MCK is programmable  
and is initially divided to 128×Fs before being  
used by the part. The internal clock IMCK used  
in the following discussion is always 128×Fs re-  
gardless of the external MCK pin.  
Schott Corporation  
1000 Parkers Lane Rd.  
Wayzata, MN 55391  
(612) 475-1173  
FAX (612) 475-1786  
Part Number:  
After RST, the CS8401A and CS8402A syn-  
chronize the internal timing to the audio data  
port, more specifically FSYNC, to guarantee that  
channel A is left channel data and channel B is  
right channel data as per the AES/EBU specifica-  
tion. If FSYNC moves with respect to IMCK,  
the transmitter could lose synchronization, which  
causes an internal reset.  
67125450 - compatible with Pulse  
67128990 - lower cost  
67129000 - surface mount  
67129600 - single shield  
Scientific Conversions Inc.  
42 Truman Drive  
Novato, CA. 94947  
(415) 8922323  
Figure B1 shows the structure of the serial port  
input, to the transmitter output. The audio data is  
serially shifted into R1. PLD is an internal signal  
that parallel loads R1 into the R2 buffer, and, at  
the same time, the C, U, and V bits are latched.  
On the CS8401A, the C, U, and V bits are held  
in RAM, whereas on the CS8402A, they are  
latched from external pins. The PLD signal rises  
on the first SCK edge that can latch data. This is  
coincident with the latching of the MSB of audio  
data in MSB-first, left-justified modes. PLD  
stays high for one SCK period. In the CS8402A  
section, the arrows on SCK in Figure 16 indicate  
when PLD goes high. Also, SBC in the  
CS8402A CD submode is an external version of  
PLD gated by the SBF input.  
Part Number:  
SC916-01 - single shield  
SC916-02 - surface mount  
Appendix B: MCK and FSYNC Relationship  
FSYNC should be derived either directly or indi-  
rectly from MCK. The indirect case could be a  
DSP, providing FSYNC through its serial port,  
using the same master oscillator that generates  
MCK. In either case, FSYNC’s relationship to  
MCK is fixed and does not move. Since this ap-  
pendix provides information on what would  
happen if FSYNC did move with respect to  
MCK, it does not apply to the majority of users.  
SDATA  
R1 - Shift (in) Register  
SCK  
PLD (load signal)  
+V  
internally generated  
P C U V R2 - Audio Buffer  
D
Internal Reset  
Q
CS8402A C,U,V Port  
CS8401A Internal  
Memory  
LDS (load signal)  
IMCK  
2
R3 - Shift (out) Register  
TXP  
TXN  
Biphase  
Encode  
Dri-  
ver  
Mux  
Preamble  
Figure B1. Serial Port-to-Transmitter Block Diagram  
DS60F1  
29  
CS8401A CS8402A  
9.5  
8.5  
SCK  
FSYNC  
SDATA  
CS8402A C,U, V  
PLD  
Left 0  
Right 0  
CUV0L  
CUV191R  
IMCK  
LDS  
TXP  
TXN  
Left 191  
V U C P  
191L Preamb.  
Right 191  
V U C P  
Left 0  
191R Preamb.  
CS8401A Flags  
CS8402A CBL  
Figure B2. Serial Ports-to-Transmitter Timing (slave mode)  
When the part is finished transmitting the pream-  
ble of a sub-frame, the internal signal LDS rises  
to parallel-load R2 into R3 for transmission. Af-  
ter RST, the part synchronizes the audio port to  
IMCK as shown in Figure B2. Since PLD is  
based on FSYNC and LDS is based on IMCK, if  
FSYNC moves with respect to IMCK until PLD  
and LDS occur at the same time, the data would  
not be properly loaded into R3. If LDS and PLD  
overlap, an internal reset is initiated causing the  
timing to return to the initial state shown in Fig-  
ure B2.  
Ordering Guide  
Model  
Temperature Range  
Package  
CS8401A-CP  
CS8401A-IP  
CS8401A-CS  
CS8401A-IS  
0 to 70 °C*  
-40 to 85 °C  
0 to 70 °C*  
-40 to 85 °C  
24-Pin Plastic .3" DIP  
24-Pin Plastic .3" DIP  
24-Pin Plastic SOIC  
24-Pin Plastic SOIC  
CS8402A-CP  
CS8402A-IP  
CS8402A-CS  
CS8402A-IS  
0 to 70 °C*  
-40 to 85 °C  
0 to 70 °C*  
-40 to 85 °C  
24-Pin Plastic .3" DIP  
24-Pin Plastic .3" DIP  
24-Pin Plastic SOIC  
24-Pin Plastic SOIC  
* Although the ’-CP’ and ’-CS’ suffixed parts are guaranteed to operate over 0 to 70 °C, they are  
tested at 25 °C only. If testing over temperature is desired, the ’-IP’ and ’-IS’ suffixed parts are  
tested over their specified temperature range.  
30  
DS60F1  
MILLIMETERS  
DIM MIN NOM MAX  
INCHES  
MIN NOM  
MAX  
0.180  
0.040  
0.022  
24 pin  
Plastic  
Skinny DIP  
A
3.94 4.32 4.57  
0.155 0.170  
24  
1
13  
12  
E1  
A1 0.51 0.76 1.02 0.020 0.030  
B
B1  
C
0.36 0.46 0.56  
0.014 0.018  
1.02 1.27 1.65  
0.040 0.050 0.065  
0.015  
0.20 0.25 0.38  
0.008 0.010  
D
1.265  
D
31.37 31.75 32.13  
1.235 1.250  
0.260  
0.105  
0.325  
0.150  
15°  
E1  
e1  
eA  
6.10 6.35 6.60 0.240 0.250  
A
SEATING  
PLANE  
2.67  
2.41 2.54  
0.095 0.100  
C
eA  
L
A1  
7.62  
3.18  
0°  
-
-
-
8.25 0.300  
-
-
-
e1  
L
3.81  
15°  
B1  
0.125  
0°  
B
NOTES:  
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN  
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN  
RELATION TO SEATING PLANE AND EACH OTHER.  
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.  
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.  
INCHES  
MILLIMETERS  
pins  
MIN  
MIN NOM MAX  
NOM MAX  
16  
20  
24  
28  
9.91  
0.390  
0.490  
0.590  
0.690  
10.16 10.41  
0.400 0.410  
0.500 0.510  
0.600 0.610  
0.700 0.710  
12.45  
12.70 12.95  
14.99  
17.53  
15.24 15.50  
17.78 18.03  
D
MILLIMETERS  
MIN NOM MAX MIN  
INCHES  
NOM MAX  
DIM  
SOIC  
A
A
2.54 2.67  
0.095  
2.41  
0.127  
2.29  
0.100 0.105  
E
E
1
-
0.300 0.005  
-
0.012  
1
A
2.41 2.54 0.090 0.095 0.100  
2
b
0.33 0.46 0.51  
0.013 0.018 0.020  
c
D
E
E
0.280 0.381  
0.203  
0.008  
0.011 0.015  
see table above  
10.11 10.41 10.67 0.398  
0.410 0.420  
0.292 0.295 0.298  
0.040 0.050 0.055  
7.42 7.49 7.57  
1.14 1.27 1.40  
1
A
A
e
2
A
µ
c
0.41  
0°  
L
µ
0.89 0.016  
-
-
-
-
0.035  
8°  
L
1
0°  
8°  
b
e
• Notes •  
Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation  
配单直通车
CS8401A-CS产品参数
型号:CS8401A-CS
是否Rohs认证: 不符合
生命周期:Obsolete
包装说明:PLASTIC, SOIC-24
Reach Compliance Code:unknown
风险等级:5.7
商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PDSO-G24
JESD-609代码:e0
功能数量:1
端子数量:24
最高工作温度:70 °C
最低工作温度:
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP24,.3
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V
认证状态:Not Qualified
子类别:Other Consumer ICs
最大压摆率:5 mA
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1
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