CS8416-CZZR应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

CS8416

192 kHz Digital Audio Interface Receiver

32 kHz to 192 kHz Sample Frequency Range

Features

Low-Jitter Clock Recovery

Complete EIAJ CP1201, IEC-60958, AES3,

S/PDIF-Compatible Receiver

Pin and Microcontroller Read Access to

+3.3 V Analog Supply (VA)

Channel Status and User Data

+3.3 V Digital Supply (VD)

SPI™ or I²C^®Control Port Software Mode and

Stand-Alone Hardware Mode

+3.3 V or +5.0 V Digital Interface Supply (VL)

8:2 S/PDIF Input MUX

Differential Cable Receiver

AES/SPDIF Input Pins Selectable in Hardware

On-Chip Channel Status Data Buffer Memories

Mode

Auto-Detection of Compressed Audio Input

Three General Purpose Outputs (GPO) Allow

Streams

Signal Routing

Decodes CD Q Sub-Code

OMCK System Clock Mode

Selectable Signal Routing to GPO Pins

S/PDIF-to-TX Inputs Selectable in Hardware

Mode

See the General Description and Ordering Information

on page 2.

Flexible 3-wire Serial Digital Output Port

VA

VD

VL DGND

OMCK

AGND FILT RMCK

De-emphasis

RXN

Filter

Receiver

OLRCK

OSCLK

SDOUT

Clock &

Data

AES3

Serial

Audio

Output

C & U bit

Data Buffer

S/PDIF

RXP0

RXP1

RXP2

RXP3

RXP4

RXP5

RXP6

RXP7

Recovery Decoder

TX Passthrough

8:2

MUX

GPO0

GPO1

AD2/GPO2

Control

n:3

MUX

Port &

Format

Detect

Misc.

Control

Registers

RST

SDA/

SCL/ AD1/ AD0/

CDOUT CCLK CDIN CS

AUGUST '07

DS578F3

http://www.cirrus.com

CS8416

General Description

The CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio data

according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial digital

audio output port and comprehensive control ability through a selectable control port in Software Mode or through

selectable pins in Hardware Mode. Channel status data are assembled in buffers, making read access easy. GPO

pins may be assigned to route a variety of signals to output pins.

A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream.

Stand-alone operation allows systems with no microcontroller to operate the CS8416 with dedicated output pins for

channel status data.

The CS8416 is available in 28-pin TSSOP, SOIC, and QFN packages in Commercial grade (-10° to +70° C) and

Automotive grade (-40° to +85° C). The CDB8416 Customer Demonstration board is also available for device eval-

uation and implementation suggestions. Please refer to “Ordering Information” on page 59 for complete ordering

information.

Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, ef-

fects processors, set-top boxes, and computer and automotive audio systems.

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CS8416

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6

SPECIFIED OPERATING CONDITIONS ............................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6

DC ELECTRICAL CHARACTERISTICS................................................................................................. 7

DIGITAL INPUT CHARACTERISTICS ................................................................................................... 7

DIGITAL INTERFACE SPECIFICATIONS.............................................................................................. 7

SWITCHING CHARACTERISTICS ........................................................................................................ 8

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS............................................................... 9

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE.................................................. 10

SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT ............................................... 11

2. PIN DESCRIPTION - SOFTWARE MODE .......................................................................................... 12

2.1 TSSOP Pin Description ................................................................................................................. 12

2.2 QFN Pin Description ...................................................................................................................... 14

3. PIN DESCRIPTION - HARDWARE MODE ......................................................................................... 16

3.1 TSSOP Pin Description ................................................................................................................. 16

3.2 QFN Pin Description ...................................................................................................................... 18

4. TYPICAL CONNECTION DIAGRAMS ................................................................................................ 20

5. APPLICATIONS .................................................................................................................................. 22

5.1 Reset, Power-Down and Start-Up ................................................................................................. 22

5.2 ID Code and Revision Code .......................................................................................................... 22

5.3 Power Supply, Grounding, and PCB Layout ................................................................................. 22

6. GENERAL DESCRIPTION .................................................................................................................. 23

6.1 AES3 and S/PDIF Standards Documents ..................................................................................... 23

7. SERIAL AUDIO OUTPUT PORT ......................................................................................................... 23

7.1 Slip/Repeat Behavior ..................................................................................................................... 25

7.2 AES11 Behavior ............................................................................................................................ 26

8. S/PDIF RECEIVER .............................................................................................................................. 27

8.1 8:2 S/PDIF Input Multiplexer ......................................................................................................... 27

8.1.1 General ............................................................................................................................... 27

8.1.2 Software Mode ................................................................................................................... 27

8.1.3 Hardware Mode .................................................................................................................. 28

8.2 OMCK System Clock Mode ........................................................................................................... 28

8.3 Clock Recovery and PLL Filter ...................................................................................................... 28

9. GENERAL PURPOSE OUTPUTS ....................................................................................................... 29

10. ERROR AND STATUS REPORTING ................................................................................................ 30

10.1 General ........................................................................................................................................ 30

10.1.1 Software Mode ................................................................................................................. 30

10.1.2 Hardware Mode ................................................................................................................ 30

10.2 Non-Audio Detection ................................................................................................................... 31

10.2.1 Format Detection .............................................................................................................. 31

10.3 Interrupts ..................................................................................................................................... 31

11. CHANNEL STATUS AND USER-DATA HANDLING ....................................................................... 32

11.1 Software Mode ............................................................................................................................ 32

11.2 Hardware Mode ........................................................................................................................... 32

12. CONTROL PORT DESCRIPTION ..................................................................................................... 33

12.1 SPI Mode ..................................................................................................................................... 33

12.2 I²C Mode ...................................................................................................................................... 34

13. CONTROL PORT REGISTER QUICK REFERENCE ....................................................................... 35

14. CONTROL PORT REGISTER DESCRIPTIONS .............................................................................. 36

14.1 Memory Address Pointer (MAP) .................................................................................................. 36

14.2 Control0 (00h) ............................................................................................................................. 36

14.3 Control1 (01h) ............................................................................................................................. 37

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CS8416

14.4 Control2 (02h) ............................................................................................................................. 38

14.5 Control3 (03h) ............................................................................................................................. 39

14.6 Control4 (04h) ............................................................................................................................. 39

14.7 Serial Audio Data Format (05h) ................................................................................................... 40

14.8 Receiver Error Mask (06h) ......................................................................................................... 41

14.9 Interrupt Mask (07h) .................................................................................................................... 41

14.10 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h) ......................................................... 41

14.11 Receiver Channel Status (0Ah) ................................................................................................ 42

14.12 Format Detect Status (0Bh) ....................................................................................................... 42

14.13 Receiver Error (0Ch) ................................................................................................................ 43

14.14 Interrupt 1 Status (0Dh) ............................................................................................................ 44

14.15 Q-Channel Subcode (0Eh - 17h) ............................................................................................... 44

14.16 OMCK/RMCK Ratio (18h) ....................................................................................................... 45

14.17 Channel Status Registers (19h - 22h) ....................................................................................... 45

14.18 IEC61937 PC/PD Burst Preamble (23h - 26h) .......................................................................... 45

14.19 CS8416 I.D. and Version Register (7Fh) ................................................................................... 45

15. HARDWARE MODE .......................................................................................................................... 46

15.1 Serial Audio Port Formats ........................................................................................................... 46

15.2 Hardware Mode Function Selection ............................................................................................ 46

15.3 Hardware Mode Equivalent Register Settings ............................................................................. 47

16. EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ................................................... 49

16.1 AES3 Receiver External Components ........................................................................................ 49

16.2 Isolating Transformer Requirements ........................................................................................... 49

17. CHANNEL STATUS BUFFER MANAGEMENT ............................................................................... 51

17.1 AES3 Channel Status (C) Bit Management ................................................................................ 51

17.2 Accessing the E Buffer ................................................................................................................ 51

17.2.1 Serial Copy Management System (SCMS) ...................................................................... 51

18. PLL FILTER ....................................................................................................................................... 53

18.1 General ........................................................................................................................................ 53

18.2 External Filter Components ......................................................................................................... 53

18.2.1 General ............................................................................................................................. 53

18.2.2 Capacitor Selection .......................................................................................................... 54

18.2.3 Circuit Board Layout ......................................................................................................... 54

18.2.4 Component Value Selection ............................................................................................. 54

18.2.5 Jitter Attenuation ............................................................................................................... 55

19. PACKAGE DIMENSIONS ................................................................................................................. 56

TSSOP THERMAL CHARACTERISTICS............................................................................................. 57

QFN THERMAL CHARACTERISTICS ................................................................................................. 58

20. ORDERING INFORMATION ............................................................................................................. 59

21. REVISION HISTORY ......................................................................................................................... 60

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CS8416

LIST OF FIGURES

Figure 1. Audio Port Master Mode Timing ................................................................................................... 9

Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 9

Figure 3. SPI Mode Timing ........................................................................................................................ 10

Figure 4. I²C Mode Timing ......................................................................................................................... 11

Figure 5. Typical Connection Diagram - Software Mode ........................................................................... 20

Figure 6. Typical Connection Diagram - Hardware Mode.......................................................................... 21

Figure 7. Serial Audio Output Example Formats........................................................................................ 24

Figure 8. AES3 Data Format...................................................................................................................... 25

Figure 9. Receiver Input Structure ............................................................................................................. 27

Figure 10. C/U Data Outputs...................................................................................................................... 32

Figure 11. Control Port Timing in SPI Mode .............................................................................................. 33

Figure 12. Control Port Timing, I²C Slave Mode Write............................................................................... 34

Figure 13. Control Port Timing, I²C Slave Mode Read............................................................................... 34

Figure 14. De-Emphasis Filter Response .................................................................................................. 39

Figure 15. Hardware Mode Data Flow ....................................................................................................... 46

Figure 16. Professional Input Circuit.......................................................................................................... 49

Figure 17. Transformerless Professional Input Circuit............................................................................... 49

Figure 18. Consumer Input Circuit ............................................................................................................. 50

Figure 19. S/PDIF MUX Input Circuit ......................................................................................................... 50

Figure 20. TTL/CMOS Input Circuit............................................................................................................ 50

Figure 21. Channel Status Data Buffer Structure....................................................................................... 52

Figure 22. Flowchart for Reading the E Buffer........................................................................................... 52

Figure 23. PLL Block Diagram ................................................................................................................... 53

Figure 24. Recommended Layout Example............................................................................................... 54

Figure 25. Jitter Attenuation Characteristics of PLL................................................................................... 55

LIST OF TABLES

Table 1. Typical Delays by Frequency Values........................................................................................... 26

Table 2. Clock Switching Output Clock Rates............................................................................................ 28

Table 3. GPO Pin Configurations............................................................................................................... 29

Table 4. Hardware Mode Start-Up Pin Conditions..................................................................................... 47

Table 5. Hardware Mode Serial Audio Format Select................................................................................ 48

Table 6. External PLL Component Values................................................................................................. 54

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CS8416

1. CHARACTERISTICS AND SPECIFICATIONS

All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical

performance characteristics and specifications are derived from measurements taken at nominal supply voltages

and T_A= 25°C.

SPECIFIED OPERATING CONDITIONS

(AGND, DGND = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Typ

Max

Units

VA

VD

VL

3.13

3.3

3.3 or 5.0

3.46

5.25

V

Power Supply Voltage

Ambient Operating Temperature:

Commercial Grade

Automotive Grade

-10

-40

-

+70

+85

T_A

°C

ABSOLUTE MAXIMUM RATINGS

(AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent dam-

age to the device. Normal operation is not guaranteed at these extremes.)

Parameter

Symbol

Min

-

Max

6.0

Units

V

Power Supply Voltage

VA, VD,VL

Input Current, Any Pin Except Supplies

Input Voltage

(Note 1)

I_in

V_in

T_A

-

±10

mA

V

-0.3

-55

-65

(VL) + 0.3

125

Ambient Operating Temperature (power applied)

Storage Temperature

°C

T_stg

150

°C

Notes:

1. Transient currents of up to 100 mA will not cause SCR latch-up.

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DS578F3

CS8416

DC ELECTRICAL CHARACTERISTICS

(AGND = DGND = 0 V; all voltages with respect to 0 V.)

Parameters

Symbol

Min

Typ

Max

Units

Power-Down Mode (Notes 2, 4)

Supply Current in power-down

VA

VD

VL = 3.3 V

VL = 5.0 V

IA

ID

IL

-

10

70

10

12

-

μA

Normal Operation (Notes 3, 4)

Supply Current at 48 kHz frame rate

VA

VD

VL = 3.3 V

VL = 5.0 V

IA

ID

IL

-

5.7

5.9

2.8

4.2

-

mA

Supply Current at 192 kHz frame rate

VA

VD

VL = 3.3 V

VL = 5.0 V

IA

ID

IL

-

9.4

23

7.8

11.8

-

mA

Notes:

2. Power-Down Mode is defined as RST = LO with all clocks and data lines held static.

3. Normal operation is defined as RST = HI.

4. Assumes that no inputs are floating. It is recommended that all inputs be driven high or low at all times.

DIGITAL INPUT CHARACTERISTICS

(AGND = DGND = 0 V; all voltages with respect to 0 V.)

Parameters

Symbol

I_IN

Min

Typ

Max

±0.5

200

1.0

Units

μA

mVpp

V

Input Leakage Current

-

150

-

Differential Input Sensitivity, RXP[7:0] to RXN

Input Hysteresis

V_TH

V_H

0.15

DIGITAL INTERFACE SPECIFICATIONS

(AGND = DGND = 0 V; all voltages with respect to 0 V.)

Parameters

Symbol

Min

Max

Units

High-Level Output Voltage (I_OH= -3.2 mA)

V_OH

V_OL

(VL) - 1.0

-

V

Low-Level Output Voltage (I_OL= 3.2 mA)

0.5

V

High-Level Input Voltage, except RXP[7:0], RXN

Low-Level Input Voltage, except RXP[7:0], RXN

V_IH

V_IL

2.0

(VL) + 0.3

0.8

V

-0.3

DS578F3

7

CS8416

SWITCHING CHARACTERISTICS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; C_L= 20 pF)

Parameter

Symbol

Min

200

30

-

Typ

Max

Units

μS

RST Pin Low Pulse Width

-

200

-

PLL Clock Recovery Sample Rate Range

kHz

RMCK Output Jitter

(Note 5)

200

ps RMS

RMCK Output Duty-Cycle

(Note 6)

(Note 7)

45

50

55

65

%

RMCK/OMCK Maximum Frequency

-

50

MHz

Notes:

5. Typical RMS cycle-to-cycle jitter.

6. Duty cycle when clock is recovered from biphase encoded input.

7. Duty cycle when OMCK is switched over for output on RMCK.

8

DS578F3

CS8416

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; C_L= 20 pF)

Parameter

OSCLK/OLRCK Active Edge to SDOUT Output Valid

Master Mode

Symbol

Min

Typ

Max

Units

(Note 8)

t_dpd

-

23

ns

RMCK to OSCLK active edge delay

RMCK to OLRCK delay

(Note 8)

(Note 9)

t_smd

t_lmd

0

-

12

-

ns

%

OSCLK and OLRCK Duty Cycle

Slave Mode

50

OSCLK Period

t_sckw

t_sckl

36

14

10

-

ns

OSCLK Input Low Width

OSCLK Input High Width

t_sckh

t_lrckd

t_lrcks

OSCLK Active Edge to OLRCK Edge

(Notes 8,9,10)

OSCLK Edge Setup Before OSCLK Active-Edge (Notes 8,9,11)

Notes:

8. In Software Mode the active edges of OSCLK are programmable.

9. In Software Mode the polarity of OLRCK is programmable.

10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK

has changed.

11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.

OSCLK

(output)

OLRCK

(input)

t

sckh

t

lrckd

lrcks

sckl

OLRCK

(output)

OSCLK

(input)

t

sckw

smd

t

lmd

t

dpd

RMCK

(output)

SDOUT

Figure 1. Audio Port Master Mode Timing

Figure 2. Audio Port Slave Mode and Data Input

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9

CS8416

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(Inputs: Logic 0 = 0 V, Logic 1 = VL; C_L= 20 pF)

Parameter

Symbol

Min

Max

Unit

CCLK Clock Frequency

(Note 12)

f_sck

0

6.0

MHz

CS High Time Between Transmissions

t_csh

1.0

-

µs

CS Falling to CCLK Edge

CCLK Low Time

t_css

t_scl

t_sch

t_dsu

t_dh

t_pd

t_r1

20

66

40

15

-

ns

CCLK High Time

-

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

CCLK Falling to CDOUT Stable

Rise Time of CDOUT

-

(Note 13)

-

50

25

100

-

Fall Time of CDOUT

t_f1

-

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

(Note 14)

t_r2

-

t_r2

-

Notes:

12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dic-

tated by the timing requirements necessary to access the Channel Status memory. Access to the con-

trol register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is

32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions.

13. Data must be held for sufficient time to bridge the transition time of CCLK.

14. For f_sck<1 MHz.

CS

t

scl

sch

t

csh

css

CCLK

CDIN

t

r2

f2

t

dsu

t

dh

t

pd

CDOUT

Figure 3. SPI Mode Timing

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CS8416

SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT

(Inputs: Logic 0 = 0 V, Logic 1 = VL; C_L= 20 pF)

Parameter

Symbol

f_scl

Min

-

Max

Unit

kHz

µs

SCL Clock Frequency

100

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low time

t_buf

4.7

4.0

4.7

4.0

4.7

10

250

-

t_hdst

t_low

t_high

t_sust

t_hdd

t_sud

t_r

-

µs

-

µs

Clock High Time

-

µs

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling

SDA Setup time to SCL Rising

Rise Time of SCL and SDA

-

µs

(Note 15)

-

ns

1000

300

-

ns

Fall Time SCL and SDA

t_f

-

ns

Setup Time for Stop Condition

t_susp

4.7

µs

Notes:

15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Repeated

Stop

Start

Stop

Start

SDA

SCL

t

buf

t

high

hdst

f

susp

hdst

t

sust

sud

r

hdd

low

Figure 4. I²C Mode Timing

DS578F3

11

CS8416

2. PIN DESCRIPTION - SOFTWARE MODE

2.1

TSSOP Pin Description

RXP3

RXP2

RXP1

RXP0

RXN

OLRCK

OSCLK

SDOUT

OMCK

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

2

3

4

RMCK

5

VA

VD

6

AGND

FILT

DGND

7

VL

8

RST

GPO0

9

RXP4

RXP5

RXP6

RXP7

AD0 / CS

GPO1

10

11

12

13

14

AD2 / GPO2

SDA / CDOUT

SCL / CCLK

AD1 / CDIN

Top-Down View

28-pin SOIC/TSSOP

Package

Pin #

Pin Description

Name

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise

as possible since noise on this pin will directly affect the jitter performance of the recovered clock

VA

6

VD

VL

23

21

Digital Power (Input) – Digital core power supply. Nominally +3.3 V

Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-

nected to a common ground area under the chip.

AGND

DGND

7

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected

to a common ground area under the chip.

22

Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.

On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable

in frequency and phase.

RST

FILT

9

8

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on

page 53 for more information on the PLL and the external components.

RXP0

RXP1

RXP2

RXP3

RXP4

RXP5

RXP6

RXP7

4

3

2

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or

S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select

line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-

ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec-

ommended input circuits.

1

10

11

12

13

12

DS578F3

CS8416

Pin #

Pin Description

Name

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or

S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In single-

ended operation this should be AC coupled to ground through a capacitor. See “External

AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.

RXN

5

System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the

Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock.

OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System

Clock Mode” section on page 28

OMCK

RMCK

25

24

Input Section Recovered Master Clock (Output) - Input section recovered master clock output from

the PLL. Frequency defaults to 256x the sample rate (F_s) and may be set to 128x through the RMCKF bit

in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4

register (04h).

OSCLK

OLRCK

27

28

Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL

through a 47 kΩ resistor to place the part in Software Mode.

SDOUT

26

17

Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data

line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out-

put data from the control port interface on the CS8416. See the “Control Port Description” section on

page 33.

SDA /

CDOUT

Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and

out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the

“Control Port Description” section on page 33.

SCL /

CCLK

16

14

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416

into SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is

a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8416. See the

“Control Port Description” section on page 33.

AD0 / CS

Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In

SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description”

section on page 33.

AD1 /

CDIN

15

18

General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low

through a 47 kΩ resistor. See the “Control Port Description” section on page 33 and “General Purpose

Outputs” on page 29 for GPO functions.

AD2 /

GPO2

GPO1

GPO0

19

20

General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.

General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.

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CS8416

2.2

QFN Pin Description

28

27

26

25

24

23

22

RMCK

RXP0

21

20

19

18

17

16

15

1

2

3

4

5

6

7

VD

RXN

VA

DGND

VL

AGND

FILT

Thermal Pad

GPO0

GPO1

AD2 / GPO2

RST

Top-Down View

28-pin QFN Package

RXP4

8

9

10

12

13

14

11

Pin #

Pin Description

Name

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise

as possible since noise on this pin will directly affect the jitter performance of the recovered clock

VA

3

VD

VL

20

18

Digital Power (Input) – Digital core power supply. Nominally +3.3 V

Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-

nected to a common ground area under the chip.

AGND

DGND

4

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected

to a common ground area under the chip.

19

Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.

On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable

in frequency and phase.

RST

FILT

6

5

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on

page 53 for more information on the PLL and the external components.

14

DS578F3

CS8416

Pin #

Pin Description

Name

RXP0

RXP1

RXP2

RXP3

RXP4

RXP5

RXP6

RXP7

1

28

27

26

7

8

9

10

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or

S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select

line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-

ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec-

ommended input circuits.

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or

S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In single-

ended operation this should be AC coupled to ground through a capacitor. See “External

AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.

RXN

2

System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the

Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock.

OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System

Clock Mode” section on page 28

OMCK

RMCK

22

21

Input Section Recovered Master Clock (Output) - Input section recovered master clock output from

the PLL. Frequency defaults to 256x the sample rate (F_s) and may be set to 128x through the RMCKF bit

in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4

register (04h).

OSCLK

OLRCK

24

25

Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL

through a 47 kΩ resistor to place the part in Software Mode.

SDOUT

23

14

Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data

line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out-

put data from the control port interface on the CS8416. See the “Control Port Description” section on

page 33.

SDA /

CDOUT

Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and

out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the

“Control Port Description” section on page 33.

SCL /

CCLK

13

11

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416

into SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is

a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8416. See the

“Control Port Description” section on page 33.

AD0 / CS

Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In

SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description”

section on page 33.

AD1 /

CDIN

12

15

General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low

through a 47 kΩ resistor. See the “Control Port Description” section on page 33 and “General Purpose

Outputs” on page 29 for GPO functions.

AD2 /

GPO2

GPO1

GPO0

16

17

General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.

General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.

THERMAL

PAD

-

Thermal Pad - Thermal relief pad for optimized heat dissipation.

DS578F3

15

CS8416

3. PIN DESCRIPTION - HARDWARE MODE

3.1

TSSOP Pin Description

RXP3

RXP2

OLRCK

OSCLK

SDOUT

OMCK

RMCK

VD

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

2

RXP1

3

RXP0

4

RXN

5

VA

6

AGND

FILT

DGND

VL

7

8

RST

TX

9

RXSEL1

RXSEL0

TXSEL1

TXSEL0

NV / RERR

C

10

11

12

13

14

U

Top-Down View

28-pin SOIC/TSSOP

Package

RCBL

96KHZ

AUDIO

Pin Name

Pin #

Pin Description

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little

VA

6

noise as possible since noise on this pin will directly affect the jitter performance of the recovered

clock

VD

VL

23

21

Digital Power (Input) – Digital core power supply. Nominally +3.3 V

Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be

connected to a common ground area under the chip.

AGND

DGND

7

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-

nected to a common ground area under the chip.

22

Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are

reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks

are stable in frequency and phase.

RST

FILT

9

8

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog

ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter”

on page 53 for more information on the PLL and the external components.

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or

S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The

select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left

floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49

for recommended input circuits.

RXP0

RXP1

RXP2

RXP3

4

3

2

1

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or

S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single-

ended operation this should be AC coupled to ground through a capacitor. See “External

AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.

RXN

5

16

DS578F3

CS8416

Pin Name

Pin #

Pin Description

System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on

OMCK after reset. When enabled, the clock signal input on this pin is automatically output through

RMCK on PLL unlock. See “OMCK System Clock Mode” on page 28.

OMCK

25

Input Section Recovered Master Clock (Output) - Input section recovered master clock output

from the PLL. Frequency is 256x the sample rate (F_s) when the U pin is pulled down by a 47 kΩ

resistor to DGND. Frequency is 128x the sample rate (F_s) when the U pin is pulled up by a 47 kΩ

resistor to VL.

RMCK

24

OSCLK

OLRCK

27

28

Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to

DGND through a 47 kΩ resistor to place the part in Hardware Mode.

SDOUT

26

RXSEL1

RXSEL0

10

11

Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input.

TXSEL1

TXSEL0

12

13

TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out-

put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.

S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered

before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase

detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the

unused receiver inputs.

TX

20

Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected

by a 47 kΩ resistor to DGND. RERR is selected by a 47 kΩ resistor to VL.

NV/RERR

AUDIO

14

15

Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See

“Non-Audio Detection” on page 31. This pin is also used to select the serial port format (SFSEL1) at

reset.

96 kHz Sample Rate Detect (Output) - If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a

“1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate. Also used to set the

Emphasis Audio Match feature at reset.

96KHZ

RCBL

16

17

Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block.

RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then

returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set

the serial audio port to master or slave at reset.

Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the

rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset.

C

U

19

18

User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling

edges of OLRCK. Also used to select the frequency of RMCK to either 256*F_sor 128*F_sat reset.

DS578F3

17

CS8416

3.2

QFN Pin Description

28

27

26

25

24

23

22

RMCK

RXP0

21

20

19

18

17

16

15

1

2

3

4

5

6

7

VD

RXN

VA

DGND

AGND

FILT

Thermal Pad

VL

TX

C

RST

Top-Down View

28-pin QFN Package

U

RXSEL1

8

9

10

12

13

14

11

Pin Name

Pin #

Pin Description

Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little

VA

3

noise as possible since noise on this pin will directly affect the jitter performance of the recovered

clock

VD

VL

20

18

Digital Power (Input) – Digital core power supply. Nominally +3.3 V

Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be

connected to a common ground area under the chip.

AGND

DGND

4

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-

nected to a common ground area under the chip.

19

Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are

reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks

are stable in frequency and phase.

RST

FILT

6

5

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog

ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter”

on page 53 for more information on the PLL and the external components.

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or

S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The

select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left

floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49

for recommended input circuits.

RXP0

RXP1

RXP2

RXP3

1

28

27

26

18

DS578F3

CS8416

Pin Name

Pin #

Pin Description

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or

S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single-

ended operation this should be AC coupled to ground through a capacitor. See “External

AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.

RXN

2

System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on

OMCK after reset. When enabled, the clock signal input on this pin is automatically output through

RMCK on PLL unlock. See “OMCK System Clock Mode” on page 28.

OMCK

RMCK

22

21

Input Section Recovered Master Clock (Output) - Input section recovered master clock output

from the PLL. Frequency is 256x the sample rate (F_s) when the U pin is pulled down by a 47 kΩ

resistor to DGND. Frequency is 128x the sample rate (F_s) when the U pin is pulled up by a 47 kΩ

resistor to VL.

OSCLK

OLRCK

24

25

Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to

DGND through a 47 kΩ resistor to place the part in Hardware Mode.

SDOUT

23

RXSEL1

RXSEL0

7

8

Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input.

TXSEL1

TXSEL0

9

10

TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out-

put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.

S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered

before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase

detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the

unused receiver inputs.

TX

17

Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected

by a 47 kΩ resistor to DGND. RERR is selected by a 47 kΩ resistor to VL.

NV/RERR

AUDIO

11

12

Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See

“Non-Audio Detection” on page 31. This pin is also used to select the serial port format (SFSEL1) at

reset.

96 kHz Sample Rate Detect (Output) - If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a

“1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate. Also used to set the

Emphasis Audio Match feature at reset.

96KHZ

RCBL

13

14

Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block.

RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then

returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set

the serial audio port to master or slave at reset.

Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the

rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset.

C

U

16

15

-

User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling

edges of OLRCK. Also used to select the frequency of RMCK to either 256*F_sor 128*F_sat reset.

THERMAL

PAD

Thermal Pad - Thermal relief pad for optimized heat dissipation.

DS578F3

19

CS8416

4. TYPICAL CONNECTION DIAGRAMS

*

Ferrite

Bead

+3.3 V

Analog

Supply

+3.3 V or +5 V

*

10μF 0.1μF

0.1μF

47kΩ

VA VD

VL

SDOUT

OLRCK

OSCLK

Serial Audio

RXN

Input

Device

RXP0

RXP1

CS8416

RXP2

RXP3

RXP4

RXP5

RXP6

RXP7

AES3 /

S/PDIF

Sources

**

RMCK

OMCK

Clock Control

Clock Source

VL

GPO0

GPO1

AD2/GPO2

AD0 / CS

External

Interface

AD1 / CDIN

SCL / CCLK

SDA / CDOUT

RST

Microcontroller

AGND

FILT

DGND

R_FLT

C_FLT

C_RIP

***

* A separate analog supply is only necessary in applications where RMCK is used for a jitter sensitive task. For

applications where RMCK is not used for a jitter sensitive task, connect VA to VD via a ferrite bead. Keep decou-

pling capacitors between VA and AGND.

** See “S/PDIF Receiver” on page 27 and “External AES3/SPDIF/IEC60958 Receiver Components” on page 49

for typical input configurations and recommended input circuits.

*** For best jitter performance, connect the filter ground directly to the AGND pin. See Table 6 on page 54 for PLL

filter values.

Figure 5. Typical Connection Diagram - Software Mode

20

DS578F3

CS8416

**

Ferrite

Bead

+3.3 V

Analog

Supply

+3.3 V or +5 V

**

10μF

0.1μF

VD

VA

VL

OLRCK

OSCLK

SDOUT

RXN

Serial Audio

Input Device

RXP0

RXP1

RXP2

RXP3

RST

AES3 /

S/PDIF

Sources

***

CS8416

47k Ω

VL

RXSEL0

RXSEL1

TXSEL0

TXSEL1

NV/RERR

RMCK

OMCK

Clock Control

Clock Source

Hardware

Control

*

AUDIO

96KHZ

External

Interface

*

TX

RCBL

*

U

C

AGND

FILT

DGND

C_RIP

R_FLT

C_FLT

****

* These pins must be pulled high to VL or low to DGND through a 47 kΩ resistor.

** A separate analog supply is only necessary in applications where RMCK is used for a jitter sensitive task. For

applications where RMCK is not used for a jitter sensitive task, connect VA to VD via a ferrite bead. Keep decou-

pling capacitors between VA and AGND.

*** See “S/PDIF Receiver” on page 27 and “External AES3/SPDIF/IEC60958 Receiver Components” on page 49

for typical input configurations and recommended input circuits.

**** For best jitter performance connect the filter ground directly to the AGND pin. See Table 6 on page 54 for PLL

filter values.

Figure 6. Typical Connection Diagram - Hardware Mode

DS578F3

21

CS8416

5. APPLICATIONS

5.1

Reset, Power-Down and Start-Up

When RST is low, the CS8416 enters a low power mode and all internal states are reset, including the con-

trol port and registers, and the outputs are muted. In Software Mode, when RST is high, the control port

becomes operational, and the desired settings should be loaded into the control registers. Writing a 1 to the

RUN bit will then cause the part to leave the low power state and begin operation. After the PLL has settled,

the serial audio outputs will be enabled.

Some options within the CS8416 are controlled by a start-up mechanism. During the reset state, some of

the pins are reconfigured internally to be inputs. Immediately upon exiting the reset state, the level of these

pins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to be used to

set alternative modes in the CS8416 by connecting a 47 kΩ resistor to between the pin and either VL (HI)

or DGND (LO). For each mode, every start-up option select pin MUST have an external pull-up or pull-down

resistor as there are no internal pull-up or pull-down resistors for these startup conditions (except for TX,

which has an internal pull-down). In Software Mode, the only start-up option pins are GPO2, which are used

to set a chip address bit for the control port in I²C Mode, and SDOUT, which selects between Hardware and

Software Modes. The Hardware Mode uses many start-up options, which are detailed in Section 15.2 “Hard-

ware Mode Function Selection” on page 46.

5.2

ID Code and Revision Code

The CS8416 has a register that contains a 4-bit code to indicate that the addressed device is a CS8416.

This is useful when other CS84XX family members are resident in the same system, allowing common soft-

ware modules.

The CS8416 4-bit revision code is also available. This allows the software driver for the CS8416 to identify

which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future

revisions, it is strongly recommend that the revision code is read into a variable area within the microcon-

troller, and used wherever appropriate as revision details become known.

5.3

Power Supply, Grounding, and PCB Layout

For most applications, the CS8416 can be operated from a single +3.3 V supply, following normal supply

decoupling practices (See Figures 5 and 6). For applications where the recovered input clock, output on the

RMCK pin, is required to be low jitter, then use a separate, quiet, analog +3.3 V supply for VA, decoupled

to AGND. Make certain that no digital traces are routed near VA, AGND, or FILT as noise may couple and

degrade performance. These pins should be well isolated from switching signals and other noise sources.

VL sets the level for the digital inputs and outputs, as well as the AES/SPDIF receiver inputs.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling

capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as

the CS8416 to minimize inductance effects, and all decoupling capacitors should be as close to the CS8416

as possible. See “PLL Filter” on page 53 for layout recommendations for the PLL.

22

DS578F3

CS8416

6. GENERAL DESCRIPTION

The CS8416 is a monolithic CMOS device that receives and decodes audio data according to the AES3, IEC60958,

S/PDIF, and EIAJ CP1201 interface standards.

The CS8416 provides an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to

be routed to an output of the CS8416. Input data can be either differential or single-ended. A low jitter clock is re-

covered from the incoming data using a PLL. The decoded audio data is output through a configurable, 3-wire serial

audio output port. The channel status and Q-channel subcode portion of the user data are assembled in registers

and may be accessed through an SPI or I²C port.

Three General Purpose Output (GPO) pins are provided to allow a variety of signals to be accessed under software

control. In Hardware Mode, dedicated pins are used to select audio stream inputs for decoding and transmission to

a dedicated TX pin. Hardware Mode also provides channel status and user data output pins.

Figures 5 and 6 show the power supply and external connections to the CS8416 when configured for Software Mode

and Hardware Mode. Please note that all I/O pins, including RXN and RXP[7:0], operate at the VL voltage.

6.1

AES3 and S/PDIF Standards Documents

This document assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to

have current copies of the AES3, IEC60958, and IEC61937 specifications on hand for easy reference.

The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org or at

www.ansi.org. Obtain a copy of the latest IEC60958/61937 standard from ANSI or from the International

Electrotechnical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is available from the

Japanese Electronics Bureau.

Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tutorial on digital

audio specifications, but it should not be considered a substitute for the standards.

The paper An Understanding and Implementation of the SCMS Serial Copy Management System for

Digital Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from the

AES as reprint 3518.

7. SERIAL AUDIO OUTPUT PORT

A 3-wire serial audio output port is provided. The port can be adjusted to suit the attached device by setting the con-

trol registers. The following parameters are adjustable: master or slave, serial clock frequency, audio data resolu-

tion, left- or right-justification of the data relative to left/right clock, optional one-bit cell delay of the first data bit, the

polarity of the bit clock, and the polarity of the left/right clock. By setting the appropriate control bits, many formats

are possible.

Figure 7 shows a selection of common output formats, along with the control bit settings. A special AES3 direct out-

put format is included, which allows the serial output port access to the V, U, and C bits embedded in the serial audio

data stream. When using the part in AES3 direct-output format, the de-emphasis filter must be off (see Section 14.4

on page 38). The P bit, which would normally be a parity bit, is replaced by a Z bit, which is used to indicate the start

of each block. The received channel status block start signal is also available as the RCBL pin in Hardware Mode

and through a GPO pin in Software Mode.

In master mode, the left/right clock (OLRCK) and the serial bit clock (OSCLK) are outputs, derived from the recov-

ered RMCK clock. In slave mode, OLRCK and OSCLK are inputs. OLRCK is normally synchronous to the appropri-

ate master clock, but OSCLK can be asynchronous and discontinuous if required. By appropriate phasing of OLRCK

and control of the serial clocks, multiple CS8416’s can share one serial port. OLRCK should be continuous, but the

duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to

DS578F3

23

CS8416

clock all the data bits. When in slave mode, the serial audio output port cannot be set for right-justified data. The

CS8416 allows immediate mute of the serial audio output port audio data by the MUTESAO bit of Control Register 1.

For more information about serial audio formats, refer to the Cirrus Logic applications note AN282, “The 2-Channel

Serial Audio Interface: A Tutorial”, available at www.cirrus.com.

OLRCK

Channel A

Channel B

Left

Justified OSCLK

(Out)

LSB

MSB

LSB

MSB

SDOUT

Channel A

Channel B

OLRCK

I²S

(Out)

OSCLK

MSB

LSB

MSB

LSB

MSB

SDOUT

Channel A

Channel B

OLRCK

Right

Justified OSCLK

(Out)

LSB

MSB

LSB

MSB Extended

Channel A

MSB Extended

Channel A

SDOUT

Channel B

OLRCK

AES3

Channel B

Direct

(Out)

OSCLK

LSB

MSB

V

U

C

MSB

V

U

C

MSB

V

U

C

Z

LSB

MSB

V U C Z

SDOUT

Frame 191

Frame 0

SOMS*

SOSF*

SORES[1:0]* SOJUST*

SODEL* SOSPOL* SOLRPOL*

Left-Justified

X

1

X

XX

11

0

1

0

1

0

1

0

I²S

Right-Justified

AES3 Direct

X

X = don’t care to match format, but does need to be set to the desired setting

* See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit

Figure 7. Serial Audio Output Example Formats

24

DS578F3

CS8416

7.1

Slip/Repeat Behavior

When using the serial audio output port in slave mode with an OLRCK input that is asynchronous to the

incoming AES3 data, the interrupt bit OSLIP (bit 5 in the Interrupt 1 Status register, 0Dh) is provided to in-

dicate when repeated or dropped samples occur. Refer to Figure 8 for the AES3 data format diagram.

When the serial output port is configured as slave, depending on the relative frequency of OLRCK to the

input AES3 data (Z/X) preamble frequency, the data will be slipped or repeated at the output of the CS8416.

After a fixed delay from the Z/X preamble (a few periods of the internal clock, which is running at 256Fs),

the circuit will look back in time until the previous Z/X preamble and check which of the following conditions

occurred:

1. If during that time, the internal data buffer was not updated, a slip has occurred. Data from the previous

frame will be output and OSLIP will be set to 1. Due to the OSLIP bit being “sticky,” it will remain 1 until

the register is read. It will then be reset until another slip/repeat condition occurs.

2. If during that time the internal data buffer did not update between two positive or negative edges (de-

pending on OLRPOL) of OLRCK, a repeat has occurred. In this case, the buffer data was updated twice,

so the part has lost one frame of data. This event will also trigger OSLIP to be set to 1. Due to the OSLIP

bit being “sticky,” it will remain 1 until the register is read. It will then be reset until another slip/repeat

condition occurs.

3. If during that time, it did see a positive edge on OLRCK (or negative edge if the SOLRPOL is set to 1)

no slip or repeat has happened. Due to the OSLIP bit being “sticky,” it will remain in its previous state

until either the register is read or a slip/repeat condition occurs.

If the user reads OSLIP as soon as the event triggers, over a long period of time the rate of occurring INT

will be equal to the difference in frequency between the input AES data and the slave serial output LRCK.

The CS8416 uses a hysteresis window when a slip/repeat event occurs. The slip/repeat is triggered when

an edge of OLRCK passes a window size from the beginning of the Z/X preamble. Without the hysteresis

window, jitter on OLRCK with a frequency very close to Fs could slip back and forth, causing multiple slip/re-

peat events. The CS8416 uses a hysteresis window to ensure that only one slip/repeat happens even with

jitter on OLRCK

Frame 191

Frame 0

Frame 1

Channel A

Data

Channel B

Data

Channel A

Data

Channel B

Data

Channel A

Data

Channel B

Data

X

Y

Z

Y

X

Y

Preambles

OLRCK (in slave mode)

Figure 8. AES3 Data Format

DS578F3

25

CS8416

7.2

AES11 Behavior

When OLRCK is configured as a master, the positive or negative edge of OLRCK (depending on the setting

of SOLRPOL in register 05h) will be within -1.0%(1/Fs) to 1.1%(1/Fs) from the start of the preamble X/Z. In

master mode, the latency through the part is dependent on the input sample frequency. The typical delay

through the part from the beginning of the preamble to the active edge of OLRCK for the various sample

frequencies is given in Table 1. In master mode without the de-emphasis filter engaged, the latency of the

audio data will be 3 frames.

Fs (kHz)

32

Delay (ns)

98.0

44.1

48

80.5

78.0

64

67.0

96

57.5

192

47.0

Table 1. Typical Delays by Frequency Values

When OLRCK is configured as a slave, any synchronized input within +/-28%(1/Fs) from the positive or neg-

ative edge of OLRCK (depending on the setting of SOLRPOL in register 05h) will be treated as being sam-

pled at the same time. Since the CS8416 has no control of the OLRCK in slave mode, the latency of the

data through the part will be a multiple of 1/Fs plus the delay between OLRCK and the preambles.

Both of these conditions are within the tolerance range set forth in the AES11 standard.

26

DS578F3

CS8416

8. S/PDIF RECEIVER

The CS8416 includes an AES3/SPDIF digital audio receiver. The receiver accepts and decodes bi-phase encoded

audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The re-

ceiver consists of an analog differential input stage, driven through analog input pins RXP0 to RXP7 and a common

RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status

and user data. External components are used to terminate the incoming data cables and isolate the CS8416. These

components are detailed in “External AES3/SPDIF/IEC60958 Receiver Components” on page 49. Figure 9 shows

the input structure of the receiver.

VL

22 kΩ

(22000/N ) Ω

VL = 5.0 V: 2.3 kΩ

VL = 3.3 V: 3.0 kΩ

R XN

+

R XP[7:0]

-

VL = 5.0 V: (1500 + 800/N) Ω

VL = 3.3 V: (1500 + 1500/N ) Ω

22 kΩ

(22000/N ) Ω

AG N D

If RXP[7:0] is selected by either the receiver MUX or the TX passthrough MUX, N=1.

If RXP[7:0] is selected by both the receiver MUX and the TX passthrough MUX, N=2.

If RXP[7:0] is not selected at all, N=0 (i.e. high impedance).

Figure 9. Receiver Input Structure

8.1

8:2 S/PDIF Input Multiplexer

8.1.1

General

The CS8416 employs a 8:2 S/PDIF input multiplexer to accommodate up to eight channels of input digital

audio data. Digital audio data may be single-ended or differential. Differential inputs utilize RXP[7:0] and

a shared RXN. Single ended signals are accommodated by using the RXP[7:0] inputs and AC coupling

RXN to ground.

All active inputs to the CS8416 8:2 input multiplexer should be coupled through a capacitor as these inputs

are biased at VL/2 when selected. These inputs are floating when not selected. Unused multiplexer inputs

should be left floating or tied to AGND. The recommended capacitor value is 0.01 μF to 0.1 μF. The rec-

ommended dielectrics for the AC coupling capacitors are C0G or X7R.

The input voltage range for the input multiplexer is set by the I/O power supply pin, VL. The input voltage

of the RXP[7:0] and RXN pins is also set by the level of VL. Input signals with voltage levels above VL or

below DGND may degrade performance or damage the part.

8.1.2

Software Mode

The multiplexer select line control is accessed through bits RXSEL[2:0] in control port register 04h. The

multiplexer defaults to RXP0.

DS578F3

27

CS8416

The second output of the input multiplexer is used to provide the selected input as a source to be output

on a GPO pin. This pass through signal is selected by TXSEL[2:0] in control port register 04h. This single-

ended signal is resolved to full-rail, but is not de-jittered before it is output.

8.1.3

Hardware Mode

In Hardware Mode the input to the decoder is selected by dedicated pins, RXSEL[1:0].

The pass through signal is selected by dedicated pins, TXSEL[1:0] for output on the dedicated TX pin.

This single-ended signal is resolved to full-rail, but is not de-jittered before it is output.

Selectable inputs are restricted to RXP0 to RXP3 for both the receiver and the TX output pin. These inputs

are selected by RXSEL[1:0] and TXSEL[1:0] respectively.

8.2

OMCK System Clock Mode

A special clock switching mode is available that allows the OMCK clock input to automatically replace

RMCK when the PLL becomes unlocked. This is accomplished without spurious transitions or glitches on

RMCK. In Hardware Mode this feature is enabled by a transition (rising edge active) on the OMCK pin after

reset. Therefore to not enable the clock switching feature in Hardware Mode, OMCK should be tied to DGND

or VL. However, in Hardware Mode, once the clock switching feature has been enabled, it can only be dis-

abled by resetting the part. In Software Mode the automatic clock switching feature is enabled by setting

SWCLK bit in Control1 register to a “1”. Additionally in Software Mode, OMCK can be manually forced to

output on RMCK by using the FSWCLK bit in the Control0 register.

When the clock switching feature is enabled, OSCLK and OLRCK are derived from the OMCK input when

the clock has been switched and the serial port is in master mode. When clock switching is enabled and the

PLL is not locked, OLRCK will be OMCK/256 and OSCLK will be OMCK/4. When the PLL loses lock, the

frequency of the VCO drops to ~750 kHz. When this system clock mode is not enabled, the OSCLK and

OLRCK will be based on the VCO when the PLL is not locked and has reached its steady-state idle frequen-

cy. Table 2 shows an example of output clocks based on clock switching being enabled or disabled.

Clock Switching

Enabled/Disabled

PLL

RMCK Clock

Ratio

RMCK

OSCLK

OLRCK

Locked/Unlocked

128*F_s

256*F_s

Disabled

Locked

6.144 MHz

~375 kHz

3.072 MHz

~187.5 kHz

2.8224 MHz

3.072 MHz

~187.5 kHz

2.8224 MHz

48 kHz

Enabled

Disabled

Unlocked

Locked

~2.925 kHz

44.1 kHz

48 kHz

Enabled

11.2896 MHz

12.288 MHz

~750 kHz

Disabled

Enabled

Locked

48 kHz

Disabled

Unlocked

~2.925 kHz

44.1 kHz

Enabled

11.2896 MHz

Example with OMCK = 11.2896 MHz, the receiver input sample rate = 48 kHz,

OSLCK = 64*Fs, and FSWCLK (Software Mode only) = ‘0’.

Table 2. Clock Switching Output Clock Rates

8.3

Clock Recovery and PLL Filter

Please see “PLL Filter” on page 53 for a general description of the PLL, selection of recommended PLL filter

components, and layout considerations. Figures 5 and 6 show the recommended configuration of the two

capacitors and one resistor that comprise the PLL filter.

28

DS578F3

CS8416

9. GENERAL PURPOSE OUTPUTS

Three General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in configuring the

CS8416. Fourteen signals are available to be routed to any of the GPO pins. The outputs of the GPO pins are set

through the GPOxSEL[3:0] bits in the Control2 (02h) and Control3 (03h) registers. All GPO pins default to GND

after reset.

GPO pins may be configured to provide the following data:

Function

Code

Definition

GND

0000

Fixed low level

EMPH

INT

0001

0010

0011

0100

0101

0110

0111

State of EMPH bit in the incoming data stream.

CS8416 interrupt output

Channel status bit

C

U

User data bit

RERR

NVERR

RCBL

Receiver Error

Non-Validity Receiver Error

Receiver Channel Status Block

If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1 kHz.

Otherwise the output is indeterminate.

96KHZ

1000

AUDIO

VLRCK

TX

1001

1010

1011

1100

Non-audio indicator for decoded input stream

Virtual LRCK. Can be used to frame the C and U output data.

Pass through of AES/SPDIF input selected by TXSEL[2:0] in the Control 4 register (04h)

VDD fixed high level

VDD

HRMCK

1101

F_SX 512 (Note 1)

Codes 1110 to 1111 - Reserved

Table 3. GPO Pin Configurations

Notes:

1. Frequency = 25 MHz Max, duty cycle not guaranteed, target duty cycle = 50% @ F_S= 48 kHz.

DS578F3

29

CS8416

10.ERROR AND STATUS REPORTING

10.1 General

While decoding the incoming bi-phase encoded data stream, the CS8416 has the ability to identify various

error conditions.

10.1.1 Software Mode

Software Mode allows the most flexibility in reading errors. When unmasked, bits in the Receiver Error

register (0Ch) indicate the following errors:

1. QCRC – CRC error in Q subcode data.

2. CCRC – CRC error in channel status data.

3. UNLOCK – PLL is not locked to incoming data stream.

4. V – Data Validity bit is set.

5. CONF – The logical OR of UNLOCK and BIP. The input data stream may be near error condition due

to jitter degradation.

6. BIP – Biphase encoding error.

7. PAR – Parity error in incoming data.

The error bits are “sticky,” meaning that they are set on the first occurrence of the associated error and

will remain set until the user reads the register through the control port. This enables the register to log all

unmasked errors that occurred since the last time the register was read.

As a result of the bits “stickiness,” it is necessary to perform two reads on these registers to see if the error

condition still exists.

The Receiver Error Mask register (06h) allows masking of individual errors. The bits in this register default

to 00h and serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to

1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver error

register, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio

sample according to the status of the HOLD bits. The exceptions are the QCRC and CCRC errors, which

do not affect the current audio sample, even if unmasked.

The HOLD bits allow a choice of:

•

Holding the previous sample

•

Replacing the current sample with zero (mute)

OR

•

Not changing the current audio sample

10.1.2 Hardware Mode

In Hardware Mode, the user may only choose between Non-Validity Receiver Error (NVERR) or Receiver

Error (RERR) by pulling the NV/RERR pin low or high, respectively. The pull-up/pull-down condition will

be sensed on start-up, and the appropriate error reporting will be set.

RERR – The previous audio sample is held and passed to the serial audio output port if the validity bit is

high, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample.

NVERR – The previous audio sample is held and passed to the serial audio output port if a parity, bi-

phase, confidence or PLL lock error occurs during the current sample.

30

DS578F3

CS8416

10.2 Non-Audio Detection

An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in-

coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit

1, which is extracted automatically by the CS8416. However, certain non-audio sources, such as AC-3™ or

MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8416 AES3

receiver can detect such non-audio data through the use of an autodetect module. The autodetect module

is similar to autodetect software used in Cirrus Logic DSPs.

If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS^®data transmission, an

internal AUTODETECT signal will be asserted. If the sync codes no longer appear after a certain amount

of time, autodetection will time-out and AUTODETECT will be de-asserted until another format is detected.

The AUDIO signal is the logical OR of AUTODETECT and the received channel status bit 1 (as decoded

according to the CHS bit in the Control1 register).

In Hardware Mode, AUDIO is output on pin 15. In Software Mode, AUDIO is available through the GPO pins.

If non-audio data is detected, the data is still processed exactly as if it were normal audio. The exception is

the use of de-emphasis auto-select feature which will bypass the de-emphasis filter if the input stream is

detected to be non-audio. It is up to the user to mute the outputs as required.

10.2.1 Format Detection

In Software Mode, the CS8416 can automatically detect various serial audio input formats. The Format

Detect Status register (0Bh) is used to indicate a detected format. The register will indicate if uncom-

pressed PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Addi-

tionally, the IEC61937 Pc/Pd burst preambles are available in registers 23h-26h. See the register

descriptions for more information.

10.3 Interrupts

The CS8416 has a comprehensive interrupt capability. The INT signal, available in Software Mode, indi-

cates when an interrupt condition has occurred and may be output on one of the GPOs. It can also be set

through bits INT[1:0] in the Control1 register (01h) to be active low, active high or active low with no active

pull-up transistor. This last mode is used for active low, wired-OR hook- ups, with multiple peripherals con-

nected to the microcontroller interrupt input pin.

Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source

may be masked off through mask register bits. In addition, each source may be set to rising edge, falling

edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the mi-

crocontroller, many different configurations are possible, depending on the needs of the equipment design-

er. Refer to the register descriptions for the Interrupt Mask (07h), Interrupt Mode MSB (08h), Interrupt Mode

LSB (09h), and Interrupt 1 Status (0Dh) registers

DS578F3

31

CS8416

11.CHANNEL STATUS AND USER-DATA HANDLING

“Channel Status Buffer Management” on page 51 describes Channel Status and User data control.

11.1 Software Mode

In Software Mode, several options are available for accessing the Channel Status and User data that is en-

coded in the received AES3/SPDIF stream.

The first option allows access directly through registers. The first 5 bytes of the Channel Status block are

decoded into the Receiver Channel Status Registers 19h - 22h. Registers 19h - 1Dh contain the A channel

status data. Registers 1Eh - 22h contain the B channel status data.

Received Channel Status (C), User (U), and EMPH bits may also be output to the GPO pins by appropriately

setting the GPOxSEL bits in control port registers 02h and 03h. In serial port master mode, OLRCK and

RCBL can be made available to qualify the U data output. In serial port slave mode, VLRCK and RCBL can

be made available to qualify the U data output. VLRCK is a virtual word clock, equal to the receiver recov-

ered sample rate, that can be used to frame the C/U output. VLRCK and RCBL are available through the

GPO pins. Figure 10 illustrates timing of the C and U data and their related signals.

The user may also access all of the C and U bits directly from the output data stream (SDOUT) by setting

bits SORES[1:0]=11 (AES3 Direct Mode) in the Serial Audio Data Format register (05h). The appropriate

bits can be stripped from the SDOUT signal by external control logic such as a DSP or microcontroller.

If the incoming User data bits have been encoded as Q-channel subcode, the data is decoded, buffered,

and presented in 10 consecutive register locations (0Eh-17h). An interrupt may be enabled to indicate the

decoding of a new Q-channel block, which may be read through the control port.

The encoded Channel Status bits which indicate sample word length are decoded according to AES3-1992

or IEC 60958. The number of auxiliary bits are reported in bits 7 to 4 of the Receiver Channel Status register

(0Ah).

11.2 Hardware Mode

In Hardware Mode, Received Channel Status (C), and User (U) bits are output on pins 19 and 18. In serial

port master mode, OLRCK and RCBL are made available to qualify the C and U data output. Figure 10 il-

lustrates timing of the C and U data and their related signals.

The user may also access all of the C and U bits directly from the output data stream (SDOUT) by pulling

the AUDIO and C pins high through 47 kΩ resistors to VL (AES3 Direct Mode). The appropriate bits can be

stripped from the SDOUT signal by external control logic such as a DSP or microcontroller. Only OLRCK in

master mode is available to qualify the U output. See “Hardware Mode Function Selection” on page 46 and

“Hardware Mode Equivalent Register Settings” on page 47 to configure these pins..

RCBL

(out)

VLRCK

(out)

C/U

(out)

–

RCBL goes high 2 frames after receipt of a Z preamble and is high for 16 frames.

VLRCK is a virtual work clock, available through the GPO pins, that can be used

to frame the C/U output.

–

VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming

Figure 10. C/U Data Outputs

32

DS578F3

CS8416

12.CONTROL PORT DESCRIPTION

The control port is used to access the registers, allowing the CS8416 to be configured for the desired operational

modes and formats. The operation of the control port may be completely asynchronous with respect to the audio

sample rates. However, to avoid potential interference problems, the control port pins should remain static if no op-

eration is required.

The control port has 2 modes: SPI and I²C, with the CS8416 acting as a slave device. SPI Mode is selected if there

is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C Mode is selected by con-

necting the AD0/CS pin through a resistor to VL or DGND, thereby permanently selecting the desired AD0 bit ad-

dress state.

12.1 SPI Mode

In SPI Mode, CS is the CS8416 chip select signal, CCLK is the control port bit clock (input into the CS8416

from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line

to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.

Figure 11 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first

seven bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write indicator

(R/W), which should be low to write. The next eight bits include the 7-bit Memory Address Pointer (MAP),

which is set to the address of the register that is to be updated. The next eight bits are the data which will

be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state.

It may be externally pulled high or low with a 47 kΩ resistor, if desired.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle which

finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip address

and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed

register (CDOUT will leave the high impedance state). The MAP automatically increments, so data for suc-

cessive registers will appear consecutively.

CS

C C L K

C H IP

M A P

DATA

A D D R E S S

ADDRESS

0010000

LSB

MSB

b y te 1

R/W

C D IN

b y te n

High Impedance

LSB

MSB

C D O U T

MAP = Memory Address Pointer, 8 bits, MSB first

Figure 11. Control Port Timing in SPI Mode

DS578F3

33

CS8416

12.2 I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There

is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be con-

nected through a resistor to VL or DGND as desired. The GPO2 pin is used to set the AD2 bit by connecting

a 47 kΩ resistor from the GPO2 pin to VL or to DGND. The states of the pins are sensed while the CS8416

is being reset.

The signal timings for a read and write cycle are shown in Figures 12 and 13. A Start condition is defined

as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is

high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS8416 after a Start

condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 4

bits of the 7-bit address field are fixed at 0010. To communicate with a CS8416, the chip address field, which

is the first byte sent to the CS8416, should match 0010 followed by the settings of the AD2, AD1, and AD0

pins. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte includes the Mem-

ory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the

contents of the register pointed to by the MAP will be output. The MAP automatically increments, so data

from successive registers will appear consecutively. Each byte is separated by an acknowledge bit (ACK).

The ACK bit is output from the CS8416 after each input byte is read, and is input to the CS8416 from the

microcontroller after each transmitted byte.

Note that the read operation can not set the MAP, so an aborted write operation is used as a preamble. As

shown in Figure 13, the write operation is aborted after the acknowledge for the MAP byte by sending a stop

condition.

26

27 28

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

24 25

SCL

SDA

DATA +1

DATA +n

CHIP ADDRESS (WRITE)

0 AD2 AD1 AD0

MAP BYTE

DATA

0

1

0

7

6

1

0

7

6

1

0

7

6

1

0

6

5

4

3

2

1

0

ACK

STOP

START

Figure 12. Control Port Timing, I²C Slave Mode Write

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26 27 28

SCL

SDA

STOP

CHIP ADDRESS (WRITE)

AD2 AD1 AD0

MAP BYTE

CHIP ADDRESS (READ)

AD2 AD1 AD0

DATA

DATA +1 DATA + n

0

1

0

1

0

1

6

5

4

3

2

1

0

7

0

7

0

7

0

ACK

START

ACK

NO

ACK

START

STOP

Figure 13. Control Port Timing, I²C Slave Mode Read

34

DS578F3

CS8416

13.CONTROL PORT REGISTER QUICK REFERENCE

Addr R/W

Function

7

6

5

4

3

2

1

0

(HEX)

00

01

02

R/W

Control0

Control1

Control2

0

FSWCLK

MUTSAO

0

PDUR

TRUNC

HOLD0

Reserved

RMCKF

Reserved

CHS

SWCLK

DETCI

INT1

INT0

HOLD1

EMPH_CN EMPH_CN EMPH_CN GPO0SEL3 GPO0SEL2 GPO0SEL1 GPO0SEL0

TL2 TL1 TL0

03

04

05

R/W

Control3

Control4

GPO1SEL3 GPO1SEL2 GPO1SEL1 GPO1SEL0 GPO2SEL3 GPO2SEL2 GPO2SEL1 GPO2SEL0

RUN

RXD

RXSEL2

SORES1

RXSEL1

SORES0

RXSEL0

SOJUST

TXSEL2

SODEL

TXSEL1

TXSEL0

R/W Serial Audio Data

Format

SOMS

SOSF

SOSPOL SOLRPOL

06

R/W

Receiver Error

Mask

0

QCRCM

CCRCM UNLOCKM

VM

CONFM

BIPM

PARM

07

08

R/W

Interrupt Mask

0

PCCHM

PCCH1

OSLIPM

OSLIP1

DETCM

DETC1

CCHM

CCH1

RERRM

RERR1

QCHM

QCH1

FCHM

FCH1

Interrupt Mode

MSB

09

0A

0B

R/W

R

Interrupt Mode

LSB

0

AUX3

0

PCCH0

AUX2

PCM

OSLIP0

AUX1

DETC0

AUX0

CCH0

PRO

RERR0

COPY

QCH0

ORIG

FCH0

EMPH

96KHZ

Receiver Channel

Status

R

Audio Format

Detect

IEC61937

DTS_LD

DTS_CD

Reserved DGTL_SIL

0C

0D

0E

R

Receiver Error

Interrupt Status

0

QCRC

PCCH

CCRC

OSLIP

UNLOCK

DETC

V

CONF

RERR

BIP

PAR

FCH

CCH

QCH

Q-Channel

CONTROL CONTROL CONTROL CONTROL ADDRESS ADDRESS ADDRESS ADDRESS

Subcode [0:7]

0F

10

11

12

13

14

15

16

17

18

R

Q-Channel

Subcode [8:15]

TRACK

INDEX

TRACK

INDEX

TRACK

INDEX

TRACK

INDEX

TRACK

INDEX

TRACK

INDEX

TRACK

INDEX

TRACK

INDEX

Q-Channel

Subcode [16:23]

Q-Channel

Subcode [24:31]

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

Q-Channel

Subcode [32:39]

Q-Channel

Subcode [40:47]

Q-Channel

Subcode [48:55]

Q-Channel

Subcode [56:63]

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

[Q-Channel

Subcode 64:71]

ABS

SECOND

ABS

SECOND

ABS

SECOND

ABS

SECOND

ABS

SECOND

ABS

SECOND

ABS

SECOND

ABS

SECOND

Q-Channel

Subcode [72:79]

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

OMCK_RMCK

Ratio

ORR7

ORR6

ORR5

ORR4

ORR3

ORR2

ORR1

ORR0

19

1A

1B

1C

1D

R

Channel A Status

AC0[7]

AC1[7]

AC2[7]

AC3[7]

AC4[7]

AC0[6]

AC1[6]

AC2[6]

AC3[6]

AC4[6]

AC0[5]

AC1[5]

AC2[5]

AC3[5]

AC4[5]

AC0[4]

AC1[4]

AC2[4]

AC3[4]

AC4[4]

AC0[3]

AC1[3]

AC2[3]

AC3[3]

AC4[3]

AC0[2]

AC1[2]

AC2[2]

AC3[2]

AC4[2]

AC0[1]

AC1[1]

AC2[1]

AC3[1]

AC4[1]

AC0[0]

AC1[0]

AC2[0]

AC3[0]

AC4[0]

DS578F3

35

CS8416

Addr R/W

(HEX)

Function

7

6

5

4

3

2

1

0

1E

1F

20

21

22

23

R

Channel B Status

BC0[7]

BC1[7]

BC2[7]

BC3[7]

BC4[7]

PC0[7]

BC0[6]

BC1[6]

BC2[6]

BC3[6]

BC4[6]

PC0[6]

BC0[5]

BC1[5]

BC2[5]

BC3[5]

BC4[5]

PC0[5]

BC0[4]

BC1[4]

BC2[4]

BC3[4]

BC4[4]

PC0[4]

BC0[3]

BC1[3]

BC2[3]

BC3[3]

BC4[3]

PC0[3]

BC0[2]

BC1[2]

BC2[2]

BC3[2]

BC4[2]

PC0[2]

BC0[1]

BC1[1]

BC2[1]

BC3[1]

BC4[1]

PC0[1]

BC0[0]

BC1[0]

BC2[0]

BC3[0]

BC4[0]

PC0[0]

BurstPreamblePC

Byte 0

24

25

26

7F

R

BurstPreamblePC

Byte 1

PC1[7]

PD0[7]

PD1[7]

ID3

PC1[6]

PD0[6]

PD1[6]

ID2

PC1[5]

PD0[5]

PD1[5]

ID1

PC1[4]

PD0[4]

PD1[4]

ID0

PC1[3]

PD0[3]

PD1[3]

VER3

PC1[2]

PD0[2]

PD1[2]

VER2

PC1[1]

PD0[1]

PD1[1]

VER1

PC1[0]

PD0[0]

PD1[0]

VER0

BurstPreamblePD

Byte 0

BurstPreamblePD

Byte 1

ID & Version

14. CONTROL PORT REGISTER DESCRIPTIONS

14.1 Memory Address Pointer (MAP)

Not a register

7

0

6

5

4

3

2

1

0

MAP6

MAP5

MAP4

MAP3

MAP2

MAP1

MAP0

MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write.

Default = ‘0000000’

14.2 Control0 (00h)

7

6

5

4

3

2

1

0

FSWCLK

0

PDUR

TRUNC

Reserved

FSWCLK – Forces the clock signal on OMCK to be output on RMCK regardless of the SWCLK (Control1

register bit 6) bit functionality or PLL lock.

Default = ‘0’

0 – Clock signal on OMCK is output on RMCK according to the SWCLK bit functionality.

1 – Forces the clock signal on OMCK to be output on RMCK regardless of the SWCLK bit functionality.

PDUR – Changes the type of phase detector used to lock to the active RXP[7:0] input. This bit should only

be set if the sample rate range is between 32 kHz and 108 kHz. If the sample rate is outside of this range

and the PDUR bit is set, loss of lock may occur.

Default = ‘0’

0 – Normal Update Rate Phase Detector - Recovered master clock (RMCK) will have low wide-band jitter,

but increased in-band jitter.

36

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1 – Higher Update Rate Phase Detector - Recovered master clock (RMCK) will have low in-band jitter, but

increased wide-band jitter. Use this setting for the best performance when the output is connected to a delta-

sigma digital-to-analog converter (DAC).

TRUNC – Determines if the audio word length is set according to the incoming channel status data as de-

coded by the AUX[3:0] bits. The resulting word length in bits is 24 minus AUX[3:0].

Default = ‘0’

0 – Incoming data is not truncated.

1 – Incoming data is truncated according to the length specified in the channel status data.

Truncation occurs before the de-emphasis filter. TRUNC has no effect on output data if de-emphasis filter

is not used.

Reserved – These bits may change state depending on the input audio data.

14.3 Control1 (01h)

7

6

5

4

3

2

1

0

SWCLK

MUTESAO

INT1

INT0

HOLD1

HOLD0

RMCKF

CHS

SWCLK - Lets OMCK determine RMCK, OSCLK, OLRCK when PLL loses lock

Default = ‘0’

0 - Disable automatic clock switching. RMCK runs at the VCO frequency (~750 kHz) on PLL Unlock.

1 - Enable automatic clock switching on PLL unlock. OMCK clock input is automatically output on RMCK on

PLL Unlock.

MUTESAO - Mute control for the serial audio output port

Default = ‘0’

0 - SDOUT not muted.

1 – SDOUT muted (set to all zeros).

INT[1:0] - Interrupt output pin (INT) control

Default = ‘00’

00 - Active high; high output indicates interrupt condition has occurred.

01 - Active low, low output indicates an interrupt condition has occurred.

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. Thus it is not recommended

to multiplex INT onto GPO2 in I²C Control Port Mode since an external resistor is required on GPO2 to spec-

ify the AD2 bit of the chip address.

11 – Reserved.

HOLD[1:0] – Determine how received audio sample is affected when a receive error occurs

Default = ‘00’

00 – hold last audio sample.

01 – replace the current audio sample with all zeros (mute).

10- do not change the received audio sample.

11 - reserved

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RMCKF – Recovered Master Clock Frequency

Default = ‘0’

0 – RMCK output frequency is 256*F_S.

1 – RMCK output frequency is 128*F_S.

CHS – Sets which channel's C data is decoded in the Receiver Channel Status register (0Ah).

Default = ‘0’

0 – A channel.

1 – B channel.

If CHS = 0 and TRUNC = 1, both channels' audio data will be truncated by the AUX[3:0] bits indicated in the

channel A Channel Status data. If CHS = 1 and TRUNC = 1, both channels' audio data will be truncated by

the AUX[3:0] bits indicated in the channel B Channel Status data. This will occur even if the AUX[3:0] bits

indicated in the channel A Channel Status data are not equal to the AUX[3:0] bits indicated in the channel

B Channel Status data.

14.4 Control2 (02h)

7

6

5

4

3

2

1

0

DETCI

EMPH_CNTL2 EMPH_CNTL1 EMPH_CNTL0 GPO0SEL3

GPO0SEL2

GPO0SEL1

GPO0SEL0

DETCI – D to E status transfer inhibit

Default = ‘0’

0 – Allow update.

1 – Inhibit update.

EMPH_CNTL[2:0] – De-emphasis filter control. See Figure 14 for De-emphasis filter response.

Default = ‘000’

000 – If the serial audio output port is using the AES3 direct-output format, the de-emphasis filter must re-

main off.

001 – 32 kHz setting.

010 – 44.1 kHz setting.

011 – 48 kHz setting.

100 – 50 μs/15 μs de-emphasis filter auto-select on. Coefficients (32, 44.1 or 48 kHz or no de-emphasis fil-

ter at all) match the pre-emphasis and sample frequency indicators in the channel status bits of Channel A.

Thus it is impossible to have de-emphasis applied to one channel but not the other. The de-emphasis filter

is turned off if the audio data is detected to be non-audio data.

GPO0SEL[3:0] – GPO0 Source select. See “General Purpose Outputs” on page 29.

Default = ‘0000’

38

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CS8416

Gain,

dB

T1 =

50us

0

T2

=15us

-10

Frequency,

KHz

F1

3.183

F2

10.61

Figure 14. De-Emphasis Filter Response

14.5 Control3 (03h)

7

6

5

4

3

2

1

0

GPO1SEL3

GPO1SEL2

GPO1SEL1

GPO1SEL0

GPO2SEL3

GPO2SEL2

GPO2SEL1

GPO2SEL0

GPO1SEL[3:0] – GPO1 Source select. See “General Purpose Outputs” on page 29.

Default = ‘0000’

GPO2SEL[3:0] – GPO2 Source select. See “General Purpose Outputs” on page 29.

Default = ‘0000’

14.6 Control4 (04h)

7

6

5

4

3

2

1

0

RUN

RXD

RXSEL2

RXSEL1

RXSEL0

TXSEL2

TXSEL1

TXSEL0

RUN - Controls the internal clocks, allowing the CS8416 to be placed in a “powered down”, low current con-

sumption state.

Default = ‘0’

0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is

operational, allowing registers to be read or changed. Power consumption is low.

1 - Normal part operation. This bit must be written to the 1 state to allow the CS8416 to begin operation. All

input clocks should be stable in frequency and phase when RUN is set to 1.

RXD – RMCK Control

Default = ‘0’

0 -RMCK is an output, Clock is derived from input frame rate.

1 – RMCK becomes high impedance. The output of OSCLK, OLRCK, and SDOUT are indeterminate.

RX_SEL[2:0] – Selects RXP0 to RXP7 for input to the receiver

Default =’000’

000 – RXP0

001 – RXP1, etc

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CS8416

TX_SEL[2:0] – Selects RXP0 to RXP7 as the input for GPO TX source

Default =’001’

000 – RXP0

001 – RXP1, etc

14.7 Serial Audio Data Format (05h)

7

6

5

4

3

2

1

0

SOMS

SOSF

SORES1

SORES0

SOJUST

SODEL

SOSPOL

SOLRPOL

SOMS - Master/Slave Mode Selector

Default = ‘0’

0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs.

1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.

SOSF - OSCLK frequency (for master mode)

Default = ‘0’

0 - OSCLK output frequency is 64*F_s.

1 - OSCLK output frequency is 128*F_s.

SORES[1:0] - Resolution of the output data on SDOUT

Default = ‘00’

00 - 24-bit resolution.

01 - 20-bit resolution.

10 - 16-bit resolution.

11 - Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. The time slot

occupied by the Z bit is used to indicate the location of the block start. This setting forces the SOJUST bit

to be “0”. When using this setting, the de-emphasis filter must be off.

SOJUST - Justification of SDOUT data relative to OLRCK

Default = ‘0’

0 - Left-Justified.

1 - Right-Justified (master mode only and SORES ≠11).

SODEL - Delay of SDOUT data relative to OLRCK, for Left-Justified data formats

(This control is only valid in Left-Justified Mode)

Default = ‘0’

0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge.

1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge.

SOSPOL - OSCLK clock polarity

Default = ‘0’

0 - SDOUT is sampled on rising edges of OSCLK.

1 - SDOUT is sampled on falling edges of OSCLK.

40

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CS8416

SOLRPOL - OLRCK clock polarity

Default = ‘0’

0 - SDOUT data is valid for the left channel when OLRCK is high.

1 - SDOUT data is valid for the right channel when OLRCK is high.

14.8 Receiver Error Mask (06h)

7

6

5

4

3

2

1

0

QCRCM

CCRCM

UNLOCKM

VM

CONFM

BIPM

PARM

The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a mask

bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error register,

will affect RERR, will affect the RERR interrupt, and will affect the current audio sample according to the

status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not

appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and will

not affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they

do not affect the current audio sample even when unmasked. This register defaults to 00h.

14.9 Interrupt Mask (07h)

7

6

5

4

3

2

1

0

PCCHM

OSLIPM

DETCM

CCHM

RERRM

QCHM

FCHM

The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1, the error

is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set

to 0, the error is masked, meaning that its occurrence will not affect the internal INT signal or the status reg-

ister. The bit positions align with the corresponding bits in Interrupt Status register. This register defaults to

00h.

The INT signal may be selected to output on the GPO pins. See “General Purpose Outputs” on page 29.

14.10 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h)

7

0

6

5

4

3

2

1

0

PCCH1

PCCH0

OSLIP1

OSLIP0

DETC1

DETC0

CCH1

CCH0

RERR1

RERR0

QCH1

QCH0

FCH1

FCH0

The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are

three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active

mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode,

the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt

pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only

depends on the INT[1:0] bits. These registers default to 00h.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

DS578F3

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CS8416

14.11 Receiver Channel Status (0Ah)

7

6

5

4

3

2

1

0

AUX3

AUX2

AUX1

AUX0

PRO

COPY

ORIG

EMPH

The bits in this register can be associated with either channel A or B of the received data. The desired chan-

nel is selected with the CHS bit of the Control1 register.

AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, decoded ac-

cording to IEC60958 and AES3.

0000 - Auxiliary data is not present.

0001 - Auxiliary data is 1 bit long.

0010 - Auxiliary data is 2 bits long.

0011 - Auxiliary data is 3 bits long.

0100 - Auxiliary data is 4 bits long.

0101 - Auxiliary data is 5 bits long.

0110 - Auxiliary data is 6 bits long.

0111 - Auxiliary data is 7 bits long.

1000 - Auxiliary data is 8 bits long.

1001 - 1111 Reserved

PRO - Channel status block format indicator

0 - Received channel status block is in the consumer format.

1 - Received channel status block is in the professional format.

COPY - SCMS copyright indicator

0 - Copyright asserted.

1 - Copyright not asserted. If the category code is set to General in the incoming AES3 stream, copyright

will always be indicated by COPY, even when the stream indicates no copyright.

ORIG - SCMS generation indicator, decoded from the category code and the L bit.

0 - Received data is 1st generation or higher.

1 - Received data is original.

Note: COPY and ORIG will both be set to 1 if incoming data is flagged as professional or if the receiver

is not in use.

EMPH – Indicates whether the input audio data has been pre-emphasized. Also indicates turning on of the

de-emphasis filter during de-emphasis auto-select mode.

0 – 50 μs/15 μs pre-emphasis indicated.

1 – 50 μs/15 μs pre-emphasis not indicated.

14.12 Format Detect Status (0Bh)

7

6

5

4

3

2

1

0

PCM

IEC61937

DTS_LD

DTS_CD

Reserved

DGTL_SIL

96KHZ

Note: PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive. A ‘1’ indicated the condition

was detected.

PCM – Uncompressed PCM data was detected.

IEC61937 – IEC61937 data was detected.

DTS_LD – DTS_LD data was detected.

42

DS578F3

CS8416

DTS_CD – DTS_CD data was detected.

Reserved – This bit may change state depending on the input audio data.

DGTL_SIL – Digital Silence was detected: at least 2047 consecutive constant samples of the same 24-bit

audio data on both channels.

96KHZ – If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1 kHz.

Otherwise the output is indeterminate.

14.13 Receiver Error (0Ch)

7

6

5

4

3

2

1

0

QCRC

CCRC

UNLOCK

V

CONF

BIP

PAR

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of

the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error

source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register.

QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries

0 - No error.

1 - Error.

CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid in Pro

mode

0 - No error.

1 - Error.

UNLOCK - PLL lock status bit. Updated on CS block boundaries.

0 - PLL locked.

1 - PLL out of lock.

V - Received AES3 Validity bit status. Updated on sub-frame boundaries.

0 - Data is valid and is normally linear coded PCM audio.

1 - Data is invalid, or may be valid compressed audio.

CONF - Confidence bit. Updated on sub-frame boundaries.

0 - No error.

1 - Confidence error. The logical OR of UNLOCK and BIP. The input data stream may be near error condi-

tion due to jitter degradation.

BIP - Bi-phase error bit. Updated on sub-frame boundaries.

0 - No error.

1 - Bi-phase error. This indicates an error in the received bi-phase coding.

PAR - Parity bit. Updated on sub-frame boundaries.

0 - No error.

1 - Parity error.

DS578F3

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CS8416

14.14 Interrupt 1 Status (0Dh)

7

6

5

4

3

2

1

0

PCCH

OSLIP

DETC

CCH

RERR

QCH

FCH

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since

the register was last read. A “0” means the associated interrupt condition has NOT occurred since the last

reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and

the interrupt source is still true. Status bits that are masked off in the associated mask register will always

be “0” in this register.

PCCH – PC burst preamble change.

Indicates that the PC byte has changed from its previous value. If the IEC61937 bit in the Format Detect

Status register goes high, it will cause a PCCH interrupt even if the PC byte hasn’t changed since the last

time the IEC61937 bit went high.

OSLIP - Serial audio output port data slip interrupt

When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source,

this bit will go high every time a data sample is dropped or repeated. See “Slip/Repeat Behavior” on

page 25 for more information.

DETC - D to E C-buffer transfer interrupt.

Indicates the completion of a D to E C-buffer transfer. See “Channel Status Buffer Management” on

page 51.

C_CHANGE -Indicates that the current 10 bytes of channel status is different from the previous 10 bytes.

(5 bytes per channel)

RERR - A receiver error has occurred.

The Receiver Error register may be read to determine the nature of the error which caused the interrupt.

QCH – A new block of Q-subcode is available for reading. The data must be read within 588 AES3 frames

after the interrupt occurs to avoid corruption of the data by the next block.

FCH – Format Change: Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL bits in the

Format Detect Status register transition from 0 to 1. When these bits in the Format Detect Status register

transition from 1 to 0, an interrupt will not be generated.

14.15 Q-Channel Subcode (0Eh - 17h)

7

6

5

4

3

2

1

0

CONTROL

TRACK

INDEX

CONTROL

TRACK

INDEX

CONTROL

TRACK

INDEX

CONTROL

TRACK

INDEX

ADDRESS

TRACK

INDEX

ADDRESS

TRACK

INDEX

ADDRESS

TRACK

INDEX

ADDRESS

TRACK

INDEX

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

MINUTE

SECOND

FRAME

ZERO

ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE

ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND

ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME

Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus, bit 7 of address 0Eh is Q[0] while

bit 0 of address 0Eh is Q[7]. Similarly, bit 0 of address 17h corresponds to Q[79].

44

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CS8416

14.16 OMCK/RMCK Ratio (18h)

7

6

5

4

3

2

1

0

ORR7

ORR6

ORR5

ORR4

ORR3

ORR2

ORR1

ORR0

This register allows the calculation of the incoming sample rate by the host microcontroller from the equation

ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256*Fso. ORR is rep-

resented as an unsigned 2-bit integer and a 6-bit fractional part. The value is meaningful only after the PLL

has reached lock. For example, if the OMCK is 12.288 MHz, Fso would be 48 kHz (48 kHz =

12.288 MHz/256). Then, if the input sample rate is also 48 kHz, you would get 1.0 from the ORR register

(The value from the ORR register is hexadecimal, so the actual value you will get is 40h).

If F_SO/F_SI> 3 ⁶³/₆₄, ORR will saturate at the value FFh. Also, there is no hysteresis on ORR. Therefore a

small amount of jitter on either clock can cause the LSB ORR[0] to oscillate.

ORR[7:6] - Integer part of the ratio (Integer value=Integer(SRR[7:6])).

ORR[5:0] - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64).

14.17 Channel Status Registers (19h - 22h)

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

Channel A Status Byte 0

Channel A Status Byte 1

Channel A Status Byte 2

Channel A Status Byte 3

Channel A Status Byte 4

Channel B Status Byte 0

Channel B Status Byte 1

Channel B Status Byte 2

Channel B Status Byte 3

Channel B Status Byte 4

AC0[7]

AC1[7]

AC2[7]

AC3[7]

AC4[7]

BC0[7]

BC1[7]

BC2[7]

BC3[7]

BC4[7]

AC0[6]

AC1[6]

AC2[6]

AC3[6]

AC4[6]

BC0[6]

BC1[6]

BC2[6]

BC3[6]

BC4[6]

AC0[5]

AC1[5]

AC2[5]

AC3[5]

AC4[5]

BC0[5]

BC1[5]

BC2[5]

BC3[5]

BC4[5]

AC0[4]

AC1[4]

AC2[4]

AC3[4]

AC4[4]

BC0[4]

BC1[4]

BC2[4]

BC3[4]

BC4[4]

AC0[3]

AC1[3]

AC2[3]

AC3[3]

AC4[3]

BC0[3]

BC1[3]

BC2[3]

BC3[3]

BC4[3]

AC0[2]

AC1[2]

AC2[2]

AC3[2]

AC4[2]

BC0[2]

BC1[2]

BC2[2]

BC3[2]

BC4[2]

AC0[1]

AC1[1]

AC2[1]

AC3[1]

AC4[1]

BC0[1]

BC1[1]

BC2[1]

BC3[1]

BC4[1]

AC0[0]

AC1[0]

AC2[0]

AC3[0]

AC4[0]

BC0[0]

BC1[0]

BC2[0]

BC3[0]

BC4[0]

14.18 IEC61937 PC/PD Burst Preamble (23h - 26h)

23h

24h

25h

26h

Burst Preamble PC Byte 0

Burst Preamble PC Byte 1

Burst Preamble PD Byte 0

Burst Preamble PD Byte 1

PC0[7]

PC1[7]

PD0[7]

PD1[7]

PC0[6]

PC1[6]

PD0[6]

PD1[6]

PC0[5]

PC1[5]

PD0[5]

PD1[5]

PC0[4]

PD1[4]

PC0[3]

PC1[3]

PD0[3]

PD1[3]

PC0[2]

PC1[2]

PD0[2]

PD1[2]

PC0[1]

PC1[1]

PD0[1]

PD1[1]

PC0[0]

PC1[0]

PD0[0]

PD1[0]

14.19 CS8416 I.D. and Version Register (7Fh)

7

6

5

4

3

2

1

0

ID3

ID2

ID1

ID0

VER3

VER2

VER1

VER0

ID[3:0] - ID code for the CS8416. Permanently set to 0010

VER[3:0] = 0001 (revision A)

VER[3:0] = 0010 (revision B)

VER[3:0] = 0011 (revision C)

VER[3:0] = 0111 (revision D)

VER[3:0] = 1111 (revision E)

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CS8416

15.HARDWARE MODE

The CS8416 has a Hardware Mode that allows the device to operate without a microcontroller. Hardware Mode is

selected by connecting the 47 kΩ pull-up/down resistor on the SDOUT pin to ground. Various pins change function

in Hardware Mode, described in Section 15.2 “Hardware Mode Function Selection” on page 46.

Hardware Mode data flow is shown in Figure 15. Audio data is input through the AES3/SPDIF receiver, and routed

to the serial audio output port. The decoded C and U bits are also output, clocked at both edges of OLRCK (master

mode only, see Figure 10).

An error in the incoming audio stream will be indicated on the NV/RERR pin. This pin can be configured in one of

two ways. If RERR is chosen by pulling NV/RERR to VL, the previous audio sample is held and passed to the serial

audio output port if the validity bit is high, or a parity, bi-phase, confidence or PLL lock error occurs during the current

sample. If NVERR is chosen by pulling NV/RERR to DGND, only parity, bi-phase, confidence or PLL lock error

cause the previous audio sample to be held.

15.1 Serial Audio Port Formats

In Hardware Mode, only a limited number of alternative serial audio port formats are available. Table 5 de-

fines the equivalent Software Mode bit settings for each format.

The start-up options, shown in Table 4, allow choice of the serial audio output port as a master or slave, and

the serial audio port format.

RXSEL[1:0] TXSEL[1:0]

OMCK

TX

RXP0

RXP1

TX Passthrough

4:2

MUX

RXP2

RXP3

OLRCK

OSCLK

SDOUT

Serial

Audio

Output

AES3 Rx

&

Decoder

RXN

De-emphasis

Filter

C

U

RMCK NV/RERR 96kHz

AUDIO

RCBL

Power supply pins (VA, VD, and VL), AGND, DGND, the reset pin (RST) and the PLL filter pin (FILT)

are omitted from the diagram. Please refer to the Typical Connection Diagram for connection details.

Figure 15. Hardware Mode Data Flow

15.2 Hardware Mode Function Selection

Hardware Mode and several options for Hardware Mode are selected by pulling CS8416 pins up to VL or

down to DGND through a 47 kΩ resistor. These settings are sensed immediately after RST is released. For

46

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each mode, every start-up option select pin (except for TX, which has an internal pull-down) MUST have an

external pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startup

conditions (set after reset).

Pin Name

SDOUT

Pull Down to DGND Function

Hardware Mode

Pull Up to VL Function

Software Mode

RCBL

AUDIO

C

Serial Port Slave Mode

Serial Port Master Mode

Serial Format Select 1 (SFSEL1)=0

Serial Format Select 0 (SFSEL0)=0

RMCK Frequency=256*F_s

Serial Format Select 1 (SFSEL1)=1

Serial Format Select 0 (SFSEL0)=1

RMCK Frequency=128*F_s

U

TX

Normal Phase Detector update rate.

Emphasis Audio Match Off

NVERR Selected

Higher Phase Detector update rate.

Emphasis Audio Match On

RERR Selected

96KHZ

NV/RERR

Table 4. Hardware Mode Start-Up Pin Conditions

15.3 Hardware Mode Equivalent Register Settings

Listed below are the equivalent values that the registers are set to in Hardware Mode.

Control0 Register (00h)

FSWCLK = 0

PDUR = Set by TX pin pull-up/down after reset.

TRUNC = 0

Control1 Register (01h)

SWCLK = Set to 1 if there a transition on OMCK after reset. Otherwise set to 0.

MUTSAO = 0

INT[1:0] = N/A.

HOLD[1:0] = 00

RMCKF = Set by U pin pull-up/down after reset.

CHS = 0

Control2 Register (02h)

DETCI = N/A

EMPH_CNTL[2] = set by 96KHZ pull-up/down after reset. See Figure 14 for the de-emphasis filter re-

sponse.

EMPH_CNTL[1:0] = 00

GPO0SEL[3:0] = N/A

Control3 Register (03h)

GPO1SEL[3:0] = N/A

GPO2SEL[3:0] = N/A

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CS8416

Control4 Register (04h)

RUN = 1

RXD = 0

RX_SEL[2] = 0

RX_SEL[1:0] = RX_SEL[1:0] pins.

TX_SEL[2] = 0

TX_SEL[1:0] = TX_SEL[1:0] pins.

Serial Audio Data Format Register (05h)

SOMS = set by RCBL pull-up/down after reset.

bits[6:0] = Set by pull-up/down on AUDIO & C after reset. See Table 5 for bit settings.

Serial Format Select [1:0]

00 (Left-Justified 24-bit)

01(I²S 24 bit)

SOSF

SORES[1:0] SOJUST SODEL SOSPOL SOLRPOL

0

00

11

0

1

0

1

0

1

0

10 (Right-Justified 24-bit)

11 (Direct AES3)

Table 5. Hardware Mode Serial Audio Format Select

Receiver Error Mask register (06h)

QCRCM = 0

CRCM = 0

UNLOCKM = 1

CONFM = 1

BIPM = 1

PARM = 1

VM = set by NV/RERR pull-up/down after reset.

Registers 07h through 7Fh do not have Hardware Mode equivalent settings.

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16.EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS

16.1 AES3 Receiver External Components

The CS8416 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig-

ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with

110 Ω ± 20% impedance. The XLR connector on the receiver should have female pins with a male shell.

Since the receiver has a very high input impedance, a 110 Ω resistor should be placed across the receiver

terminals to match the line impedance, as shown in Figures 16 and 17. Although transformers are not re-

quired by the AES specification, they are strongly recommended.

If some isolation is desired without the use of transformers, a 0.01 μF capacitor should be placed in series

with each input pin (RXP[7:0] and RXN) as shown in Figure 17. However, if a transformer is not used, high

frequency energy could be coupled into the receiver, causing degradation in analog performance.

Figures 16 and 17 show an optional (recommended) DC blocking capacitor (0.1 μF to 0.47 μF) in series with

the cable input. This improves the robustness of the receiver, preventing the saturation of the transformer,

or any DC current flow, if a DC voltage is present on the cable.

In the case of the consumer interface, the standards call for an unbalanced circuit having a receiver imped-

ance of 75 Ω ±5%. The connector for the consumer interface is an RCA phono socket. The receiver circuit

for the consumer interface is shown in Figure 18. An implementation of the Input S/PDIF Multiplexer using

the consumer interface is shown in Figure 19.

The circuit shown in Figure 20 may be used when external RS422 receivers, optical receivers or other

TTL/CMOS logic outputs drive the CS8416 receiver section.

In the configuration of systems, it is important to avoid ground loops and DC current flowing down the shield

of the cable that could result when boxes with different ground potentials are connected. Generally, it is

good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a

capacitor to chassis ground at the receiver. However, in some cases it is advantageous to have the ground

of two boxes held to the same potential, and the cable shield might be depended upon to make that electrical

connection. Generally, it is a good idea to provide the option of grounding or capacitively coupling the shield

to the chassis.

16.2 Isolating Transformer Requirements

Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on

transformer selection.

6

CS841

CS8416

RXP0

XLR

* See Text

0.01 μF

* See Text

RXP0

RXN

110 Ω

Twisted

Pair

110 Ω

Twisted

Pair

110 Ω

RXN

1

Figure 16. Professional Input Circuit

Figure 17. Transformerless Professional Input Circuit

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49

CS8416

.01μF

C S 8416

R X P 7

75 Ω

C oax

CS8416

RXP0

R X P 6

0.01 μF

75 Ω

C oax

RCA Phono

75 Ω

.

75 Ω

.01μF

75 Ω

R X P 0

75 Ω

C oax

Coax

RXN

0.01 μF

R X N

.01μF

Figure 18. Consumer Input Circuit

Figure 19. S/PDIF MUX Input Circuit

TTL/CMOS

Gate

CS8416

RXP0

0.01 μF

RXN

0.01 μF

Figure 20. TTL/CMOS Input Circuit

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17.CHANNEL STATUS BUFFER MANAGEMENT

17.1 AES3 Channel Status (C) Bit Management

The CS8416 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels

(5 x 2 x 8 = 80 bits). The user may read from this buffer’s RAM through the control port.

The buffering scheme involves two buffers, named D and E, as shown in Figure 21. The MSB of each byte

represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port

address 19h) is the consumer/professional bit for channel status block A.

The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocks

of data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the first

five bytes of C data.

The complete C data may be obtained through the C pin in Hardware Mode and through one of the GPO

pins in Software Mode. The C data is serially shifted out of the CS8416 clocked by the rising and falling

edges of OLRCK.

17.2 Accessing the E Buffer

The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of

the CS8416, through the control port.

The user can configure the interrupt enable register to cause interrupts to occur whenever D to E buffer

transfers occur. This allows determination of the allowable time periods to interact with the E buffer.

Also provided is a D to E inhibit bit in the Control2 register (02h). This may be used whenever “long” control

port interactions are occurring or for debugging purposes.

A flowchart for reading the E buffer is shown in Figure 22. Since a D to E interrupt occurs just after reading,

there is a substantial time interval until the next D to E transfer (approximately 192 frames worth of time).

This is usually enough time to access the E data without having to inhibit the next transfer.

17.2.1 Serial Copy Management System (SCMS)

In Software Mode, the CS8416 allows read access to all the channel status bits. For consumer mode

SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and

L bit appropriately.

In Hardware Mode, the SCMS protocol can be followed by either using the COPY and ORIG output pins,

or by using the C bit serial output pin. These options are documented in Section 15. “Hardware Mode” on

page 46.

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CS8416

A

B

8-bits 8-bits

Control

Port

Received

Data

Buffer

5 words

From

AES3

Receiver

Registers

19 words

D

E

C Data Serial Output

Figure 21. Channel Status Data Buffer Structure

D to E interrupt occurs

Optionally set D to E inhibit

Read E data

If set, clear D to E inhibit

Return

Figure 22. Flowchart for Reading the E Buffer

52

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18.PLL FILTER

18.1 General

An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 23

is a simplified diagram of the PLL. When the PLL is locked to an bi-phase encoded input stream, it is updat-

ed at each preamble in the bi-phase encoded stream. This occurs at twice the sampling frequency, F_S.

There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is impor-

tant. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown

in Figure 25. In addition, the PLL has been designed to only use the preambles (PDUR=0) of the bi-phase

encoded stream to provide lock update information to the PLL. This results in the PLL being immune to data

dependent jitter affects because the preambles do not vary with the data.

The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.

If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will

only track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the sample

rate that the PLL first locks onto upon application of an bi-phase encoded data stream or after enabling the

CS8416 clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return

to its wide lock range mode and re-acquire a new nominal center sample rate.

INPUT

Phase

RMCK

Comparator

VCO

and Charge Pump

R_FLT

C_RIP

C_FLT

÷N

Figure 23. PLL Block Diagram

18.2 External Filter Components

18.2.1 General

The PLL behavior is affected by the external filter component values. Figures 5 and 6 shows the recom-

mended configuration of the two capacitors and one resistor that comprise the PLL filter. In Table 6, the

component values shown have a high corner frequency jitter attenuation curve, take a short time to lock,

and offer good output jitter performance. Lock times are worst case for an F

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