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产品型号CSD17310Q5A的概述

芯片CSD17310Q5A的概述 CSD17310Q5A是一款高度集成的N通道MOSFET,专为高效电源管理应用设计。该器件的特点在于其低导通电阻及快速的开关性能,使其在DC-DC转换器、负载开关以及电动汽车等领域得到了广泛应用。CSD17310Q5A由德州仪器(Texas Instruments)研发,凭借其稳健的性能和高可靠性,成为了现代电源设计中的一个重要组件。 芯片CSD17310Q5A的详细参数 CSD17310Q5A的关键参数如下: - 最大漏极源电压(V_DS): 30V - 最大连续漏极电流(I_D): 48A - 导通电阻(R_DS(on)): 7.5 mΩ(V_GS=10V) - 栅极源电压(V_GS): ±20V - 输入电容(C_iss): 1300 pF - 输出电容(C_oss): 80 pF - 反向传导电流(I_S): 4.5A - 开关时间(t_on/...

产品型号CSD17310Q5A的Datasheet PDF文件预览

CSD17310Q5A  
www.ti.com  
SLPS255 FEBRUARY 2010  
30V, N-Channel NexFET™ Power MOSFETs  
Check for Samples: CSD17310Q5A  
1
FEATURES  
PRODUCT SUMMARY  
Drain to Source Voltage  
2
Optimized for 5V Gate Drive  
VDS  
Qg  
30  
8.9  
2.1  
V
Ultralow Qg and Qgd  
Gate Charge Total (4.5V)  
Gate Charge Gate to Drain  
nC  
nC  
m  
mΩ  
mΩ  
V
Low Thermal Resistance  
Avalanche Rated  
Qgd  
VGS = 3V  
5.7  
4.5  
3.9  
RDS(on) Drain to Source On Resistance  
VGS = 4.5V  
VGS = 8V  
Pb Free Terminal Plating  
RoHS Compliant  
VGS(th)  
Threshold Voltage  
1.3  
Halogen Free  
SON 5-mm × 6-mm Plastic Package  
Text and br Added for Spacing  
Text and br Added for Spacing  
ORDERING INFORMATION  
APPLICATIONS  
Notebook Point of Load  
Device  
Package  
Media  
Qty  
Ship  
SON 5-mm × 6-mm  
Plastic Package  
13-Inch  
Reel  
Tape and  
Reel  
Point-of-Load Synchronous Buck in  
Networking, Telecom and Computing Systems  
CSD17310Q5A  
2500  
Optimized for Synchronous FET Applications  
Text and br Added for Spacing  
Text and br Added for Spacing  
ABSOLUTE MAXIMUM RATINGS  
DESCRIPTION  
TA = 25°C unless otherwise stated  
VALUE  
UNIT  
V
The NexFET™ power MOSFET has been designed  
to minimize losses in power conversion applications,  
and optimized for 5V gate drive applications.  
VDS  
VGS  
Drain to Source Voltage  
30  
Gate to Source Voltage  
+10 / –8  
100  
V
Continuous Drain Current, TC = 25°C  
Continuous Drain Current(1)  
Pulsed Drain Current, TA = 25°C(2)  
Power Dissipation(1)  
A
ID  
Top View  
21  
A
IDM  
PD  
TJ,  
134  
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
3.1  
W
Operating Junction and Storage  
–55 to 150  
168  
°C  
TSTG Temperature Range  
Avalanche Energy, single pulse  
ID = 58A, L = 0.1mH, RG = 25Ω  
EAS  
mJ  
qJA = 40°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick)  
Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.  
D
(1)  
R
D
P0093-01  
(2) Pulse duration 300ms, duty cycle 2%  
Text 4 Spacing  
RDS(on) vs VGS  
Text 4 Spacing  
GATE CHARGE  
16  
14  
12  
10  
8
8
ID = 20A  
ID = 20A  
VDS = 15V  
7
6
5
4
3
2
1
0
TC = 125°C  
6
4
TC = 25°C  
2
0
0
1
2
3
4
5
6
7
8
9
10  
0
2
4
6
8
10  
12  
14  
16  
VGS - Gate-to-Source Voltage - V  
Qg - Gate Charge - nC  
G006  
G003  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NexFET is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  
CSD17310Q5A  
SLPS255 FEBRUARY 2010  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ELECTRICAL CHARACTERISTICS  
(TA = 25°C unless otherwise stated)  
PARAMETER  
Static Characteristics  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
BVDSS  
IDSS  
Drain to Source Voltage  
VGS = 0V, ID = 250mA  
30  
V
mA  
nA  
V
Drain to Source Leakage Current  
Gate to Source Leakage Current  
Gate to Source Threshold Voltage  
VGS = 0V, VDS = 24V  
VDS = 0V, VGS = +10/-8V  
VDS = VGS, ID = 250mA  
VGS = 3V, ID = 20A  
1
100  
1.8  
7.8  
5.9  
5.1  
IGSS  
VGS(th)  
0.9  
1.3  
5.7  
4.5  
3.9  
85  
mΩ  
mΩ  
mΩ  
S
RDS(on)  
Drain to Source On Resistance  
Transconductance  
VGS = 4.5V, ID = 20A  
VGS = 8V, ID = 20A  
gfs  
VDS = 15V, ID = 20A  
Dynamic Characteristics  
Ciss  
Coss  
Crss  
RG  
Input Capacitance  
1200  
630  
59  
1560  
820  
77  
pF  
pF  
pF  
Output Capacitance  
Reverse Transfer Capacitance  
Series Gate Resistance  
Gate Charge Total (4.5V)  
Gate Charge Gate to Drain  
Gate Charge Gate to Source  
Gate Charge at Vth  
Output Charge  
VGS = 0V, VDS = 15V, f = 1MHz  
0.9  
8.9  
2.1  
2.7  
1.4  
15.9  
6.5  
11.6  
15  
1.8  
Qg  
11.6  
nC  
nC  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
Qgd  
Qgs  
Qg(th)  
Qoss  
td(on)  
tr  
VDS = 15V, IDS = 20A  
VDS = 12.8V, VGS = 0V  
Turn On Delay Time  
Rise Time  
VDS = 15V, VGS = 4.5V, IDS = 20A,  
RG = 2Ω  
td(off)  
tf  
Turn Off Delay Time  
Fall Time  
5
Diode Characteristics  
VSD  
Qrr  
trr  
Diode Forward Voltage  
ISD = 20A, VGS = 0V  
0.85  
21  
1
V
Reverse Recovery Charge  
Reverse Recovery Time  
nC  
ns  
VDD= 12.8V, IF = 20A, di/dt = 300A/ms  
22  
THERMAL CHARACTERISTICS  
(TA = 25°C unless otherwise stated)  
PARAMETER  
Thermal Resistance Junction to Case(1)  
Thermal Resistance Junction to Ambient(1)(2)  
MIN  
TYP  
MAX  
UNIT  
°C/W  
°C/W  
RqJC  
RqJA  
1.9  
51  
(1)  
R
qJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×  
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design.  
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.  
Text  
Text  
Text  
Text  
and  
and  
and  
and  
br  
br  
br  
br  
Added  
Added  
Added  
Added  
for  
for  
for  
for  
Spacing  
Spacing  
Spacing  
Spacing  
2
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Copyright © 2010, Texas Instruments Incorporated  
Product Folder Link(s): CSD17310Q5A  
CSD17310Q5A  
www.ti.com  
SLPS255 FEBRUARY 2010  
GATE  
Source  
GATE  
Source  
Max RqJA = 51°C/W  
when mounted on  
1 inch2 (6.45 cm2) of  
2-oz. (0.071-mm thick)  
Cu.  
Max RqJA = 123°C/W  
when mounted on a  
minimum pad area of  
2-oz. (0.071-mm thick)  
Cu.  
DRAIN  
DRAIN  
M0137-02  
M0137-01  
TYPICAL MOSFET CHARACTERISTICS  
(TA = 25°C unless otherwise stated)  
10  
1
0.5  
0.3  
Duty Cycle = t1/t2  
0.1  
0.1  
0.05  
P
0.02  
0.01  
t1  
0.01  
0.001  
t2  
Single Pulse  
Typical RqJA = 98°C/W (min Cu)  
TJ = P ´ ZqJA ´ RqJA  
0.001  
0.01  
0.1  
1
10  
100  
1k  
tp - Pulse Duration - s  
G012  
Figure 1. Transient Thermal Impedance  
Copyright © 2010, Texas Instruments Incorporated  
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TYPICAL MOSFET CHARACTERISTICS (continued)  
(TA = 25°C unless otherwise stated)  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
VDS = 5V  
TC = 125°C  
VGS = 8V  
VGS = 4.5V  
VGS = 3.5V  
TC = 25°C  
TC = -55°C  
VGS = 3V  
VGS = 2.5V  
0
0.2  
0.4  
0.6  
0.8  
1
1
0
0
1.2  
1.4  
1.6  
1.8  
2
2.2  
2.4  
2.6  
VDS - Drain-to-Source Voltage - V  
VGS - Gate-to-Source Voltage - V  
G001  
G002  
Figure 2. Saturation Characteristics  
TEXT ADDED FOR SPACING  
Figure 3. Transfer Characteristics  
TEXT ADDED FOR SPACING  
8
7
6
5
4
3
2
1
0
3
2.5  
2
ID = 20A  
VDS = 15V  
f = 1MHz  
VGS = 0V  
Coss = Cds + Cgd  
Ciss = Cgd + Cgs  
1.5  
1
Crss = Cgd  
0.5  
0
0
2
4
6
8
10  
12  
14  
16  
5
10  
15  
20  
25  
30  
Qg - Gate Charge - nC  
VDS - Drain-to-Source Voltage - V  
G003  
G004  
Figure 4. Gate Charge  
Figure 5. Capacitance  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
16  
14  
12  
10  
8
1.8  
1.6  
1.4  
1.2  
1
ID = 20A  
ID = 250µA  
TC = 125°C  
0.8  
0.6  
0.4  
0.2  
0
6
4
TC = 25°C  
2
0
1
2
3
4
5
6
7
8
9
10  
-75  
-25  
25  
75  
125  
175  
VGS - Gate-to-Source Voltage - V  
TC - Case Temperature - °C  
G006  
G005  
Figure 6. Threshold Voltage vs. Temperature  
Figure 7. On-State Resistance vs. Gate-to-Source Voltage  
4
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Product Folder Link(s): CSD17310Q5A  
CSD17310Q5A  
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SLPS255 FEBRUARY 2010  
TYPICAL MOSFET CHARACTERISTICS (continued)  
(TA = 25°C unless otherwise stated)  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
1.6  
1.4  
1.2  
1
100  
10  
ID = 20A  
VGS = 8V  
1
TC = 125°C  
0.1  
0.8  
0.6  
0.4  
0.2  
TC = 25°C  
0.01  
0.001  
0.0001  
-75  
-25  
25  
75  
125  
175  
0
0.2  
0.4  
0.6  
0.8  
1
TC - Case Temperature - °C  
VSD - Source-to-Drain Voltage - V  
G007  
G008  
Figure 8. Normalized On-State Resistance vs. Temperature  
Figure 9. Typical Diode Forward Voltage  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
1k  
1k  
100  
10  
100  
1ms  
TC = 25°C  
10  
10ms  
1001  
100ms  
1
0.1  
Area Limited  
by RDS(on)  
TC = 125°C  
1s  
Single Pulse  
Typical RθJA = 98°C/W (min Cu)  
DC  
0.01  
1
0.01  
0.1  
1
10  
100  
0.01  
0.1  
1
10  
100  
VDS - Drain-to-Source Voltage - V  
t(AV) - Time in Avalanche - ms  
G009  
G010  
Figure 10. Maximum Safe Operating Area  
Figure 11. Single Pulse Unclamped Inductive Switching  
TEXT ADDED FOR SPACING  
120  
100  
80  
60  
40  
20  
0
-50  
-25  
0
25  
50  
75  
100 125 150 175  
TC - Case Temperature - °C  
G011  
Figure 12. Maximum Drain Current vs. Temperature  
Copyright © 2010, Texas Instruments Incorporated  
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CSD17310Q5A  
SLPS255 FEBRUARY 2010  
www.ti.com  
MECHANICAL DATA  
Q5A Package Dimensions  
E2  
L
H
K
q
L1  
Top View  
Side View  
Bottom View  
q
E1  
E
Front View  
M0135-01  
MILLIMETERS  
NOM  
DIM  
MIN  
0.90  
0.33  
0.20  
4.80  
3.61  
5.90  
5.70  
3.38  
MAX  
1.10  
0.51  
0.30  
5.00  
3.96  
6.10  
5.80  
3.78  
A
b
1.00  
0.41  
c
0.25  
D1  
D2  
E
4.90  
3.81  
6.00  
E1  
E2  
e
5.75  
3.58  
1.27 BSC  
0.51  
H
0.41  
1.10  
0.51  
0.06  
0°  
0.61  
K
L
0.61  
0.13  
0.71  
0.20  
12°  
L1  
q
6
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Copyright © 2010, Texas Instruments Incorporated  
Product Folder Link(s): CSD17310Q5A  
CSD17310Q5A  
www.ti.com  
SLPS255 FEBRUARY 2010  
MILLIMETERS  
INCHES  
DIM  
Recommended PCB Pattern  
MIN  
MAX  
6.305  
4.56  
4.56  
0.7  
MIN  
MAX  
0.248  
0.18  
F1  
F1  
F2  
6.205  
4.46  
4.46  
0.65  
0.62  
0.63  
0.7  
0.244  
0.176  
0.176  
0.026  
0.024  
0.025  
0.028  
0.026  
0.024  
0.193  
0.176  
F7  
F6  
F3  
0.18  
F4  
0.028  
0.026  
0.027  
0.031  
0.028  
0.026  
0.197  
0.18  
F5  
0.67  
0.68  
0.8  
F6  
F7  
F8  
0.65  
0.62  
4.9  
0.7  
F9  
0.67  
5
F10  
F11  
4.46  
4.56  
F10  
M0139-01  
For recommended circuit layout for PCB designs, see application note SLPA005 Reducing Ringing Through  
PCB Layout Techniques.  
Q5A Tape and Reel Information  
K0  
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ  
0.30 0.05  
2.00 0.05  
+0.10  
–0.00  
Ø 1.50  
B0  
A0  
8.00 0.10  
R 0.30 MAX  
Ø 1.50 MIꢁ  
R 0.30 TYP  
A0 = 6.50 0.10  
B0 = 5.30 0.10  
K0 = 1.40 0.10  
M0138-01  
Notes:  
1. 10-sprocket hole-pitch cumulative tolerance ±0.2  
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm  
3. Material: black static-dissipative polystyrene  
4. All dimensions are in mm (unless otherwise specified)  
5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket  
6. MSL1 260°C (IR and convection) PbF reflow compatible  
Copyright © 2010, Texas Instruments Incorporated  
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SLPS255 FEBRUARY 2010  
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Package Marking Information  
Location  
1st Line  
8
5
5
8
CSD  
= Fixed Characters  
NNNNN = Product Code  
2nd Line (Date Code)  
CSDNNNNN  
YYWWC  
LLLLL  
YY  
WW  
C
= Last 2 digits of the Year  
= 2-digit Work Week  
= Country of Origin  
> Philippines = P  
> Taiwan = T  
> China = C  
3rd Line  
LLLLL  
= Last 5 digits of the Wafer Lot #  
1
4
4
1
Pin 1  
Identifier  
M0136-01  
8
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PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Feb-2010  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
CSD17310Q5A  
ACTIVE  
SON  
DQJ  
8
2500  
TBD  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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Addendum-Page 1  
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配单直通车
CSD17310Q5A产品参数
型号:CSD17310Q5A
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
包装说明:6 X 5 MM, ROHS COMPLIANT, PLASTIC, SON-8
针数:8
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8541.29.00.95
Factory Lead Time:1 week
风险等级:1.68
Samacsys Confidence:4
Samacsys Status:Released
Samacsys PartID:696931
Samacsys Pin Count:9
Samacsys Part Category:MOSFET (N-Channel)
Samacsys Package Category:Other
Samacsys Footprint Name:Q5A VSON-FET
Samacsys Released Date:2019-02-11 12:59:31
Is Samacsys:N
其他特性:AVALANCHE RATED
雪崩能效等级(Eas):168 mJ
外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:30 V
最大漏极电流 (Abs) (ID):100 A
最大漏极电流 (ID):100 A
最大漏源导通电阻:0.0078 Ω
FET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):77 pF
JESD-30 代码:R-PDSO-N8
JESD-609代码:e3
湿度敏感等级:1
元件数量:1
端子数量:5
工作模式:ENHANCEMENT MODE
最高工作温度:150 °C
最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):260
极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):3.1 W
最大脉冲漏极电流 (IDM):134 A
认证状态:Not Qualified
子类别:FET General Purpose Power
表面贴装:YES
端子面层:Matte Tin (Sn)
端子形式:NO LEAD
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING
晶体管元件材料:SILICON
Base Number Matches:1
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