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产品型号CSD17556Q5B的概述

芯片CSD17556Q5B概述 CSD17556Q5B是一款高性能的MOSFET (金属氧化物半导体场效应晶体管)，由德州仪器（Texas Instruments, TI）公司设计和生产。该芯片在电源管理、开关电源及各种电路应用中发挥着重要作用。CSD17556Q5B以其低功耗、高效率和热稳定性在现代电子设备中受到了广泛关注。其主要应用领域包括计算机电源、高性能电源调节器、DC-DC转换器以及其他需要高频开关能力的设备。 CSD17556Q5B详细参数 CSD17556Q5B的技术指标相对突出，具有以下几个重要参数： 1. 最大漏极电压 (VDS)：45V 2. 最大漏极电流 (ID)：65A 3. 门源电压 (VGS)：±20V 4. 寄生电容 (Ciss)：在100kHz下的输入电容约为1200pF 5. 导通电阻 (RDS(on))：在10V栅极电压下典型值为5.5mΩ 6. 功...

产品型号CSD17556Q5B的Datasheet PDF文件预览

CSD17556Q5B

www.ti.com

SLPS392 –MARCH 2013

30V N-Channel NexFET™ Power MOSFETs

Check for Samples: CSD17556Q5B

PRODUCT SUMMARY

FEATURES

T_A= 25°C unless otherwise stated

TYPICAL VALUE

UNIT

•

Extremely Low Resistance

Ultralow Q_gand Q_gd

V_DS

Q_g

Drain to Source Voltage

Gate Charge Total (4.5V)

Gate Charge Gate to Drain

mΩ

Low Thermal Resistance

Avalanche Rated

Q_gd

7.5

V_GS= 4.5V

V_GS= 10V

1.5

1.2

R_DS(on)Drain to Source On Resistance

V_GS(th)Threshold Voltage

Pb Free Terminal Plating

RoHS Compliant

1.4

Halogen Free

ORDERING INFORMATION

SON 5-mm × 6-mm Plastic Package

Device

CSD17556Q5B

Package

Media

Qty

Ship

SON 5-mm × 6-mm

Plastic Package

13-Inch

Reel

Tape and

Reel

2500

APPLICATIONS

•

Point-of-Load Synchronous Buck in

Networking, Telecom, and Computing Systems

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C unless otherwise stated

VALUE

UNIT

•

Synchronous Rectification

V_DS

V_GS

Drain to Source Voltage

Gate to Source Voltage

Active ORing and Hotswap Applications

±20

Continuous Drain Current (Package limited),

T_C= 25°C

100

215

DESCRIPTION

The NexFET™ power MOSFET has been designed

to minimize losses in synchronous rectification and

other power conversion applications.

I_D

Continuous Drain Current (Silicon limited),

T_C= 25°C

Continuous Drain Current⁽¹⁾

Pulsed Drain Current, T_A= 25°C⁽¹⁾⁽²⁾

Power Dissipation⁽¹⁾

214

3.1

I_DM

P_D

T_J,

Top View

Operating Junction and Storage

T_STGTemperature Range

–55 to 150

500

°C

Avalanche Energy, single pulse

I_D= 100A, L = 0.1mH, R_G= 25Ω

E_AS

(1) Typical R_θJA= 42°C/W on 1-inch²(6.45-cm²), 2-oz. (0.071-

mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.

(2) Pulse duration ≤300μs, duty cycle ≤2%

P0093-01

SPACE

R_DS(on)vs V_GS

SPACE

GATE CHARGE

T_C= 25°C Id = 30A

T_C= 125ºC Id = 30A

I_D= 30A

V_DS=15V

Q_g- Gate Charge (nC)

V_GS- Gate-to- Source Voltage (V)

G001

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NexFET is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CSD17556Q5B

SLPS392 –MARCH 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ELECTRICAL CHARACTERISTICS

(T_A= 25°C unless otherwise stated)

PARAMETER

Static Characteristics

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BV_DSS

I_DSS

Drain to Source Voltage

V_GS= 0V, I_DS= 250μA

μA

Drain to Source Leakage Current

Gate to Source Leakage Current

Gate to Source Threshold Voltage

V_GS= 0V, V_DS= 24V

V_DS= 0V, V_GS= 20V

V_DS= V_GS, I_DS= 250μA

V_GS= 4.5V, I_DS= 40A

V_GS= 10V, I_DS= 40A

V_DS= 15V, I_DS= 40A

100

1.65

1.8

I_GSS

V_GS(th)

1.15

1.4

1.5

mΩ

R_DS(on)

Drain to Source On Resistance

1.2

1.4

g_fs

Transconductance

197

Dynamic Characteristics

C_iss

C_oss

C_rss

R_G

Input Capacitance

5400

1770

7020

2310

Ω

V_GS= 0V, V_DS= 15V,

f = 1MHz

Output Capacitance

Reverse Transfer Capacitance

Series Gate Resistance

Gate Charge Total (4.5V)

Gate Charge Gate to Drain

Gate Charge Gate to Source

Gate Charge at Vth

Output Charge

0.7

1.4

Q_g

Q_gd

Q_gs

Q_g(th)

Q_oss

t_d(on)

t_r

7.5

V_DS= 15V, I_DS= 40A

V_DS= 15V, V_GS= 0V

6.1

Turn On Delay Time

Rise Time

V_DS= 15V, V_GS= 4.5V,

I_DS= 40A,R_G= 2Ω

t_d(off)

t_f

Turn Off Delay Time

Fall Time

Diode Characteristics

V_SD

Q_rr

t_rr

Diode Forward Voltage

I_SD= 40A, V_GS= 0V

0.8

Reverse Recovery Charge

Reverse Recovery Time

V_DD= 15V, I_F= 40A, di/dt = 300A/μs

THERMAL CHARACTERISTICS

(T_A= 25°C unless otherwise stated)

PARAMETER

Thermal Resistance Junction to Case⁽¹⁾

Thermal Resistance Junction to Ambient⁽¹⁾⁽²⁾

MIN

TYP

MAX

UNIT

°C/W

R_θJC

R_θJA

1.3

(1)

_θJCis determined with the device mounted on a 1-inch²(6.45-cm²), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×

3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. R_θJCis specified by design, whereas R_θJAis determined by the user’s board design.

(2) Device mounted on FR4 material with 1-inch²(6.45-cm²), 2-oz. (0.071-mm thick) Cu.

Submit Documentation Feedback

Product Folder Links: CSD17556Q5B

CSD17556Q5B

www.ti.com

SLPS392 –MARCH 2013

GATE

Source

GATE

Source

Max R_θJA= 50°C/W

when mounted on

1 inch²(6.45 cm²) of 2-

oz. (0.071-mm thick)

Cu.

Max R_θJA= 125°C/W

when mounted on a

minimum pad area of

2-oz. (0.071-mm thick)

Cu.

DRAIN

M0137-02

M0137-01

TYPICAL MOSFET CHARACTERISTICS

(T_A= 25°C unless otherwise stated)

Figure 1. Transient Thermal Impedance

Submit Documentation Feedback

Product Folder Links: CSD17556Q5B

CSD17556Q5B

SLPS392 –MARCH 2013

www.ti.com

TYPICAL MOSFET CHARACTERISTICS (continued)

(T_A= 25°C unless otherwise stated)

TEXT ADDED FOR SPACING

200

180

160

140

120

100

200

180

160

140

120

100

V_DS= 5V

V_GS=10V

V_GS=6V

V_GS=4.5V

T_C= 125°C

T_C= 25°C

T_C= −55°C

0.1

0.2

0.3

0.4

0.5

V_DS- Drain-to-Source Voltage (V)

V_GS- Gate-to-Source Voltage (V)

G001

Figure 2. Saturation Characteristics

TEXT ADDED FOR SPACING

Figure 3. Transfer Characteristics

TEXT ADDED FOR SPACING

100000

10000

1000

100

C_iss= C_gd+ C_gs

C_oss= C_ds+ C_gd

C_rss= C_gd

I_D= 30A

V_DS=15V

Q_g- Gate Charge (nC)

V_DS- Drain-to-Source Voltage (V)

G001

Figure 4. Gate Charge

TEXT ADDED FOR SPACING

Figure 5. Capacitance

TEXT ADDED FOR SPACING

1.8

1.6

1.4

1.2

I_D= 250uA

T_C= 25°C Id = 30A

T_C= 125ºC Id = 30A

0.8

0.6

−75

−25

125

175

T_C- Case Temperature (ºC)

V_GS- Gate-to- Source Voltage (V)

G001

Figure 6. Threshold Voltage vs. Temperature

Figure 7. On-State Resistance vs. Gate-to-Source Voltage

Submit Documentation Feedback

Product Folder Links: CSD17556Q5B

CSD17556Q5B

www.ti.com

SLPS392 –MARCH 2013

TYPICAL MOSFET CHARACTERISTICS (continued)

(T_A= 25°C unless otherwise stated)

TEXT ADDED FOR SPACING

2.2

100

V_GS= 4.5V

V_GS= 10V

I_D=30A

T_C= 25°C

T_C= 125°C

1.8

1.6

1.4

1.2

0.1

0.01

0.001

0.0001

0.8

0.6

0.4

−75

−25

125

175

0.2

0.4

0.6

0.8

T_C- Case Temperature (ºC)

V_SD− Source-to-Drain Voltage (V)

G001

Figure 8. Normalized On-State Resistance vs. Temperature

Figure 9. Typical Diode Forward Voltage

TEXT ADDED FOR SPACING

10000

300

100

T_C= 25ºC

T_C= 125ºC

1ms

100ms

10ms

1000

100

0.1

0.01

Single Pulse

TypicalR_thetaJA=100ºC/W(min Cu)

0.01

0.1

V_DS- Drain-to-Source Voltage (V)

T_AV- Time in Avalanche (mS)

G001

Figure 10. Maximum Safe Operating Area

Figure 11. Single Pulse Unclamped Inductive Switching

TEXT ADDED FOR SPACING

300.0

250.0

200.0

150.0

100.0

50.0

Silicon limited

Package limited

0.0

−50 −25

100 125 150 175

T_C- Case Temperature (ºC)

G001

Figure 12. Maximum Drain Current vs. Temperature

Submit Documentation Feedback

Product Folder Links: CSD17556Q5B

CSD17556Q5B

SLPS392 –MARCH 2013

www.ti.com

MECHANICAL DATA

Q5B Package Dimensions

MILLIMETERS

NOM

DIM

MIN

0.95

0.36

0.15

0.20

4.90

4.12

0.20

4.90

5.90

3.48

MAX

1.05

0.46

0.25

0.30

5.10

4.32

0.30

5.10

6.10

3.68

1.00

0.41

0.20

0.25

5.00

4.22

0.25

5.00

6.00

3.58

1.27 TYP

0.56

0.46

0°

0.66

1.40 TYP

Submit Documentation Feedback

Product Folder Links: CSD17556Q5B

CSD17556Q5B

www.ti.com

SLPS392 –MARCH 2013

Recommended PCB Pattern

For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through

PCB Layout Techniques.

Recommended Stencil Pattern

Submit Documentation Feedback

Product Folder Links: CSD17556Q5B

CSD17556Q5B

SLPS392 –MARCH 2013

www.ti.com

Q5B Tape and Reel Information

4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ

0.30 0.05

2.00 0.05

+0.10

–0.00

Ø 1.50

8.00 0.10

R 0.30 MAX

Ø 1.50 MIꢁ

R 0.30 TYP

A0 = 6.50 0.10

B0 = 5.30 0.10

K0 = 1.40 0.10

M0138-01

Notes:

1. 10-sprocket hole-pitch cumulative tolerance ±0.2

2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm

3. Material: black static-dissipative polystyrene

4. All dimensions are in mm (unless otherwise specified)

5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket

Submit Documentation Feedback

Product Folder Links: CSD17556Q5B

PACKAGE OPTION ADDENDUM

www.ti.com

22-Mar-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

CSD17556Q5B

ACTIVE

VSON

DNK

2500

Pb-Free (RoHS

Exempt)

CU SN

Level-1-260C-UNLIM

-55 to 150 CSD17556

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Mar-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CSD17556Q5B

VSON

DNK

2500

330.0

12.8

6.5

5.3

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Mar-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSON DNK

SPQ

Length (mm) Width (mm) Height (mm)

335.0 335.0 32.0

CSD17556Q5B

2500

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

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CSD17556Q5B产品参数

型号:	CSD17556Q5B
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	VSON-8
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8541.29.00.95
风险等级：	1.1
其他特性：	AVALANCHE RATED
雪崩能效等级（Eas）：	500 mJ
外壳连接：	DRAIN
配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	30 V
最大漏极电流 (Abs) (ID)：	100 A
最大漏极电流 (ID)：	34 A
最大漏源导通电阻：	0.0018 Ω
FET 技术：	METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：	88 pF
JESD-30 代码：	R-PDSO-N8
JESD-609代码：	e3
湿度敏感等级：	1
元件数量：	1
端子数量：	5
工作模式：	ENHANCEMENT MODE
最高工作温度：	150 °C
最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	260
极性/信道类型：	N-CHANNEL
最大功率耗散 (Abs)：	191 W
最大脉冲漏极电流 (IDM)：	214 A
子类别：	FET General Purpose Powers
表面贴装：	YES
端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
晶体管应用：	SWITCHING
晶体管元件材料：	SILICON
Base Number Matches：	1

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产品型号CSD17556Q5B的概述

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