CXA2069Q各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号CXA2069Q的概述

CXA2069Q芯片概述 CXA2069Q是一款由索尼公司（Sony Corporation）开发的音频信号处理集成电路，广泛应用于各种音频设备中，如电视、音响系统和家庭影院。这款芯片主要用于实现高保真音频播放，同时具备调音、音量控制和多种音效处理功能。详细参数 CXA2069Q的主要参数包括： 1. 工作电压：通常在5V到12V之间。 2. 功率输出：最大输出功率为2W，适合低功耗应用。 3. 信噪比：良好的信噪比，通常在80dB以上，有助于音频清晰度的提升。 4. 频率响应：宽范围的频率响应，通常为20Hz至20kHz，满足人耳可听范围的需求。 5. 温度范围：适用于-40°C至85°C的工作环境。 6. 封装类型：常见封装形式为SOP-16或DIP-16，适合多种电路设计需求。制造厂家和封装信息 CXA2069Q是由索尼公司设计和制造的，因此其芯片的可靠性和性能得到了行业的...

产品型号CXA2069Q的Datasheet PDF文件预览

CXA2069Q

S2-Compatible 7-Input 3-Output Audio/Video Switch

Description

64 pin QFP (Plastic)

The CXA2069Q is a 7-input, 3-output audio/video

switch featuring I²C bus compatibility for TVs. This

IC has input pins that are compatible with S2

protocol.

Features

• 4 inputs that are compatible with S2 protocol

• Serial control with I²C bus

• 7 inputs, 3 outputs

Absolute Maximum Ratings (Ta=25 °C)

• The desired inputs can be selected independently

for each of the 3 outputs

• Supply voltage

VCC

°C

• Operating temperature

• Wide band video amplifier (20 MHz, –3 dB)

• Y/C MIX circuit

Topr

–20 to +75

–65 to +150

1300

• Storage temperature

• Slave address can be changed (90H/92H)

• Audio muting from external pin

• High impedance maintained by I²C bus lines (SDA,

SCL) even when power is OFF

Tstg

• Allowable power dissipation

°C

• Wide audio dynamic range (3 Vrms typ.)

Operating Conditions

Supply voltage

9±0.5

Applications

Audio/video switch featuring I²C bus compatibility

for TVs

Structure

Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

—1—

E96Y05B81

CXA2069Q

Block Diagram

VOUT1

6dB

V3 15

YIN1

YOUT1

TRAP1

COUT1

CIN1

6dB

V/YOUT2

6dB

TRAP2

COUT2

VOUT3

YOUT3

COUT3

6dB

VGND

BIAS

VCC

BIAS

6dB

LTV

LV1

LV2

LV3

LV4

LV5

LV6

RTV

RV1

RV2

RV3

RV4

RV5

RV6

AGND

LOUT1

ROUT1

0dB

6dB

LOUT2

ROUT2

LOUT3

ROUT3

0dB

DC OUT

SCL

SDA

ADR

S-1

6dB

S-2

Logic

S-3

S-4

S2-1

13 S2-2

Audio system is attenuated by 6dB at input,

and a total gain is 0dB (LOUT1 and ROUT1

can be changed to –6dB).

S2-3

S2-4

MUTE

—2—

CXA2069Q

L C S

3 C

3 V R

3 Y

A D S

D N G A

T U O C D

3 T U O C

3 T U O L

3 T U O Y

3 T U O R

3 T U O V

^{C C}V

3 V L

3 V

2 - S

2 - 2 S

2 C

2 V R

2 Y

2 T U O L

2 T U O Y / V

2 T U O R

2 P A R T

2 T U O C

E T U M

1 N I Y

2 V L

2 V

1 - S

1 - 2 S

1 C

1 V R

1 Y

S A I B

1 V L

1 V

1 N I C

—3—

CXA2069Q

Pin Description

Symbol

No.

Equivalent circuit

Description

voltage

VCC

150

Video signal inputs.

4.0 V

4.5 V

Input composite video signals.

3µA

VCC

Y/C separation signal inputs.

Input luminance signals.

The YIN1 pin inputs the signal

obtained by Y/C separating the

VOUT1 pin output.

150

YIN1

3µA

VCC

Y/C separation signal inputs.

Input chrominance signals.

The CIN1 pin inputs the signal

obtained by Y/C separating the

VOUT1 pin output.

20k

150

27k

CIN1

62 64

VCC

62, 2 LTV, LV1

9, 16 LV2, LV3

23, 29 LV4, LV5

33k

15k

16 18

23 25

29 31

59 61

59, 64 LV6, RTV 4.5 V

4, 11 RV1, RV2

Audio signal inputs.

27k

18, 25 RV3, RV4

31, 61 RV5, RV6

VCC

250

VCC

VOUT1

VOUT3

Video signal outputs.

Output composite video signals.

3.9 V

30k

27k

23.5k

—4—

CXA2069Q

No.

Symbol

Equivalent circuit

Description

voltage

VCC

Video signal output.

Either composite video signal output

or luminance signal output can be

selected by I²C bus control.

V/YOUT2

3.8 V

YOUT1

YOUT3

3.3 V

3.8 V

Video signal outputs.

Output luminance signals.

COUT1

COUT2

COUT3

Video signal outputs.

4.5 V

Output chrominance signals.

VCC

LOUT1

LOUT2

LOUT3

ROUT1

ROUT2

ROUT3

54 52

45 43

40 38

Audio signal outputs.

4.5V

20k

Zo=50 Ω (within DC ±2 mA)

Detects the S2-compatible DC

superimposed onto the C signal.

4 : 3 video signal at 1.3 V or less

4 : 3 letter-box signal at 1.3 V or more

to 2.5 V or less

VCC

S2-1

S2-2

S2-3

S2-4

147

—

16 : 9 picture squeezed signal at 2.5 V

or more

100k

This pin is pulled down to GND by a

100 kΩ resistor, so the 4 : 3 video

signal is selected when open.

—5—

CXA2069Q

No.

Symbol

Equivalent circuit

Description

voltage

Composite video/S selector.

The detection results are written

to the status register.

VCC

50k

S-1

S-2

S-3

S-4

S signal at 3.5 V or less

100k

—

Composite video signal at 3.5 V

or more

50k

This pin is pulled up to 5 V by a 100 kΩ

resistor, so the composite video signal

is selected when open.

100k

VCC

Selects the slave address

for the I²C bus.

147

72k

ADR

SCL

SDA

—

90H at 1.5 V or less

92H at 2.5 V or more

90H when open.

28k

VCC

I²C bus signal input

VILmax=1.5 V

VIHmin=3.0 V

10.5k

VCC

I²C bus signal input

VILmax=1.5 V

VIHmin=3.0 V

VOLmax=0.4 V

—6—

CXA2069Q

No.

Symbol

Equivalent circuit

Description

voltage

Outputs the S2-compatible DC

superimposed onto the COUT3 output.

The DC is superimposed by connecting

this pin to the COUT3 output via a

capacitor.

Control is performed by the I²C bus.

When 0 V is output, Q1 is ON and the

impedance is 5 kΩ.

VCC

DC_OUT

—

S2 protocol output impedance of

10 ±3 kΩ is realized by attaching

external resistance of 4.7 kΩ.

28k

DC_OUT (bus)

Output DC

4.5 V

0 V

1.9 V

4.5 V

VCC

100

TRAP1

TRAP2

3.8 V

Connects trap circuit for subcarrier.

VCC

Audio signal output mute.

Mute OFF at 1.5 V or less

Mute ON at 2.5 V or more

Mute OFF when open.

147

72k

MUTE

—

28k

VCC

20k

147

Internal reference bias (V^CC/2).

Connect to GND via a capacitor.

BIAS

4.5 V

20k

—7—

CXA2069Q

Electrical Characteristics

(Ta=25 °C VCC=9 V)

Item

Symbol

Conditions

No signal, no load

Min.

Typ.

Max.

Unit

Current consumption

ICC

Video system (Measurement circuit ; Fig. 1)

Gain

GVv

f=100 kHz, 0.3 Vp-p input

5.9

1.4

—

6.4

—

6.9

MHz

Vp-p

Frequency response

characteristics

FBWv1 f=100 kHz, input frequency where output

amplitude is –3 dB with 0.3 Vp-p output

FBWv2 serving as 0 dB

Frequency response

characteristics (Y/C mix)

—

f=100 kHz, maximum with

Input dynamic range

Cross talk

Ddv

distortion < 1.0 %

Vctv

f=4.43 MHz, 1 Vp-p input

—

–50

Audio system (Measurement circuits ; Fig. 2 to Fig. 5)

f=1 kHz, 1 Vp-p input, 5.7 kΩ

resistor inserted to input

Gain

GVA

–1

—

f=1 kHz, input frequency where output

Frequency response

characteristics

FBWA amplitude is –3 dB with 1 Vp-p output

serving as 0 dB

—

kHz

Total harmonic

distortion

f=1 kHz, 2.2 Vp-p input, where 400 Hz

THD

0.03

3.0

0.05

—

Vrms

HPF+80 kHz LPF are inserted

Input dynamic range

Cross talk

DdA

VctA

Voff

VNA

S/N

f=1 kHz, maximum with distortion < 0.3 % 2.8

f=1 kHz, 1 Vp-p input

—

–90

–55

—

–80

–40

Ripple rejection ratio

Output DC offset

Residual noise

S/N ratio

f=100 Hz, 0.3 Vp-p applied to VCC

Offset voltage between input and output

–30

When 400 Hz HPF+30 kHz LPF

are inserted

µVrms

f=1 kHz, 1 Vrms input

fCL=400 Hz, fCH=30kHz

–100

–90

—8—

CXA2069Q

Logic system

Item

Symbol

VIH

Conditions

Min.

3.0

Typ.

—

Max.

5.0

1.5

0.4

100

—

Unit

High level

input voltage

Low level

VIL

input voltage

Low level

VOL

With SDA 3 mA current supplied

output voltage

High level

IIH

VIH=4.5V

VIL=0.4V

µA

kHz

µs

input current

Low level

IIL

input current

Maximum clock

frequency

fSCL

Minimum waiting time

for data change

Minimum waiting time

for data transfer start

Low level clock

pulse width

tBUF

4.7

4.0

4.7

4.0

4.7

300

250

—

tHD;STA

tLOW

tHIGH

tSU;STA

tHD;DAT

tSU;DAT

—

High level clock

pulse width

—

Minimum waiting time

for start preparation

Minimum data

hold time

—

Minimum data

preparation time

—

Rise time

Fall time

—

300

—

Minimum waiting time

for stop preparation

tSU;STO

4.7

—9—

CXA2069Q

Measurement point

22µ

10µ

µcon

10µ

10k

LOUT1

VOUT1

ADR

RV5

1µ

600

0.47µ

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

LV5

S-4

S2-4

1µ

600

10µ

10k

0.1µ

1µ

10µ

1µ

600

10k

600

CXA2069Q

RV4

0.47µ

1µ

0.47µ

1µ

600

RV6

LV4

0.47µ

1µ

600

LTV

0.47µ

S-3

1µ

600

RTV

S2-3

Input signal

Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24, 26, 30, 60 and 63.

Output signal is measured from one of the following pins: 37, 39, 41, 44, 47, 53, 56 and 58.

Fig. 1 Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit

Measurement point

22µ

10µ

µcon

10µ

10k

LOUT1

VOUT1

ADR

RV5

1µ

5.7k

600

0.47µ

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

LV5

S-4

S2-4

5.7k

10µ

10k

0.1µ

10µ

CXA2069Q

1µ

5.7k

1µ

5.7k

600

RV4

0.47µ

1µ

5.7k

1µ

5.7k

600

RV6

LV4

1µ

0.47µ

LTV

0.47µ

S-3

1µ

5.7k

600

RTV

S2-3

Input signal

Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 29, 31, 59, 61, 62 and 64.

Output signal is measured from one of the following pins: 38, 40, 43, 45, 52 and 54.

Fig. 2 Audio system (gain, frequency response characteristics,

total harmonic distortion, input dynamic range, cross talk) measurement circuit

—10—

CXA2069Q

Measurement point

10µ

µcon

10µ

10k

LOUT1

VOUT1

ADR

RV5

1µ

600

0.47µ

1µ

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

LV5

S-4

S2-4

600

10µ

10k

10µ

1µ

0.1µ

1µ

600

10k

600

CXA2069Q

RV4

0.47µ

1µ

0.47µ

1µ

600

RV6

LV4

1µ

0.47µ

600

LTV

0.47µ

S-3

1µ

600

RTV

S2-3

A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 38, 40, 43, 45, 52 and 54 are measured.

Fig. 3 Audio system (ripple rejection ratio) measurement circuit

Measurement point

22µ

10µ

µcon

10µ

10k

LOUT1

VOUT1

ADR

RV5

1µ

5.7k

600

0.47µ

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

LV5

S-4

S2-4

5.7k

10µ

10k

10µ

0.1µ

10k

CXA2069Q

1µ

1µ 5.7k

0.47µ

5.7k

600

RV4

0.47µ

1µ 5.7k

5.7k

600

RV6

LV4

0.47µ

LTV

0.47µ

S-3

1µ 5.7k

600

RTV

S2-3

Measurement point

Fig. 4 Audio system (output DC offset voltage) measurement circuit

—11—

CXA2069Q

40dB

Measurement point

10µ 4.5V

22µ

µcon

10µ

10k

LOUT1

VOUT1

ADR

RV5

1µ

0.47µ

600

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

LV5

S-4

S2-4

1µ

600

10µ

10k

0.1µ

1µ

10µ

1µ

600

10k

600

CXA2069Q

RV4

0.47µ

1µ

0.47µ

1µ

600

RV6

LV4

0.47µ

1µ

600

LTV

0.47µ

S-3

1µ

600

RTV

S2-3

Fig. 5 Audio system (residual noise) measurement circuit

—12—

CXA2069Q

t u p n i 5 O E D I V

t u p n i 4 O E D I V

µ 1

L C S

3 C

3 V R

3 Y

0 2 2

µ 1 . 0

µ 1

A D S

k 0 7 4

D N G A

T U O C D

3 T U O C

3 T U O L

3 T U O Y

3 T U O R

3 T U O V

^{C C}V

5 7

k 0 7 4

5 7

µ 7 4 . 0

µ 1

3 V L

3 V

µ 7 4 . 0

2 - S

2 - 2 S

2 C

µ 1

µ 1 . 0

µ 1

2 V R

2 Y

k 0 7 4

5 7

µ 7 4 . 0

µ 1

2 T U O L

2 T U O Y / V

2 T U O R

2 P A R T

2 T U O C

E T U M

1 N I Y

2 V L

2 V

k 0 7 4

5 7

µ 7 4 . 0

1 - S

1 - 2 S

1 C

p 0 1 µ 0 8 1 0 2 6

µ 1

µ 1 . 0

µ 1

1 V R

1 Y

k 0 7 4

5 7

µ 7 4 . 0

µ 1

S A I B

1 V L

1 V

k 0 7 4

5 7

1 N I C

µ 7 4 . 0

t u p t u o 1 O E D I V

t u p n i 6 O E D I V

t u p n i V T

—13—

CXA2069Q

I²C BUS Control Signal

34 SDA

tBUF

33 SCL

tHD;STA tLOW

tHD;DAT

tHIGH ^tFtSU;DAT

tSU;STA

tSU;STO

Fig. 6 I²C BUS Control Signal Timing Chart

Description of Operation

The CXA2069Q is a TV I²C bus-compatible AV switch IC. The video system and the stereo audio system

both have 7 inputs and 3 outputs each. 4 of the 7 video system inputs support S2 and S protocols.

The desired inputs can be independently assigned to each output (in the audio system, the left and right

channels are processed as one unit) by I²C bus control. However, the same input is assigned to both the

video and audio system output 3.

I²C BUS Registers

1) I²C BUS

The I²C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA–serial data,

SCL–serial clock) provide control over start, stop, data transfer, synchronization, and collision

avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR

format.

SDA

MSB

LSB

MSB

LSB

SCL

S : Start condition ; SDA is set “Low” when SCL is “High”

P : Stop condition ; SDA is set “High” when SCL is “High”

A : Acknowledge ; signal sent from the slave

Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which

indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave IC

receives data at the rising edge of SCL and the master ²IC changes data at the falling edge of SCL.

Slave : An IC that is placed under the control of the master.

In a normal system, all devices excluding the central microcomputer are slaves.

Master : A central microcomputer or other controlling IC.

—14—

CXA2069Q

2) Control Registers

The CXA2069Q control is exercised by writing 3-byte data into the three 8-bit control registers which

control the output selector circuits for the 3 outputs.

Slave address

DATA1

DATA2

DATA3

S ; Start condition

A ; Acknowledge

P ; Stop condition

O Control register structure (DATA1 to DATA3)

• All registers are set to “0” during IC power on.

• “ ” indicates undefined.

Slave add.

DATA1

ADR

A-IN1

R/W

A-GAIN S/COMP1

V/YOUT S/COMP2

S/COMP3

V-IN1

V-IN2

AV-IN3

DATA2

A-IN2

DATA3

DC OUT

R/W (1) : Read/write mode

0 : Control data write

1 : Status register read

ADR (1) : This bit sets the slave address set by the address pin.

0 : 90H

1 : 92H

A-GAIN (1) : LOUT1/ROUT1 output gain selector

0 : 0 dB output

1 : –6 dB output

S/COMP1 to S/COMP3 (1 each) : S terminal input/composite signal input selectors

By setting S/COMP1 to “0”, when composite signal input is selected, YOUT1/COUT1 output the

inputs from YIN1/CIN1 during video 1 output.

0 : Composite signal inputs (TV, V1 to V6 inputs)

1 : S terminal inputs (Y1/C1 to Y4/C4 inputs)

V/YOUT (1) : This bit selects the output to Pin 44 (V/YOUT2).

0 : VOUT (composite signal) output

1 : YOUT (luminance signal) output

V-IN1 to V-IN2 (3 each) : These bits select the input signals output to each video output.

V-IN1 corresponds to the VOUT1 and YOUT1/COUT1 outputs, and V-IN2 to the VOUT2 and

YOUT2/COUT2 outputs.

0 : Mute

4 : Selects the V3 and Y3/C3 inputs

5 : Selects the V4 and Y4/C4 inputs

6 : Selects the V5 input

1 : Selects the TV input

2 : Selects the V1 and Y1/C1 inputs

3 : Selects the V2 and Y2/C2 inputs

7 : Selects the V6 input

—15—

CXA2069Q

A-IN1 to A-IN2 (3 each) : These bits select the input signals output to each audio output.

A-IN1 corresponds to the LOUT1/ROUT1 outputs, and A-IN2 to the LOUT2/ROUT2 outputs.

0 : Mute

4 : Selects the LV3/RV3 inputs

5 : Selects the LV4/RV4 inputs

6 : Selects the LV5/RV5 inputs

7 : Selects the LV6/RV6 inputs

1 : Selects the LTV/RTV inputs

2 : Selects the LV1/RV1 inputs

3 : Selects the LV2/RV2 inputs

AV-IN3 (3) : This bit selects the input signals output to output 3.

Both the video output and the audio output are selected at the same time only for AV-IN3.

0 : Mute

4 : Selects the V3, Y3/C3 and LV3/RV3 inputs

5 : Selects the V4, Y4/C4 and LV4/RV4 inputs

1 : Selects the TV and LTV/RTV inputs

2 : Selects the V1, Y1/C1 and LV1/RV1 inputs 6 : Selects the V5 and LV5/RV5 inputs

3 : Selects the V2, Y2/C2 and LV2/RV2 inputs 7 : Selects the V6 and LV6/RV6 inputs

DC OUT (2) : These bits set the DC voltage output from Pin 35 (DC OUT).

0 : 4.5 V

1 : 0 V

2 : 1.9 V

3 : 4.5 V

3) Status Registers

• When reading two bytes

Slave address

• When reading one byte

Slave address

DATA1

DATA2

NA P

S ; Start condition

A ; Acknowledge

NA ; No acknowledge

P ; Stop condition

When communication is to be terminated in the status register reading mode, the “no-acknowledge”

signal is needed to assure that the master does not issue the acknowledge signal to the slave.

It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after

DATA1.

O Status register structure (DATA1 to DATA2)

Slave add.

DATA1

ADR

S1SEL

S2SEL

S3SEL

S4SEL

S-C1

S-C3

S-C2

S-C4

DATA2

—16—

CXA2069Q

S1SEL to S4SEL (1 each) : S-1 to S-4 pin status

0 ; S-1 to S-4 pins are not grounded.

1 ; S-1 to S-4 pins are grounded.

S-1 to S-4 pin DC voltage S1SEL to S4SEL

3.5 V or more

3.5 V or less

S1SEL to S4SEL are actually determined by

comparing the S-1 to S-4 pin DC voltages with

3.5 V.

S-C1, S-C2, S-C3, S-C4 (2 each) : S2-1, S2-2, S2-3 and S2-4 pin status

0 ; 4 : 3 video signal

S2-1 to S2-4 pin DC voltage S-C1 to S-C4

1 ; 4 : 3 letter-box signal

1.3 V or less

1.3 V or more to 2.5 V or less

2.5 V or more

2 ; 16 : 9 video squeezed signal

3 ; No signal

S-C1 to S-C4 are actually determined by

comparing the S2-1 to S2-4 pin DC voltages

with two threshold. However, when the S-1 to

S-4 pins are open, the outputs are fixed to “3”.

S-1 to S-4 OPEN

4) Power-on Reset

The CXA2069Q has an internal power-on reset function that sets each control register to “0” during IC

power ON.

The power-on reset V^THhas hysteresis.

Power-on reset

released

Power-on reset

VCC

4.5V

5.6V

—17—

CXA2069Q

Video system frequency response characteristics

TV, V1 to V6 → VOUT1 to VOUT3

Y1 to Y4 → YOUT1 to YOUT3

C1 to C4 → COUT1 to COUT3

Y1/C1 to Y4/C4

→ VOUT1 to VOUT3

–2

100k

10M

100M

Frequency [Hz]

Audio system frequency response characteristics

L/RTV, L/R1 to L/R6 → LOUT1 (0dB)

L/RTV, L/R1 to L/R6 → LOUT2 to LOUT3

–2

–4

–6

–8

L/RTV, L/R1 to L/R6 → LOUT1 (–6dB)

10k

Frequency [Hz]

100k

Audio system distortion vs. Input amplitude

f=1kHz

400Hz HPF, 80kHz LPF

0.1

LOUT1 output (0dB gain)

LOUT2 and

LOUT 3 outputs

0.01

0.002

Input amplitude [Vrms]

—18—

CXA2069Q

Package Outline Unit : mm

64PIN QFP(PLASTIC)

23.9 ± 0.4

+ 0.1

0.15 – 0.05

+ 0.4

20.0 – 0.1

0.15

+ 0.2

0.1 – 0.05

+ 0.35

2.75 – 0.15

+ 0.15

0.4 – 0.1

1.0

0° to10°

0.2

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

EPOXY RESIN

SOLDER/PALLADIUM

PLATING

QFP-64P-L01

SONY CODE

EIAJ CODE

LEAD MATERIAL

PACKAGE MASS

42/COPPER ALLOY

1.5g

QFP064-P-1420

JEDEC CODE

—19—

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CXA2069Q产品参数

型号:	CXA2069Q
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	QFP
包装说明：	QFP, QFP64,.7X.95,40
针数：	64
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.77
模拟集成电路 - 其他类型：	AUDIO/VIDEO SWITCH
JESD-30 代码：	R-PQFP-G64
JESD-609代码：	e4
长度：	20 mm
信道数量：	7
功能数量：	1
端子数量：	64
最高工作温度：	75 °C
最低工作温度：	-20 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP
封装等效代码：	QFP64,.7X.95,40
封装形状：	RECTANGULAR
封装形式：	FLATPACK
峰值回流温度（摄氏度）：	260
电源：	9 V
认证状态：	Not Qualified
座面最大高度：	3.1 mm
子类别：	Multiplexer or Switches
最大供电电压 (Vsup)：	9.5 V
最小供电电压 (Vsup)：	8.5 V
标称供电电压 (Vsup)：	9 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	COMMERCIAL EXTENDED
端子面层：	Palladium (Pd)
端子形式：	GULL WING
端子节距：	1 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	10
宽度：	14 mm
Base Number Matches：	1

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