HI2570, CXD2570
Analog Characteristics AV 1 = AV 2 = AV 3 = AV 4 = XV
= DV
= 5.0V ± 10%, AV 1 = AV 2 = AV 3 = AV 4 =
DD
DD
DD
DD
DD
DD SS SS SS SS
o
XV = DV = 0V, T = 25 C (Continued)
SS
SS
A
ITEM
Channel Separation
CONDITIONS
MIN.
—
TYP.
100
MAX.
—
UNIT
dB
1kHz, 0dB
Gain Difference Between Channels
Output Level
—
0.05
1.93
—
dB
R
= 3.9kW
1.80
2.10
Vrms
L
Description of Functions
CRYSTAL
OSCILLATOR
FREQUENCY
1. Serial data interface
XSL2
XSL1
XSL0
XCLK UCLK
256Fs 128Fs
256Fs 256Fs
256Fs 384Fs
256Fs 512Fs
[Related pins] LRCK, BCK, SOUT, SIN, MASL, MLSL
L
L
L
L
L
L
L
H
L
256Fs
512Fs
768Fs
1024Fs
The serial data format is common for both SIN (DA converter
input) and SOUT (AD converter output), consisting of two
channels per sampling serial data represented by 2’s com-
plement. Each channel is divided into 32-bit slots, of which
16 bits are handled as data.
H
H
H
*The CXD2555Q, which has the same pin configuration with
this IC is recommended when using only Fs = 32kHz to
48kHz.
MASL is used to select whether the 16 bits of valid data is
placed in the first or the last half of the 32-bit slots.
4. Crystal oscillator frequency selection (FS = 8kHz to
16kHz)
Similarly, MLSL is used to select whether the serial data is
arranged at MSB first of LSB first.
[Related pins] XTLI, XTLO, XSL0, XSL1, XSL2, UCLK,
XCLK
MASL
High
Low
MLSL
High
Low
Frontward truncation
Rearward truncation
MSB first
LSB first
With XSL2 fixed High, the device can be operated with low-
Fs frequencies. In this case, the frequency of the crystal
oscillator can be selected by setting a combination of XSL0
and XSL1 accordingly.
2. Master mode/slave mode
[Related pins] MS, LRCK, BCK
CRYSTAL
OSCILLATOR
FREQUENCY*
When using the CXD2570Q in multiple units or in a pair with
DA converter such as the CXD2558M, one of these
CXD2570Qs should be in the master mode to serve as the
source of clocks LRCK and BCK.
XSL2
XSL1
XSL0
XCLK UCLK
H
H
H
H
L
L
L
H
L
512Fs
—
512Fs 256Fs
—
—
H
H
1024Fs
—
512Fs 512Fs
The other ICs including CXD2570Qs are used in the slave
mode, with their clocks LRCK and BCK supplied by the mas-
ter CXD2570Q.
H
—
—
5. A/D converter input level
MS
High
Low
MODE
LRCK AND BCK I/O
Any desired input level V (m . 0.1Vrms) can be selected by
IN
adjusting R to generate the full-scale output of the AD con-
Master mode
Slave mode
Output
Input
IN
verter.
V
generation of full-scale output varies with the products,
IN
3. Crystal oscillator frequency selection (FS = 16kHz to
48kHz)
and calculate the V maximum level (approximately -3dB
below the full-scale) using the following equation to input the
signal.
IN
[Related pins] XTLI, XTLO, XSL0, XSL1, XSL2, UCLK,
XCLK
(1) Fs = 16kHz to 48kHz (XSL2 = Low)
R
= 1230 ⋅ V [Vrms] -1200 (Ω)
By setting a combination of XSL0 and XSL1, with XSL2 fixed
low, the frequency of the external crystal oscillator con-
nected to XTLI and XTLO can be selected. In this case,
XCLK outputs a clock whose frequency is always 256 times
Fs, and UCLK outputs a clock that is half the crystal oscilla-
tor frequency.
IN
IN
(2) Fs = 8 to 16kHz (XSL2 = High)
= 26600 ⋅ V [Vrms] -1200 (Ω)
R
IN
IN
6. D/A converter output level
To change the D/A converter output level, adjust R15, R17,
R30 and R32 in Application Circuit on page.
When supplying the master clock from some other external
source, not a crystal oscillator, use XTLI for this clock input
and leave XTLO open.
7