CXP84124各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

CXP84120/84124

CMOS 8-bit Single Chip Microcomputer

Description

80 pin QFP (Plastic)

The CXP84120/84124 is a CMOS 8-bit single chip

micro-computer integrating on a single chip an A/D

converter, serial interface, timer/counter, time base

timer, capture timer/counter, remote control reception

circuit and other servo systems besides the basic

configurations of 8-bit CPU, ROM, RAM, and I/O

port.

The CXP84120/84124 also provides a power-on

reset function and a sleep/stop function that enables lower power consumption.

Features

• Wide-range instruction system (213 instructions) to cover various types of data

— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle

400ns at 10MHz operation

122µs at 32kHz operation

20K bytes (CXP84120)

24K bytes (CXP84124)

624 bytes

• Incorporated ROM capacity

• Incorporated RAM capacity

• Peripheral functions

— A/D converter

8 bits, 8 channels, successive approximation method

(Conversion time of 32µs/10MHz)

SIO with 8-bit, 8-stage FIFO incorporated for data use

(Auto transfer for 1 to 8 bytes), 1 channel

8-bit standard SIO, 1 channel

8-bit timer

— Serial interface

— Timer

8-bit timer/counter

19-bit time base timer

16-bit capture timer/counter

32kHz timer/counter

— Remote control reception circuit Incorporated noise elimination circuit

Incorporated 8-bit, 6-stage FIFO for measurement data

14 bits, 1 channel

— PWM output

• Interruption

14 factors, 15 vectors, multi-interruption possible

Sleep/stop

• Standby mode

• Package

80-pin plastic QFP

• Piggyback/evaluation chip

CXP84100 80-pin ceramic QFP

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E92234A81-PS

CXP84120/84124

A T R O P B T R O P C T R O P D T R O P E T R O P F T R O P G T R O P H T R O P I T R O P

s s V

D D V

T S R

L A T X

L A T X E

X T

X E T

I M N / 3 E P

3 T N I / 3 I P

2 T N I / 2 I P

1 T N I / 1 I P

0 T N I / 0 I P

R E L L O R T N O C T P U R R E T N I

F E R V A

s s V A

– 2 –

CXP84120/84124

Pin Assignment (Top View)

80 79 78 77 76 75 74 73 72

71 70 69 68 67

66 65

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

PI4

PF3

2

PI3/INT3

PI2/INT2

PI1/INT1

PI0/INT0

PE5TO

PF4

3

PF5

4

PF6

5

PF7

6

PD0

7

PE4/PWM

PE3/NMI

PE2/RMC

PE1/EC1

PE0/EC0

PB7/SO1

PB6/SI1

PD1

8

PD2

9

PD3

PD4

PD5

PD6

PD7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PH0

PH1

PH2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

PB5/SCK1

PB4/SO0

PB3/SI0

PB2/SCK0

PB1/CS0

PB0/CINT

PA7/AN7

PA6/AN6

PA5/AN5

PA4/AN4

PA3/AN3

35

36 37 38

40

39

25 26 27 28 29 30

31

32 33

34

Note) NC (Pin 73) must be connected to VDD.

– 3 –

CXP84120/84124

Pin Description

Symbol

I/O

Description

(Port A)

8-bit I/O port. I/O can be

set in a unit of single bit.

Incorporation of the

pull-up resistance can be (8 pins)

set through the software

in a unit of 4 bits.

PA0/AN0

to

PA7/AN7

Analog inputs to A/D converter.

I/O/Analog input

(8 pins)

PB0/CINT

PB1/CS0

PB2/SCK0

PB3/SI0

I/O/Input

I/O/I/O

External capture input to 16-bit timer/counter.

Chip select input for serial interface (CH0).

Serial clock I/O (CH0).

(Port B)

7-bit I/O port in which I/O

can be set in a unit of

single bit. Also, an

uppermost bit (PB7)

exclusively for output.

Incorporation of pull-up

resistor can be set

through the software in a

unit of 4 bits.

I/O/Input

I/O/Output

I/O/I/O

Serial data input (CH0).

PB4/SO0

PB5/SCK1

PB6/SI1

Serial data output (CH0).

Serial clock I/O (CH1).

I/O/Input

Output/Output

Serial data input (CH1).

(8 pins)

PB7/SO1

Serial data output (CH1).

(Port C)

8-bit I/O port. I/O can be set in a unit of single bit. Capable of driving

12mA sink current. Incorporation of pull-up resistor can be set through

the software in a unit of 4 bits.

PC0 to PC7

PD0 to PD7

I/O

(8 pins)

(Port D)

8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-

up resistor can be set through the software in a unit of 4 bits.

(8 pins)

Input/Input

Output/Output

PE0/EC0

PE1/EC1

PE2/RMC

PE3/NMI

PE4/PWM

External event inputs for timer/counter.

(2 pins)

(Port E)

6-bit port. Lower 4 bits

are for inputs; upper

Remote control reception circuit input.

Non-maskable interruption request input.

2 bits are for outputs.

14-bit PWM output.

(6 pins)

Rectangular wave output for 16-bit

timer/counter. Output for 32kHz oscillation

frequency division.

Output/Output/

Output

PE5/TO/ADJ

PF0 to PF7

(Port F)

8-bit I/O port. I/O can be set in a unit of single bit. Incorporation of

pull-up resistor can be set through the software in a unit of 4 bits.

(8 pins)

I/O

– 4 –

CXP84120/84124

Symbol

I/O

Description

(Port G)

8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-

up resistor can be set through the software in a unit of 4 bits.

(8 pins)

PG0 to PG7

I/O

(Port H)

8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-

up resistor can be set through the software in a unit of 4 bits.

(8 pins)

PH0 to PH7

(Port I)

PI0/INT0

to

PI3/INT3

External interruption

request inputs.

8-bit I/O ports. I/O can be set in a unit of single

bit. Incorporation of pull-up resistor can be set

through the software in a unit of 4 bits.

(8 pins)

I/O/Input

I/O

PI4 to PI7

EXTAL

XTAL

Input

Output

Crystal connectors for system clock oscillation. When the clock is supplied

externally, input to EXTAL; opposite phase clock should be input to XTAL.

Crystal connectors for 32kHz timer/counter clock generation circuit.

Connect a 32kHz crystal oscillator between TEX and TX.

For usage as event input, connect clock oscillation source to TEX, and

open TX.

TEX

TX

Input

Output

Input

RST

NC

Low-level active, system reset.

NC. Under normal operating conditions, connect to V^DD.

Reference voltage input for A/D converter.

A/D converter GND.

AV^REF

AVss

V^DD

Input

Positive power supply.

Vss

GND

– 5 –

CXP84120/84124

Input/Output Circuit Formats for Pins

When reset

Circuit format

Port A

Pull-up resistance

"0" when reset

Port A data

PA0/AN0

to

PA7/AN7

Port A direction

"0" when reset

Input protection

circuit

IP

Hi-Z

Data bus

RD (Port A)

Port A input

selection

Input multiplexer

"0" when reset

A/D converter

Pull-up transistors

approx. 10kΩ

8 pins

Port B

Pull-up resistance

"0" when reset

Port B data

PB0/CINT

PB1/CS0

PB3/SI0

PB6/SI1

Hi-Z

Port B direction

"0" when reset

IP

Schmitt input

Data bus

RD (Port B)

CINT

CS0

SI0

Pull-up transistors

approx. 10kΩ

4 pins

SI1

Port B

Pull-up resistance

"0" when reset

SCK OUT

Output enable

Port B output

selection

PB2/SCK0

PB5/SCK1

"0" when reset

IP

Hi-Z

Port B data

Port B direction

"0" when reset

Schmitt input

Data bus

RD (Port B)

2 pins

Pull-up transistors

approx. 10kΩ

SCK in

– 6 –

CXP84120/84124

When reset

Circuit format

Port B

Pull-up resistance

SO

Output enable

Port B output

selection

"0" when reset

PB4/SO0

IP

Port B data

Hi-Z

Port B direction

"0" when reset

Data bus

RD (Port B)

1 pin

Pull-up transistors

approx. 10kΩ

Port B

Internal reset signal

SO

Output enable

Port B output

selection

PB7/SO1

High level

"1" when reset

Port B data

Data bus

Pull-up transistors

approx. 10kΩ

1 pin

RD (Port B)

Port C

2

Pull-up resistance

"0" when reset

Port C data

PC0 to PC7

Hi-Z

1

Port C direction

"0" when reset

IP

1

Large current drive

Data bus

of 12mA possible

Pull-up transistors

approx. 10kΩ

2

RD (Port C)

8 pins

Port E

PE0/EC0

PE1/EC1

PE2/RMC

PE3/NMI

Schmitt input

EC0

EC1

IP

RMC/NMI

Hi-Z

Data bus

4 pins

RD (Port E)

– 7 –

CXP84120/84124

When reset

Circuit format

Port E

PWM

Port E output

selection

PE4/PWM

1 pin

"0" when reset

High level

Port E data

"1" when reset

RD (Port E)

Data bus

Port E

Ouput enable

TO

ADJ16K

ADJ2K

MPX

Port E output

selection

Port E output

selection

PE5/TO/ADJ

"00" when reset

High level

Port E output

selection

"0" when reset

Port E data

ADJ signals are frequency division

"1" when reset

Data bus

outputs for 32kHz oscillation frequency

adjustment. ADJ2K provides usage as

buzzer output.

RD (Port E)

1 pin

Port D

Port F

Port G

Port H

Port I

Pull-up resistance

"0" when reset

Port data

PD0 to PD7

PF0 to PF7

PG0 to PG7

PH0 to PH7

PI4 to PI7

Hi-Z

Port direction

"0" when reset

IP

Data bus

RD

Pull-up transistors

approx. 10kΩ

36 pins

– 8 –

CXP84120/84124

When reset

Circuit format

Port I

Pull-up resistance

"0" when reset

Port data

PI0/INT0

to

PI3/INT3

Port direction

"0" when reset

Hi-Z

IP

Data bus

RD

INT0

INT1

INT2

INT3

Pull-up transistors

approx. 10kΩ

4 pins

• Diagram shows circuit

composition during oscillation.

EXTAL

XTAL

EXTAL

IP

Oscillation

• Feedback resistor is removed

during stop.

XTAL

2 pins

• Diagram shows circuit

composition during oscillation.

TEX

TX

TEX

TX

IP

Oscillation

• When the operation of the oscillation

circuit is stopped by the software, the

feedback resistor is removed, and

TEX and TX become "Low" level and

"High" level respectively.

2 pins

Pull-up resistor

RST

1 pin

OP

Mask option

Low level

IP

Schmitt input

– 9 –

CXP84120/84124

Absolute Maximum Ratings

(Vss = 0V reference)

Item

Symbol

VDD

Rating

–0.3 to +7.0

–0.3 to +0.3

–0.3 to +7.0

–5

Unit

V

Remarks

Supply voltage

V

AVSS

VIN

1

V

Input voltage

V

Output voltage

VOUT

IOH

mA

°C

mW

High level output current

High level total output current

Output per pin

Total for all output pins

–50

∑IOH

IOL

15

Value per pin, excluding large current outputs

Value per pin ²for large current outputs

Total for all output pins

Low level output current

20

IOLC

∑IOL

Topr

Tstg

PD

Low level total output current

Operating temperature

Storage temperature

100

–20 to +75

–55 to +150

600

Allowable power dissipation

1

VIN and VOUT must not exceed VDD + 0.3V.

2

The large current drive transistor is the N-ch transistor of Port C (PC).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding these conditions may adversely

affect the reliability of the LSI.

Recommended Operating Conditions

(Vss = 0V reference)

Remarks

Item

Symbol

Min.

4.5

Max.

5.5

Unit

V

High-speed mode

1

guaranteed operation range

Low-speed mode

3.5

5.5

Supply voltage

VDD

1

guaranteed operation range

2.7

2.5

5.5

Guaranteed operation range with TEX clock

Guaranteed data hold range during stop

2

0.7VDD

0.8VDD

V^DD

VDD

V

VIH

High level input

voltage

3

VIHS

VIHEX

VIL

Hysteresis input

4

VDD – 0.4 VDD + 0.3

V

EXTAL

2

0

0.3VDD

0.2VDD

0.4

V

Low level input

voltage

3

V

VILS

VILEX

Topr

Hysteresis input

4

–0.3

–20

V

EXTAL

Operating temperature

+75

°C

1

High-speed mode is 1/2 frequency division clock selection; low-speed mode is 1/16 frequency division clock

selection.

2

3

4

Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF to PH, PI4 to PI7).

Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2, INT3.

Specifies only during external clock input.

– 10 –

CXP84120/84124

Electrical Characteristics

DC Characteristics

(Ta = –20 to +75°C, Vss = 0V reference)

Max.

Item

Symbol

Pins

Conditions

VDD = 4.5V, IOH = –0.5mA

VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOL = 1.8mA

VDD = 4.5V, IOL = 3.6mA

VDD = 4.5V, IOL = 12.0mA

VDD = 5.5V, VIH = 5.5V

VDD = 5.5V, VIL = 0.4V

VDD = 5.5V, VIH = 5.5V

Min.

4.0

Typ.

Unit

V

High level

output voltage

VOH

PA to PD,

PE4, PE5,

PF to PI

V

3.5

0.4

0.6

V

Low level

output voltage

VOL

V

PC

1.5

V

IIHE

IILE

IIHT

IILT

IILR

40

µA

mA

µA

0.5

–0.5

0.1

EXTAL

–40

10

TEX

Input current

–10

–400

–2.0

–0.1

–1.5

VDD = 5.5V,

VIL = 0.4V

1

RST

2

PA to PD ,

PF to PI

IIL

IIZ

2

VDD = 4.5V, VIL = 4.0V

–10

VDD = 5.5V,

VI = 0, 5.5V

I/O leakage

current

PE0 to PE3,

±10

40

µA

1

RST

High-speed mode operation

(1/2 frequency division clock)

IDD1

18

mA

VDD = 5.5V, 10MHz crystal oscillation

(C1 = C2 = 15pF)

VDD = 3V, 32kHz crystal oscillation

(C1 = C2 = 47pF)

IDD2

35

1.1

9

100

8

µA

mA

µA

Sleep mode

Power supply

VDD

3

current

IDDS1

IDDS2

IDDS3

VDD = 5.5V, 10MHz crystal oscillation

(C1 = C2 = 15pF)

VDD = 3V, 32kHz crystal oscillation

(C1 = C2 = 47pF)

30

10

Stop mode

V

DD = 5.5V, termination of 10MHz and

32kHz crystal oscillation

Pins other

than PB7,

PE4, PE5,

Clock 1MHz

0V for all pins excluding measured

10

20

pF

Input capacity

CIN

AVREF, AVSS, pins

VDD, VSS

1

2

3

RST specifies the input current when pull-up resistance has been selected; leakage current when no

resistance has been selected.

Pins PA to PD, and PF to PI specify the input current when pull-up resistance has been selected; leakage

current when no resistance has been selected. (Excludes output PB7)

When all pins are open.

– 11 –

CXP84120/84124

AC Characteristics

(1) Clock timing

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

Symbol Pins

Conditions

Fig. 1, Fig. 2

Min.

1

Typ.

Max.

10

Unit

XTAL

System clock frequency

fC

MHz

EXTAL

System clock input pulse

width

t

XL,

XH

Fig. 1, Fig. 2

External clock drive

ns

ms

37.5

EXTAL

t

System clock input

rise time, fall time

t

CR,

CF

Fig. 1, Fig. 2

External clock drive

200

20

t

Event count input clock

pulse width

t

EH,

EL

EC0

EC1

1

tsys + 50

Fig. 3

t

Event count input clock

rise time, fall time

t

ER,

EF

EC0

EC1

t

VDD = 2.7 to 5.5V

Fig. 2 (32kHz clock

applied condition)

TEX

TX

System clock frequency

fC

kHz

32.768

Event count input clock

input pulse width

t

TL,

µs

10

TEX

Fig. 3

tTH

Event count input clock

rise time, fall time

tTR,

TF

ms

20

t

1

tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock

control register (address: 00FEH).

tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)

1/fc

VDD – 0.4V

EXTAL

0.4V

tXH

tCF

tXL

tCR

Fig. 1. Clock timing

Crystal oscillation

Ceramic oscillation

32kHz clock applied condition

Crystal oscillation

External clock

EXTAL

XTAL

EXTAL

XTAL

TEX

TX

C1

C2

74HC04

C1

C2

Fig. 2. Clock applied conditions

– 12 –

CXP84120/84124

TEX

EC0

EC1

0.8VDD

0.2VDD

tEH

tTH

tEF

tTF

tEL

tTL

tER

tTR

Fig. 3. Event count clock timing

(2) Serial transfer (CH0)

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

Symbol

Condition

Min.

Max.

Unit

ns

Chip select transfer mode

(SCK0 = output mode)

CS0 ↓ → SCK0

tsys + 200

tDCSK

tDCSKF

t

DCSO

SCK0

delay time

Chip select transfer mode

(SCK0 = output mode)

CS0 ↑ → SCK0

float delay time

ns

tsys + 200

SCK0

SO0

CS0 ↓ → SO0

Chip select transfer mode

delay time

CS0 ↑ → SO0

float delay time

t

DCSOF

WHCS

SO0

CS0

ns

Chip select transfer mode

Input mode

CS0 High level width

t

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100

SCK0 cycle time

tKCY

SCK0

SI0

Output mode

Input mode

SCK0

t

KH,

KL

High, Low level width

t

Output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

SI0 input setup time

t

SIK

(for SCK0 ↑)

200

tsys + 200

100

SI0 input hold time

KSI

SI0

(for SCK0 ↑)

tsys + 200

100

SCK0 ↓ → SO0

KSO

SO0

delay time

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the

clock control register (address: 00FEH).

tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)

Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.

– 13 –

CXP84120/84124

tWHCS

CS0

0.8VDD

0.2VDD

tKCY

tDCSK

tDCSKF

tKL

tKH

0.8VDD

0.2VDD

SCK0

tSIK tKSI

0.8VDD

0.2VDD

Input

data

SI0

tDCSO

tKSO

tDCSOF

0.8VDD

Output data

SO0

0.2VDD

Fig. 4. Serial transfer CH0 timing

– 14 –

CXP84120/84124

Serial transfer (CH1)

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

Symbol

Condition

Input mode

Min.

1000

Max.

Unit

ns

SCK1 cycle time

t

KCY

SCK1

Output mode

16000/fc

400

Input mode

SCK1

t

KH,

KL

SCK1

SI1

High, Low level width

Output mode

8000/fc – 50

100

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SI1 input setup time

t

SIK

(for SCK1 ↑)

200

SI1 input hold time

KSI

SI1

(for SCK1 ↑)

100

200

100

SCK1 ↓ → SO1 delay time

KSO

SO1

Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.

tKCY

tKL

tKH

SCK1

0.8VDD

0.2VDD

tSIK

tKSI

0.8VDD

0.2VDD

Input data

SI1

tKSO

0.8VDD

Output data

SO1

0.2VDD

Fig. 5. Serial transfer CH1 timing

– 15 –

CXP84120/84124

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)

Item

Resolution

Symbol

Condition

Min.

Typ.

Max.

8

Unit

Bits

LSB

±5

Linearity error

Ta = 25°C

V^DD= 5.0V

VSS = AVSS = 0V

1

VZT

–10

70

150

mV

Zero transition voltage

Full-scale transition

voltage

2

VFT

4930

5050

5120

3

160/fADC

12/fADC

µs

V

Conversion time

t

CONV

SAMP

3

Sampling time

AVREF

VDD – 0.5

0

VDD

AVREF

1.0

Reference input voltage

Analog input voltage

VREF

VIAN

IREF

AN0 to AN7

V

0.6

Operation mode

mA

Sleep mode

Stop mode

AV^REFcurrent

AVREF

IREFS

10

µA

32kHz operation mode

FFH

FEH

1

VZT : Value at which the digital conversion value changes

from 00H to 01H and vice versa.

2

3

VFT : Value at which the digital conversion value changes

from FEH to FFH and vice versa.

fADC indicates the below values due to ADC operation

clock selection.

Linearity error

During PS2 selection, fADC = fc/2

01H

00H

VZT

During PS1 selection, fADC = fc

VFT

Analog input

Fig. 6. Definition of A/D converter terms

– 16 –

CXP84120/84124

(4) Interruption, reset input

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

Symbol

Pins

INT0

Condition Min.

Max.

Unit

INT1

External interruption

High, Low level width

t

IH

IL

INT2

INT3

NMI

1

µs

PJ0 to PJ7

Reset input Low level width

8/fc

µs

t

RSL

RST

tIH

tIL

0.8VDD

INT0

0.2VDD

INT1

INT2

tIL

tIH

INT3

NMI

(NMI specifies only for

the falling edge.)

Fig 7. Interruption input timing

tRSL

RST

0.2VDD

Fig. 8. RST input timing

– 17 –

CXP84120/84124

Appendix

(i) Main clock

(ii) Main clock

EXTAL

(iii) Sub clock

ETXETXAL

EXTAL

XTAL

XTXAL

Rd

C1

C2

C1

C2

C1 C2

Fig. 9. SPC700 series recommended oscillation circuit

Circuit

example

Manufacturer

Model

fc (MHz)

C1 (pF)

C2 (pF)

CSA4.19MG

CSA8.00MG

CSA10.0MT

4.19

8.00

(i)

MURATA

MFG

10.00

30

CST4.19MGW

CST8.00MTW

CST10.00MTW

4.19

8.00

CO., LTD.

(ii)

(i)

10.00

4.19

RIVER

ELETEC

CORPORATION

HC-49/U03

15

27

15

27

8.00

10.00

4.19

KINSEKI

LTD.

HC-49/U (-S)

8.00

10.00

Those marked with an asterisk ( ) signify types with built-in ground capacitance (C¹, C2).

Mask option table

Content

Non-existent Existent

Item

Reset pin pull-up resistance

– 18 –

CXP84120/84124

Package Outline

Unit: mm

80PIN QFP (PLASTIC)

23.9 ± 0.4

+ 0.1

0.15 – 0.05

+ 0.4

20.0 – 0.1

0.15

64

41

65

40

A

+ 0.2

0.1 – 0.05

80

25

1

24

+ 0.15

+ 0.35

2.75 – 0.15

0.8

0.35 – 0.1

M

0.2

0° to 10°

DETAIL A

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

SOLDER PLATING

SONY CODE

EIAJ CODE

QFP-80P-L01

QFP080-P-1420

42/COPPER ALLOY

1.6g

JEDEC CODE

PACKAGE MASS

– 19 –

型号:	CXP84124
生命周期：	Obsolete
IHS 制造商：	SONY CORP
包装说明：	QFP,
Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01
风险等级：	5.84
具有ADC：	YES
地址总线宽度：
位大小：	8
最大时钟频率：	10 MHz
DAC 通道：	NO
DMA 通道：	NO
外部数据总线宽度：
JESD-30 代码：	R-PQFP-G80
I/O 线路数量：	70
端子数量：	80
最高工作温度：	75 °C
最低工作温度：	-20 °C
PWM 通道：	YES
封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP
封装形状：	RECTANGULAR
封装形式：	FLATPACK
认证状态：	Not Qualified
ROM可编程性：	MROM
速度：	10 MHz
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL EXTENDED
端子形式：	GULL WING
端子位置：	QUAD
uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

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