欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • CY14B101LA-SZ25XI
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • CY14B101LA-SZ25XI图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • CY14B101LA-SZ25XI 现货库存
  • 数量26980 
  • 厂家CYPRESS 
  • 封装TSOP-32 
  • 批号新年份 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • CY14B101LA-SZ25XI图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • CY14B101LA-SZ25XI 现货库存
  • 数量6980 
  • 厂家CYPRESS 
  • 封装TSOP-32 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • CY14B101LA-SZ25XI图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CY14B101LA-SZ25XI
  • 数量9689 
  • 厂家CYPRESS(赛普拉斯) 
  • 封装
  • 批号23+ 
  • 原厂直销,现货供应,账期支持!
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • CY14B101LA-SZ25XI图
  • 集好芯城

     该会员已使用本站13年以上
  • CY14B101LA-SZ25XI
  • 数量12666 
  • 厂家CYPRESS/赛普拉斯 
  • 封装SOP32 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • CY14B101LA-SZ25XI图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CY14B101LA-SZ25XI
  • 数量8048 
  • 厂家CYPRESS 
  • 封装SOP32 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • CY14B101LA-SZ25XI图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • CY14B101LA-SZ25XI
  • 数量3000 
  • 厂家Cypress 
  • 封装32-SOIC 
  • 批号24+ 
  • 授权分销 现货热卖
  • QQ:1950791264QQ:1950791264 复制
    QQ:2216987084QQ:2216987084 复制
  • 0755-83222787 QQ:1950791264QQ:2216987084
  • CY14B101LA-SZ25XI图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CY14B101LA-SZ25XI
  • 数量100000 
  • 厂家CYPRESS 
  • 封装N/A 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • CY14B101LA-SZ25XIT图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • CY14B101LA-SZ25XIT
  • 数量
  • 厂家CYPRESS 
  • 封装32-SOIC 
  • 批号16+ 
  • 特价,原装正品,绝对公司现货库存,原装特价!
  • QQ:2880824479QQ:2880824479 复制
  • 010-62104891 QQ:2880824479
  • CY14B101LA-SZ25XIT图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CY14B101LA-SZ25XIT
  • 数量5000 
  • 厂家Cypress 
  • 封装32-SOIC 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • CY14B101LA-SZ25XI图
  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
  • CY14B101LA-SZ25XI
  • 数量3373 
  • 厂家Cypress 
  • 封装原厂封装 
  • 批号22+ 
  • 原装正品★真实库存★价格优势★欢迎来电洽谈
  • QQ:1686616797QQ:1686616797 复制
    QQ:2440138151QQ:2440138151 复制
  • 0755-22655674 QQ:1686616797QQ:2440138151
  • CY14B101LA-SZ25XI图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • CY14B101LA-SZ25XI
  • 数量13880 
  • 厂家Cypress(赛普拉斯) 
  • 封装SOIC-32 
  • 批号21+ 
  • 公司只售原装 支持实单
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • CY14B101LA-SZ25XI图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • CY14B101LA-SZ25XI
  • 数量865000 
  • 厂家CYPRESS 
  • 封装原厂封装 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • CY14B101LA-SZ25XI图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CY14B101LA-SZ25XI
  • 数量25113 
  • 厂家CYPRESS 
  • 封装SOP32 
  • 批号2023+ 
  • 绝对原装正品全新进口深圳现货
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • CY14B101LA-SZ25XI图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • CY14B101LA-SZ25XI
  • 数量3577 
  • 厂家CYPRESS 
  • 封装SOIC 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • CY14B101LA-SZ25XI图
  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • CY14B101LA-SZ25XI
  • 数量22500 
  • 厂家Cypress(赛普拉斯) 
  • 封装32-SOIC(0.295,7.50mm 宽) 
  • 批号2年内 
  • 原厂渠道 正品保障 长期供应
  • QQ:2355734291QQ:2355734291 复制
  • -0755-88604592 QQ:2355734291
  • CY14B101LA-SZ25XIT图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • CY14B101LA-SZ25XIT
  • 数量3000 
  • 厂家CYPRESS 
  • 封装N/A 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507168QQ:2355507168 复制
    QQ:2355507169QQ:2355507169 复制
  • 86-755-83219286 QQ:2355507168QQ:2355507169
  • CY14B101LA-SZ25XI图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • CY14B101LA-SZ25XI
  • 数量82000 
  • 厂家CYPRESS 
  • 封装NA 
  • 批号2023+ 
  • 原装原包现货支持实单
  • QQ:2885134554QQ:2885134554 复制
    QQ:2885134398QQ:2885134398 复制
  • 0755-22669259 QQ:2885134554QQ:2885134398
  • CY14B101LA-SZ25XI图
  • 深圳市和谐世家电子有限公司

     该会员已使用本站13年以上
  • CY14B101LA-SZ25XI
  • 数量399 
  • 厂家Cypress Semiconductor Corp 
  • 封装32-SOIC 
  • 批号最新批号 
  • 只做进口原装
  • QQ:1158840606QQ:1158840606 复制
  • 0755+84501032 QQ:1158840606
  • CY14B101LA-SZ25XI图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • CY14B101LA-SZ25XI
  • 数量85000 
  • 厂家Cypress(赛普拉斯) 
  • 封装32-SOIC(0.295,7.50mm 宽) 
  • 批号2023+ 
  • 原装现货特价
  • QQ:2885134398QQ:2885134398 复制
    QQ:2885134554QQ:2885134554 复制
  • 0755- QQ:2885134398QQ:2885134554
  • CY14B101LA-SZ25XI图
  • 深圳市惠诺德电子有限公司

     该会员已使用本站7年以上
  • CY14B101LA-SZ25XI
  • 数量29500 
  • 厂家Cypress Semiconductor Corp 
  • 封装IC NVSRAM 1MBIT PARALLEL 32SOIC 
  • 批号21+ 
  • 只做原装现货代理
  • QQ:1211267741QQ:1211267741 复制
    QQ:1034782288QQ:1034782288 复制
  • 159-7688-9073 QQ:1211267741QQ:1034782288
  • CY14B101LA-SZ25XI图
  • 深圳市恒嘉威智能科技有限公司

     该会员已使用本站7年以上
  • CY14B101LA-SZ25XI
  • 数量25000 
  • 厂家CYPRESS 
  • 封装SOP-32 
  • 批号21+ 
  • 原装正品价格绝对优势
  • QQ:1036846627QQ:1036846627 复制
    QQ:2274045202QQ:2274045202 复制
  • -0755-23942980 QQ:1036846627QQ:2274045202
  • CY14B101LA-SZ25XI图
  • 深圳市芯捷微半导体有限公司

     该会员已使用本站1年以上
  • CY14B101LA-SZ25XI
  • 数量35601 
  • 厂家CYPRESS/赛普拉斯 
  • 封装SOP32 
  • 批号23+ 
  • 芯捷微原厂原装正品热卖
  • QQ:3004285388QQ:3004285388 复制
  • 16625139831 QQ:3004285388
  • CY14B101LA-SZ25XI图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • CY14B101LA-SZ25XI
  • 数量50000 
  • 厂家CYPRESS/赛普拉斯 
  • 封装NA 
  • 批号24+ 
  • 公司原装现货可含税!假一罚十!
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • CY14B101LA-SZ25XI图
  • 深圳市珩瑞科技有限公司

     该会员已使用本站2年以上
  • CY14B101LA-SZ25XI
  • 数量850 
  • 厂家CYPRESS 
  • 封装ssop 
  • 批号21+ 
  • 只做原装正品,支持实单
  • QQ:2938238007QQ:2938238007 复制
    QQ:1840507767QQ:1840507767 复制
  • -0755-82578309 QQ:2938238007QQ:1840507767
  • CY14B101LA-SZ25XI图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • CY14B101LA-SZ25XI
  • 数量660000 
  • 厂家Cypress Semiconductor Corp 
  • 封装原厂原装 
  • 批号23+ 
  • 支持实单/只做原装
  • QQ:3008961398QQ:3008961398 复制
  • 0755-21006672 QQ:3008961398
  • CY14B101LA-SZ25XIT图
  • 深圳市诚达吉电子有限公司

     该会员已使用本站2年以上
  • CY14B101LA-SZ25XIT
  • 数量5429 
  • 厂家CYPRESS 
  • 封装N/A 
  • 批号2024+ 
  • 原装正品 一手现货 假一赔百
  • QQ:2881951980QQ:2881951980 复制
  • 15873513267 QQ:2881951980
  • CY14B101LA-SZ25XI图
  • 深圳市特拉特科技有限公司

     该会员已使用本站2年以上
  • CY14B101LA-SZ25XI
  • 数量15000 
  • 厂家CYPRESS 
  • 封装SOP32 
  • 批号22+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
  • QQ:709809857QQ:709809857 复制
  • 0755-82531732 QQ:709809857
  • CY14B101LA-SZ25XI图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • CY14B101LA-SZ25XI
  • 数量6500000 
  • 厂家赛普拉斯 
  • 封装原厂原装 
  • 批号22+ 
  • 万三科技 秉承原装 实单可议
  • QQ:3008961396QQ:3008961396 复制
  • 0755-21008751 QQ:3008961396
  • CY14B101LA-SZ25XI图
  • 北京云中青城科技有限公司

     该会员已使用本站8年以上
  • CY14B101LA-SZ25XI
  • 数量9000 
  • 厂家Cypress 
  • 封装SOIC-32 
  • 批号20+ 
  • 只做原装.诚信经营
  • QQ:1290208342QQ:1290208342 复制
    QQ:260779663QQ:260779663 复制
  • 010-62669145 QQ:1290208342QQ:260779663
  • CY14B101LA-SZ25XI图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • CY14B101LA-SZ25XI
  • 数量6980 
  • 厂家CYPRESS 
  • 封装TSOP-32 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • CY14B101LA-SZ25XI图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • CY14B101LA-SZ25XI
  • 数量32222 
  • 厂家CYPRESS/赛普拉斯 
  • 封装SOP32 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • CY14B101LA-SZ25XI图
  • 深圳市炎凯科技有限公司

     该会员已使用本站7年以上
  • CY14B101LA-SZ25XI
  • 数量6267 
  • 厂家CYPRESS 
  • 封装SOP 
  • 批号24+ 
  • 原装现货
  • QQ:354696650QQ:354696650 复制
    QQ:2850471056QQ:2850471056 复制
  • 0755-89587732 QQ:354696650QQ:2850471056
  • CY14B101LA-SZ25XI图
  • 深圳市瑞天芯科技有限公司

     该会员已使用本站7年以上
  • CY14B101LA-SZ25XI
  • 数量20000 
  • 厂家CYPRESS 
  • 封装SOP 
  • 批号22+ 
  • 深圳现货库存,保证原装正品
  • QQ:1940213521QQ:1940213521 复制
  • 15973558688 QQ:1940213521
  • CY14B101LA-SZ25XI图
  • 深圳市恒意创鑫电子有限公司

     该会员已使用本站10年以上
  • CY14B101LA-SZ25XI
  • 数量9000 
  • 厂家CYPRESS/赛普拉斯 
  • 封装SOP32 
  • 批号22+ 
  • 全新原装公司现货,支持实单
  • QQ:1493457560QQ:1493457560 复制
  • 0755-83235429 QQ:1493457560
  • CY14B101LA-SZ25XI图
  • 深圳市创思克科技有限公司

     该会员已使用本站2年以上
  • CY14B101LA-SZ25XI
  • 数量76 
  • 厂家CYPRESS/赛普拉斯 
  • 封装SOP32 
  • 批号18+ 
  • 全新原装挺实单欢迎来撩/可开票
  • QQ:1092793871QQ:1092793871 复制
  • -0755-88910020 QQ:1092793871
  • CY14B101LA-SZ25XI图
  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
  • CY14B101LA-SZ25XI
  • 数量9978 
  • 厂家Cypress Semiconductor Corp 
  • 封装 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921
  • CY14B101LA-SZ25XIT图
  • 深圳市一线半导体有限公司

     该会员已使用本站15年以上
  • CY14B101LA-SZ25XIT
  • 数量7457 
  • 厂家Cypress Semiconductor Corp 
  • 封装 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921
  • CY14B101LA-SZ25XI图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • CY14B101LA-SZ25XI
  • 数量98500 
  • 厂家CYPRESS/赛普拉斯 
  • 封装SOP32 
  • 批号23+ 
  • 真实库存全新原装正品!专业配单
  • QQ:308365177QQ:308365177 复制
  • 0755-13418564337 QQ:308365177
  • CY14B101LA-SZ25XI图
  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
  • CY14B101LA-SZ25XI
  • 数量284 
  • 厂家CYPRESS 
  • 封装SOP-32 
  • 批号24+ 
  • ★体验愉快问购元件!!就找我吧!单价:278元
  • QQ:97671956QQ:97671956 复制
  • 171-4729-1886(微信同号) QQ:97671956

产品型号CY14B101LA-SZ25XI的概述

CY14B101LA-SZ25XI 概述 CY14B101LA-SZ25XI 是一家集成电路制造商 Cypress Semiconductor(现为 Infineon Technologies 的一部分)推出的一款非易失性存储芯片。此芯片基于 CMOS(互补金属氧化物半导体)技术,兼具快速存取速率和优越的数据保留能力,适用于各种嵌入式应用。 非易失性存储器的主要特点是即使在断电的情况下也能保持数据,这是许多工业和消费类电子设备所需求的功能。CY14B101LA-SZ25XI 提供了在低功耗模式下的稳定性和灵活性,使得其成为传感器、智能设备以及其它需要可靠数据存储的应用的理想选择。 该芯片的详细参数显示出其在数据存储、访问时间以及功耗方面的优势,这些特性使得其具有广泛的应用前景。 详细参数 CY14B101LA-SZ25XI 的关键技术参数包括: - 存储容量:1兆位(1Mb) - 存储...

产品型号CY14B101LA-SZ25XI的Datasheet PDF文件预览

PRELIMINARY  
CY14B101LA, CY14B101NA  
1 Mbit (128K x 8/64K x 16) nvSRAM  
Features  
Functional Description  
20 ns, 25 ns, and 45 ns Access Times  
The Cypress CY14B101LA/CY14B101NA is a fast static RAM,  
with a nonvolatile element in each memory cell. The memory is  
Internally Organized as 128K x 8 (CY14B101LA) or 64K x 16  
(CY14B101NA)  
organized as 128K bytes of 8 bits each or 64K words of 16 bits  
each. The embedded nonvolatile elements incorporate  
QuantumTrap technology, producing the world’s most reliable  
nonvolatile memory. The SRAM provides infinite read and write  
cycles, while independent nonvolatile data resides in the highly  
reliable QuantumTrap cell. Data transfers from the SRAM to the  
nonvolatile elements (the STORE operation) takes place  
automatically at power down. On power up, data is restored to  
the SRAM (the RECALL operation) from the nonvolatile memory.  
Both the STORE and RECALL operations are also available  
under software control.  
Hands off Automatic STORE on Power Down with only a Small  
Capacitor  
STORE to QuantumTrap Nonvolatile Elements Initiated by  
Software, Device Pin, or AutoStore on Power Down  
RECALL to SRAM Initiated by Software or Power Up  
Infinite Read, Write, and Recall Cycles  
200,000 STORE Cycles to QuantumTrap  
20 year Data Retention  
Single 3V +20% to -10% Operation  
Commercial and Industrial Temperatures  
54/44-Pin TSOP-II, 48-Pin SSOP, and 32-Pin SOIC Packages  
Pb-free and RoHS Compliance  
Logic Block Diagram[1, 2, 3]  
9&$3  
9&&  
4XDWUXPꢀ7UDS  
ꢁꢂꢃꢄꢀ;ꢀꢁꢂꢃꢄ  
5
2
:
$
32:(5  
&21752/  
$
6725(  
$
5(&$//  
$
'
(
&
2
'
(
5
6725(ꢅ5(&$//  
&21752/  
$
+6%  
67$7,&ꢀ5$0  
$55$<  
ꢁꢂꢃꢄꢀ;ꢀꢁꢂꢃꢄ  
$
ꢁꢃ  
$
ꢁꢆ  
$
ꢁꢈ  
$
ꢁꢄ  
62)7:$5(  
'(7(&7  
$
$ꢁꢄꢀꢇꢀ$ꢃ  
ꢁꢉ  
'4ꢂ  
'4ꢁ  
'4ꢃ  
'4ꢆ  
'4ꢄ  
,
1
3
8
7
%
8
)
)
(
5
6
'4ꢈ  
'4ꢉ  
'4ꢊ  
&2/801ꢀ,ꢅ2  
'4ꢋ  
'4ꢌ  
'4ꢁꢂ  
2(  
&2/801ꢀ'(&  
:(  
'4ꢁꢁ  
'4ꢁꢃ  
'4ꢁꢆ  
'4ꢁꢄ  
&(  
%/(  
$
$
$
$
$
$
$
ꢁꢂ ꢁꢁ  
'4ꢁꢈ  
%+(  
Notes  
1. Address A - A for x8 configuration and Address A - A for x16 configuration.  
0
16  
0
15  
2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.  
0
7
0
15  
3. BHE and BLE are applicable for x16 configuration only.  
Cypress Semiconductor Corporation  
Document #: 001-42879 Rev. *C  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised July 09, 2009  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Pinouts  
Figure 1. Pin Diagram - 44 Pin TSOP II  
A
A
1
NC  
NC  
1
0
NC  
NC  
44  
43  
42  
41  
1
2
44  
43  
42  
41  
HSB  
NC  
[7]  
2
3
4
5
6
7
8
[5]  
[4]  
[6]  
A
A
3
4
5
6
7
8
2
NC  
NC  
NC  
A
0
15  
A
3
A
1
OE  
A
4
A
2
BHE  
40  
39  
40  
39  
[5]  
CE  
A
3
A
BLE  
DQ  
16  
[4]  
DQ  
38  
37  
36  
35  
A
4
38  
37  
36  
35  
34  
0
1
2
3
A
15  
15  
DQ  
CE  
DQ  
DQ  
DQ  
OE  
14  
13  
44 - TSOP II  
DQ  
DQ  
DQ  
V
9
10  
44 - TSOP II  
9
DQ  
DQ  
V
0
1
7
[8]  
(x8)  
DQ  
V
10  
11  
12  
(x16)  
12  
6
11  
12  
13  
14  
15  
16  
CC  
34  
33  
32  
31  
V
SS  
CC  
SS  
Top View  
(not to scale)  
V
Top View  
(not to scale)  
SS  
V
V
V
33  
32  
31  
CC  
SS  
CC  
DQ  
DQ  
DQ  
DQ  
13  
14  
DQ  
4
5
11  
2
3
5
DQ  
DQ  
DQ  
DQ  
DQ  
V
10  
4
WE  
A
5
15  
16  
17  
18  
6
7
30  
29  
28  
27  
26  
25  
24  
23  
DQ  
DQ  
30  
29  
28  
27  
26  
25  
24  
23  
9
8
CAP  
A
14  
A
6
17  
18  
WE  
A
V
13  
12  
CAP  
A
A
7
5
A
14  
A
A
6
A
19  
20  
21  
22  
19  
20  
21  
22  
A
8
A
13  
11  
A
9
A
7
A
A
12  
10  
A
8
NC  
NC  
A
NC  
NC  
11  
A
9
A
10  
Figure 2. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC  
V
CAP  
48  
47  
V
CC  
1
2
3
A
16  
A
15  
A
14  
46  
45  
44  
43  
42  
HSB  
WE  
A
12  
4
A
7
5
A
A
13  
A
6
6
8
A
5
A
9
7
NC  
A
4
8
41  
40  
NC  
A
11  
9
48-SSOP  
NC  
NC  
NC  
10  
11  
12  
39  
NC  
NC  
NC  
V
SS  
NC  
NC  
38  
37  
36  
Top View  
(not to scale)  
V
SS  
13  
14  
15  
16  
17  
18  
NC  
35  
NC  
DQ0  
34  
33  
32  
31  
DQ6  
OE  
A
3
A
2
A
10  
A
A
0
1
19  
20  
21  
22  
23  
24  
30  
29  
28  
CE  
DQ7  
DQ1  
DQ2  
NC  
DQ5  
DQ4  
DQ3  
27  
26  
25  
NC  
V
CC  
Notes  
4. Address expansion for 2 Mbit. NC pin not connected to die.  
5. Address expansion for 4 Mbit. NC pin not connected to die.  
6. Address expansion for 8 Mbit. NC pin not connected to die.  
7. Address expansion for 16 Mbit. NC pin not connected to die.  
8. HSB pin is not available in 44-TSOP II (x16) package.  
Document #: 001-42879 Rev. *C  
Page 2 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Pinouts (continued)  
Figure 3. Pin Diagram - 54-Pin TSOP II  
NC  
54  
53  
52  
51  
50  
49  
HSB  
1
2
3
[7]  
[6]  
NC  
A
0
NC  
NC  
NC  
[5]  
[4]  
A
1
4
A
2
A
15  
5
6
A
3
OE  
48  
47  
46  
45  
A
4
BHE  
BLE  
DQ  
7
8
9
10  
11  
12  
13  
14  
CE  
DQ  
DQ  
0
1
15  
DQ  
DQ  
DQ  
V
14  
13  
12  
54 - TSOP II  
(x16)  
DQ  
DQ  
44  
43  
42  
41  
40  
39  
2
3
V
CC  
SS  
Top View  
V
SS  
V
CC  
(not to scale)  
DQ  
DQ  
DQ  
DQ  
4
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
11  
10  
DQ  
5
38  
37  
36  
35  
DQ  
DQ  
6
7
9
8
DQ  
V
WE  
A
5
CAP  
A
14  
34  
33  
32  
31  
30  
29  
28  
A
6
A
13  
A
A
7
A
8
12  
A
11  
A
A
9
10  
NC  
NC  
NC  
NC  
NC  
NC  
25  
26  
27  
Table 1. Pin Definitions  
Pin Name  
A0 – A16  
I/O Type  
Description  
Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration.  
Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.  
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation.  
Input  
A0 – A15  
DQ0 – DQ7  
DQ0 – DQ15  
Input/Output  
Input  
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on  
operation.  
WE  
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written  
to the specific address location.  
Input  
Input  
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.  
CE  
OE  
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read  
cycles. I/O pins are tristated on deasserting OE HIGH.  
Input  
Input  
Byte High Enable, Active LOW. Controls DQ15 - DQ8.  
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.  
BHE  
BLE  
VSS  
Ground  
Ground for the Device. Must be connected to the ground of the system.  
Power Supply Inputs to the Device. 3.0V +20%, –10%  
VCC  
Power  
Supply  
HSB[8]  
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.  
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up  
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is  
driven HIGH for short time with standard output high current.  
VCAP  
NC  
Power  
Supply  
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to  
nonvolatile elements.  
No Connect No Connect. This pin is not connected to the die.  
Document #: 001-42879 Rev. *C  
Page 3 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Note If the capacitor is not connected to VCAP pin, AutoStore  
must be disabled using the soft sequence specified in Preventing  
AutoStore on page 6. In case AutoStore is enabled without a  
capacitor on VCAP pin, the device attempts an AutoStore  
operation without sufficient charge to complete the Store. This  
may corrupt the data stored in nvSRAM.  
Device Operation  
The CY14B101LA/CY14B101NA nvSRAM is made up of two  
functional components paired in the same physical cell. They are  
an SRAM memory cell and a nonvolatile QuantumTrap cell. The  
SRAM memory cell operates as a standard fast static RAM. Data  
in the SRAM is transferred to the nonvolatile cell (the STORE  
operation), or from the nonvolatile cell to the SRAM (the RECALL  
operation). Using this unique architecture, all cells are stored and  
recalled in parallel. During the STORE and RECALL operations,  
SRAM read and write operations are inhibited. The  
CY14B101LA/CY14B101NA supports infinite reads and writes  
similar to a typical SRAM. In addition, it provides infinite RECALL  
operations from the nonvolatile cells and up to 200K STORE  
operations. Refer to the Truth Table For SRAM Operations on  
page 16 for a complete description of read and write modes.  
Figure 4 shows the proper connection of the storage capacitor  
(VCAP) for automatic STORE operation. Refer to DC Electrical  
Characteristics on page 8 for the size of VCAP. The voltage on  
the VCAP pin is driven to VCC by a regulator on the chip. Place a  
pull up on WE to hold it inactive during power up. This pull up is  
only effective if the WE signal is tristate during power up. Many  
MPUs tristate their controls on power up. This must be verified  
when using the pull up. When the nvSRAM comes out of  
power-on-recall, the MPU must be active or the WE held inactive  
until the MPU comes out of reset.  
SRAM Read  
To reduce unnecessary nonvolatile stores, AutoStore and  
Hardware STORE operations are ignored unless at least one  
write operation has taken place since the most recent STORE or  
RECALL cycle. Software initiated STORE cycles are performed  
regardless of whether a write operation has taken place. The  
HSB signal is monitored by the system to detect if an AutoStore  
cycle is in progress.  
The CY14B101LA/CY14B101NA performs a read cycle when  
CE and OE are LOW and WE and HSB are HIGH. The address  
specified on pins A0-16 or A0-15 determines which of the 131,072  
data bytes or 65,536 words of 16 bits each are accessed. Byte  
enables (BHE, BLE) determine which bytes are enabled to the  
output, in the case of 16-bit words. When the read is initiated by  
an address transition, the outputs are valid after a delay of tAA  
(read cycle 1). If the read is initiated by CE or OE, the outputs  
are valid at tACE or at tDOE, whichever is later (read cycle 2). The  
data output repeatedly responds to address changes within the  
tAA access time without the need for transitions on any control  
input pins. This remains valid until another address change or  
until CE or OE is brought HIGH, or WE or HSB is brought LOW.  
Figure 4. AutoStore Mode  
Vcc  
0.1uF  
Vcc  
SRAM Write  
A write cycle is performed when CE and WE are LOW and HSB  
is HIGH. The address inputs must be stable before entering the  
write cycle and must remain stable until CE or WE goes HIGH at  
the end of the cycle. The data on the common I/O pins DQ0–15  
are written into the memory if the data is valid tSD before the end  
of a WE-controlled write or before the end of a CE-controlled  
write. The Byte Enable inputs (BHE, BLE) determine which bytes  
are written, in the case of 16-bit words. Keep OE HIGH during  
the entire write cycle to avoid data bus contention on common  
I/O lines. If OE is left LOW, internal circuitry turns off the output  
buffers tHZWE after WE goes LOW.  
WE  
VCAP  
VCAP  
VSS  
Hardware STORE Operation  
The CY14B101LA/CY14B101NA provides the HSB[8] pin to  
control and acknowledge the STORE operations. Use the HSB  
pin to request a Hardware STORE cycle. When the HSB pin is  
driven LOW, the CY14B101LA/CY14B101NA conditionally  
initiates a STORE operation after tDELAY. An actual STORE cycle  
only begins if a write to the SRAM has taken place since the last  
STORE or RECALL cycle. The HSB pin also acts as an open  
drain driver that is internally driven LOW to indicate a busy  
condition when the STORE (initiated by any means) is in  
progress.  
AutoStore Operation  
The CY14B101LA/CY14B101NA stores data to the nvSRAM  
using one of the following three storage operations: Hardware  
STORE activated by HSB; Software STORE activated by an  
address sequence; AutoStore on device power down. The  
AutoStore operation is a unique feature of QuantumTrap  
technology  
and  
is  
enabled  
by  
default  
on  
the  
CY14B101LA/CY14B101NA.  
SRAM write operations that are in progress when HSB is driven  
LOW by any means are given time (tDELAY) to complete before  
the STORE operation is initiated. However, any SRAM write  
cycles requested after HSB goes LOW are inhibited until HSB  
returns HIGH. In case the write latch is not set, HSB is not driven  
LOW by the CY14B101LA/CY14B101NA. But any SRAM read  
and write cycles are inhibited until HSB is returned HIGH by MPU  
or other external source.  
During a normal operation, the device draws current from VCC to  
charge a capacitor connected to the VCAP pin. This stored  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the VCC pin drops below VSWITCH, the part  
automatically disconnects the VCAP pin from VCC. A STORE  
operation is initiated with power provided by the VCAP capacitor.  
Document #: 001-42879 Rev. *C  
Page 4 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
During any STORE operation, regardless of how it is initiated,  
the CY14B101LA/CY14B101NA continues to drive the HSB pin  
LOW, releasing it only when the STORE is complete. Upon  
The software sequence may be clocked with CE controlled reads  
or OE controlled reads, with WE kept HIGH for all the six READ  
sequences. After the sixth address in the sequence is entered,  
the STORE cycle commences and the chip is disabled. HSB is  
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is  
activated again for the read and write operation.  
completion  
of  
the  
STORE  
operation,  
the  
CY14B101LA/CY14B101NA remains disabled until the HSB pin  
returns HIGH. Leave the HSB unconnected if it is not used.  
Hardware RECALL (Power Up)  
Software RECALL  
During power up or after any low power condition  
(VCC< VSWITCH), an internal RECALL request is latched. When  
VCC again exceeds the sense voltage of VSWITCH, a RECALL  
cycle is automatically initiated and takes tHRECALL to complete.  
During this time, HSB is driven low by the HSB driver.  
Data is transferred from nonvolatile memory to the SRAM by a  
software address sequence. A Software RECALL cycle is  
initiated with a sequence of read operations in a manner similar  
to the Software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled read operations must be  
performed:  
Software STORE  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x4C63 Initiate RECALL Cycle  
Data is transferred from SRAM to the nonvolatile memory by a  
software address sequence. The CY14B101LA/CY14B101NA  
Software STORE cycle is initiated by executing sequential CE  
controlled read cycles from six specific address locations in  
exact order. During the STORE cycle an erase of the previous  
nonvolatile data is first performed, followed by a program of the  
nonvolatile elements. After a STORE cycle is initiated, further  
input and output are disabled until the cycle is completed.  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared. Next, the nonvolatile information is transferred into the  
SRAM cells. After the tRECALL cycle time, the SRAM is again  
ready for read and write operations. The RECALL operation  
does not alter the data in the nonvolatile elements.  
Because a sequence of READs from specific addresses is used  
for STORE initiation, it is important that no other read or write  
accesses intervene in the sequence, or the sequence is aborted  
and no STORE or RECALL takes place.  
To initiate the Software STORE cycle, the following read  
sequence must be performed:  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x8FC0 Initiate STORE Cycle  
Table 2. Mode Selection  
[9]  
A15 - A0  
Mode  
I/O  
Power  
Standby  
Active  
CE  
WE  
OE, BHE, BLE[3]  
H
X
X
X
X
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
L
L
L
H
L
L
X
L
Active  
Active[10]  
H
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8B45  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Disable  
Notes  
9. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A - A ) are used to control software modes.  
14  
2
Rest of the address lines are don’t care.  
10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.  
Document #: 001-42879 Rev. *C  
Page 5 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Table 2. Mode Selection (continued)  
[9]  
OE, BHE, BLE[3]  
A15 - A0  
Mode  
I/O  
Power  
CE  
WE  
L
H
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4B46  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore Enable  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active[10]  
[10]  
L
L
H
H
L
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
STORE  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active ICC2  
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
Recall  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active[10]  
If the AutoStore function is disabled or reenabled, a manual  
STORE operation (Hardware or Software) must be issued to  
save the AutoStore state through subsequent power down  
cycles. The part comes from the factory with AutoStore enabled.  
Preventing AutoStore  
The AutoStore function is disabled by initiating an AutoStore  
disable sequence. A sequence of read operations is performed  
in a manner similar to the Software STORE initiation. To initiate  
the AutoStore disable sequence, the following sequence of CE  
controlled read operations must be performed:  
Data Protection  
The CY14B101LA/CY14B101NA protects data from corruption  
during low voltage conditions by inhibiting all externally initiated  
STORE and write operations. The low voltage condition is  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x8B45 AutoStore Disable  
detected when VCC is less than VSWITCH  
.
If the  
CY14B101LA/CY14B101NA is in a write mode (both CE and WE  
are LOW) at power up, after a RECALL or STORE, the write is  
inhibited until the SRAM is enabled after tLZHSB (HSB to output  
active). This protects against inadvertent writes during power up  
or brown out conditions.  
The AutoStore is reenabled by initiating an AutoStore enable  
sequence. A sequence of read operations is performed in a  
manner similar to the Software RECALL initiation. To initiate the  
AutoStore enable sequence, the following sequence of CE  
controlled read operations must be performed:  
Noise Considerations  
Refer to CY application note AN1064.  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x4B46 AutoStore Enable  
Document #: 001-42879 Rev. *C  
Page 6 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state (for example, autostore enabled). While  
the nvSRAM is shipped in a preset state, best practice is to  
again rewrite the nvSRAM into the desired state as a safeguard  
against events that might flip the bit inadvertently such as  
program bugs and incoming inspection routines.  
Best Practices  
nvSRAM products have been used effectively for over 15 years.  
While ease-of-use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
The VCAP value specified in this data sheet includes a minimum  
and a maximum value size. Best practice is to meet this  
requirement and not exceed the maximum VCAP value because  
the nvSRAM internal algorithm calculates VCAP charge and  
discharge time based on this max VCAP value. Customers that  
want to use a larger VCAP value to make sure there is extra store  
charge and store time should discuss their VCAP size selection  
withCypresstounderstandanyimpactontheVCAP voltagelevel  
at the end of a tRECALL period.  
ThenonvolatilecellsinthisnvSRAMproductaredeliveredfrom  
Cypress with 0x00 written in all cells. Incoming inspection  
routines at customer or contract manufacturer’s sites  
sometimes reprogram these values. Final NV patterns are  
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End  
product’s firmware should not assume an NV array is in a set  
programmed state. Routines that check memory content  
values to determine first time system configuration, cold or  
warm boot status, and so on should always program a unique  
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex  
or more random bytes) as part of the final system manufac-  
turing test to ensure these system routines work consistently.  
Document #: 001-42879 Rev. *C  
Page 7 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Package Power Dissipation  
Capability (TA = 25°C)....................................................1.0W  
Maximum Ratings  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Surface Mount Pb Soldering  
Temperature (3 Seconds)...........................................+260°C  
Storage Temperature ...................................65°C to +150°C  
Maximum Accumulated Storage Time:  
DC Output Current (1 output at a time, 1s duration)......15 mA  
Static Discharge Voltage ......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
At 150°C Ambient Temperature........................ 1000h  
At 85°C Ambient Temperature..................... 20 Years  
Ambient Temperature with Power Applied ..–55°C to +150°C  
Supply Voltage on VCC Relative to GND.......... –0.5V to 4.1V  
Voltage Applied to Outputs in High-Z State –0.5V to VCC + 0.5V  
Input Voltage ............................................0.5V to Vcc+0.5V  
Latch Up Current................................................... > 200 mA  
Operating Range  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
2.7V to 3.6V  
–40°C to +85°C  
Transient Voltage (<20 ns) on  
Any Pin to Ground Potential.................. –2.0V to VCC + 2.0V  
DC Electrical Characteristics  
Over the Operating Range (VCC = 2.7V to 3.6V)  
Parameter  
VCC  
Description  
Test Conditions  
Min  
Typ[11]  
3.0  
Max  
Unit  
Power Supply Voltage  
2.7  
3.6  
V
ICC1  
Average VCC Current tRC = 20 ns  
Commercial  
Industrial  
65  
65  
50  
mA  
mA  
mA  
t
t
RC = 25 ns  
RC = 45 ns  
Values obtained without output loads  
(IOUT = 0 mA)  
70  
70  
52  
mA  
mA  
mA  
ICC2  
ICC3  
Average VCC Current All Inputs Don’t Care, VCC = Max  
10  
mA  
during STORE  
AverageVCC Currentat All I/P cycling at CMOS levels.  
tRC= 200 ns, Values obtained without output loads (IOUT = 0 mA)  
CC (Typ), 25°C  
Average current for duration tSTORE  
35  
mA  
V
ICC4  
ISB  
Average VCAP Current All Inputs Don’t Care, VCC = Max  
during AutoStore Cycle Average current for duration tSTORE  
5
5
mA  
mA  
VCC Standby Current CE > (VCC – 0.2V). VIN < 0.2V or > (VCC – 0.2V).  
Standby current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz  
[12]  
IIX  
Input Leakage Current VCC = Max, VSS < VIN < VCC  
(except HSB)  
–1  
–100  
–1  
+1  
+1  
+1  
µA  
µA  
µA  
Input Leakage Current VCC = Max, VSS < VIN < VCC  
(for HSB)  
IOZ  
Off-State Output  
Leakage Current  
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or  
BHE/BLE > VIH or WE < VIL  
VIH  
Input HIGH Voltage  
Input LOW Voltage  
2.0  
Vss–0.5  
2.4  
VCC+0.5  
0.8  
V
V
VIL  
VOH  
VOL  
VCAP  
Output HIGH Voltage IOUT = –2 mA  
V
Output LOW Voltage  
Storage Capacitor  
IOUT = 4 mA  
0.4  
V
Between VCAP pin and VSS, 5V Rated  
61  
68  
180  
µF  
Notes  
11. Typical values are at 25°C, V = V (Typ). Not 100% tested.  
CC  
CC  
12. The HSB pin has I  
= -2 uA for V of 2.4V when both active high and low drivers are disabled. When they are enabled standard V and V are valid. This  
OUT  
O
H
O
H
O
L
parameter is characterized but not tested.  
Document #: 001-42879 Rev. *C  
Page 8 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Data Retention and Endurance  
Parameter  
Description  
Min  
20  
Unit  
Years  
K
DATAR  
NVC  
Data Retention  
Nonvolatile STORE Operations  
200  
Capacitance  
Parameter[13]  
Description  
Test Conditions  
Max  
7
Unit  
pF  
CIN  
Input Capacitance  
Output Capacitance  
TA = 25°C, f = 1 MHz,  
CC = VCC (Typ)  
V
COUT  
7
pF  
Thermal Resistance  
Parameter[13]  
Description  
Test Conditions  
54-TSOP II 48-SSOP 44-TSOP II 32-SOIC  
Unit  
ΘJA  
Thermal Resistance Test conditions follow standard  
(Junction to Ambient) test methods and procedures for  
30.73  
TBD  
31.11  
TBD  
°C/W  
measuring thermal impedance,  
in accordance with EIA/JESD51.  
(Junction to Case)  
ΘJC  
Thermal Resistance  
6.08  
TBD  
5.56  
TBD  
°C/W  
Figure 5. AC Test Loads  
577Ω  
R1  
for tristate specs  
577Ω  
3.0V  
3.0V  
OUTPUT  
R1  
OUTPUT  
R2  
789Ω  
R2  
789Ω  
5 pF  
30 pF  
AC Test Conditions  
Input Pulse Levels ....................................................0V to 3V  
Input Rise and Fall Times (10% - 90%)........................ <3 ns  
Input and Output Timing Reference Levels .................... 1.5V  
Note  
13. These parameters are guaranteed by design and are not tested.  
Document #: 001-42879 Rev. *C  
Page 9 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
AC Switching Characteristics  
Parameters  
20 ns  
25 ns  
45 ns  
Description  
Unit  
Cypress  
Parameters  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
Parameters  
SRAM Read Cycle  
tACE  
tACS  
tRC  
Chip Enable Access Time  
Read Cycle Time  
20  
25  
45  
ns  
ns  
[14]  
20  
25  
45  
tRC  
[15]  
tAA  
tOE  
tOH  
tLZ  
Address Access Time  
20  
10  
25  
12  
45  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
tDOE  
[15]  
3
3
3
3
3
3
tOHA  
[13, 16]  
tLZCE  
tHZCE  
tLZOE  
[13, 16]  
[13, 16]  
[13, 16]  
tHZ  
tOLZ  
tOHZ  
tPA  
8
8
10  
10  
15  
15  
0
0
0
0
0
0
tHZOE  
[13]  
tPU  
[13]  
tPS  
20  
10  
25  
12  
45  
20  
tPD  
[13]  
tDBE[  
-
-
-
Byte Enable to Data Valid  
Byte Enable to Output Active  
Byte Disable to Output Inactive  
ns  
ns  
ns  
[13]  
[13]  
tLZBE  
0
0
0
tHZBE  
8
10  
15  
SRAM Write Cycle  
tWC  
tPWE  
tSCE  
tSD  
tHD  
tAW  
tSA  
tWC  
Write Cycle Time  
Write Pulse Width  
20  
15  
15  
8
0
15  
0
25  
20  
20  
10  
0
20  
0
0
45  
30  
30  
15  
0
30  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tWP  
tCW  
tDW  
tDH  
tAW  
tAS  
tWR  
tWZ  
tOW  
-
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
tHA  
0
[13, 16,17]  
8
10  
15  
tHZWE  
[13, 16]  
Output Active after End of Write  
Byte Enable to End of Write  
3
3
3
ns  
ns  
tLZWE  
tBW  
15  
20  
30  
Switching Waveforms  
Figure 6. SRAM Read Cycle #1: Address Controlled [14, 15, 18]  
tRC  
Address  
Address Valid  
tAA  
Output Data Valid  
Previous Data Valid  
tOHA  
Data Output  
Notes  
14. WE must be HIGH during SRAM read cycles.  
15. Device is continuously selected with CE, OE and BHE/BLE LOW.  
16. Measured ±200 mV from steady state output voltage.  
17. If WE is low when CE goes low, the outputs remain in the high impedance state.  
18. HSB must remain HIGH during Read and Write cycles.  
Document #: 001-42879 Rev. *C  
Page 10 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 14, 18]  
Address  
CE  
Address Valid  
tRC  
tHZCE  
tACE  
tAA  
tLZCE  
tHZOE  
tDOE  
OE  
tHZBE  
tLZOE  
tDBE  
BHE, BLE  
tLZBE  
High Impedance  
Standby  
Data Output  
Output Data Valid  
tPU  
tPD  
Active  
ICC  
Figure 8. SRAM Write Cycle #1: WE Controlled [3, 17, 18, 21]  
tWC  
Address  
Address Valid  
tSCE  
tHA  
CE  
tBW  
BHE, BLE  
tAW  
tPWE  
WE  
Data Input  
Data Output  
tSA  
tHD  
tSD  
Input Data Valid  
tLZWE  
tHZWE  
High Impedance  
Previous Data  
Note  
21. CE or WE must be > V during address transitions.  
IH  
Document #: 001-42879 Rev. *C  
Page 11 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Figure 9. SRAM Write Cycle #2: CE Controlled [3, 17, 18, 21]  
tWC  
Address Valid  
Address  
tSA  
tSCE  
tHA  
CE  
tBW  
BHE, BLE  
tPWE  
WE  
tHD  
tSD  
Input Data Valid  
Data Input  
High Impedance  
Data Output  
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 17, 18, 21]  
tWC  
Address  
CE  
Address Valid  
tSCE  
tSA  
tHA  
tBW  
BHE, BLE  
WE  
tAW  
tPWE  
tSD  
tHD  
Data Input  
Input Data Valid  
High Impedance  
Data Output  
Document #: 001-42879 Rev. *C  
Page 12 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
AutoStore/Power Up RECALL  
20 ns  
25 ns  
45 ns  
Parameters  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
[27]  
Power Up RECALL Duration  
STORE Cycle Duration  
20  
8
20  
20  
ms  
ms  
ns  
V
tHRECALL  
[23]  
8
8
tSTORE  
[24]  
Time Allowed to Complete SRAM Write Cycle  
Low Voltage Trigger Level  
VCC Rise Time  
20  
25  
25  
tDELAY  
2.65  
2.65  
2.65  
VSWITCH  
[13]  
150  
150  
150  
µs  
V
tVCCRISE  
[13]  
HSB Output Disable Voltage  
1.9  
1.9  
1.9  
VHDIS  
[13]  
tLZHSB  
HSB To Output Active Time  
HSB High Active Time  
5
5
5
µs  
ns  
[13]  
tHHHD  
500  
500  
500  
Switching Waveforms  
Figure 11. AutoStore or Power Up RECALL[27]  
VCC  
VSWITCH  
VHDIS  
23  
Note  
23  
VVCCRISE  
tSTORE  
tSTORE  
26  
Note  
Note  
tHHHD  
tHHHD  
HSB OUT  
AutoStore  
tDELAY  
tLZHSB  
tLZHSB  
tDELAY  
POWER-  
UP  
RECALL  
tHRECALL  
tHRECALL  
Read & Write  
Inhibited  
(RWI)  
Read & Write  
Read & Write  
POWER-UP  
RECALL  
BROWN  
OUT  
AutoStore  
POWER  
DOWN  
AutoStore  
POWER-UP  
RECALL  
Notes  
22. t  
starts from the time V rises above V  
SWITCH.  
HRECALL  
CC  
23. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.  
24. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time t  
.
DELAY  
25. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V  
SWITCH.  
26. HSB pin is driven high to VCC only by internal 100 kΩ resistor, HSB driver is disabled.  
Document #: 001-42879 Rev. *C  
Page 13 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Software Controlled STORE/RECALL Cycle  
20 ns  
25 ns  
Max  
45 ns  
Max  
Parameters[27, 28]  
Description  
Unit  
Min  
Max  
Min  
Min  
tRC  
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
20  
25  
45  
ns  
ns  
ns  
ns  
µs  
tSA  
0
15  
0
0
20  
0
0
30  
0
tCW  
Clock Pulse Width  
tHA  
Address Hold Time  
tRECALL  
RECALL Duration  
200  
200  
200  
Switching Waveforms  
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[28]  
tRC  
tRC  
Address  
CE  
Address #1  
tCW  
Address #6  
tCW  
tSA  
tHA  
tHA  
tHA  
tSA  
tHA  
OE  
tHHHD  
tHZCE  
HSB (STORE only)  
DQ (DATA)  
29  
Note  
tDELAY  
tLZCE  
tLZHSB  
High Impedance  
tSTORE/tRECALL  
RWI  
Figure 13. Autostore Enable/Disable Cycle  
tRC  
tRC  
Address  
Address #1  
Address #6  
tCW  
tSA  
tCW  
CE  
OE  
tHA  
tHA  
tHA  
tSA  
tHA  
tSS  
tHZCE  
29  
Note  
tLZCE  
tDELAY  
DQ (DATA)  
Notes  
27. The software sequence is clocked with CE controlled or OE controlled reads.  
28. The six consecutive addresses must be read in the order listed in Table 2 on page 5. WE must be HIGH during all six consecutive cycles.  
29. DQ output data at the sixth read may be invalid since the output is disabled at t  
time.  
DELAY  
Document #: 001-42879 Rev. *C  
Page 14 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Hardware STORE Cycle  
20 ns  
25 ns  
45 ns  
Parameters  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
tDHSB  
tPHSB  
HSB To Output Active Time when write latch not set  
Hardware STORE Pulse Width  
20  
25  
25  
ns  
ns  
μs  
15  
15  
15  
[29, 30]  
tSS  
Soft Sequence Processing Time  
100  
100  
100  
Switching Waveforms  
Figure 14. Hardware STORE Cycle[23]  
Write latch set  
tPHSB  
HSB (IN)  
tSTORE  
tHHHD  
tDELAY  
HSB (OUT)  
DQ (Data Out)  
RWI  
tLZHSB  
Write latch not set  
tPHSB  
HSB pin is driven high to VCC only by Internal  
100kOhm resistor,  
HSB (IN)  
HSB driver is disabled  
SRAM is disabled as long as HSB (IN) is driven low.  
tDELAY  
tDHSB  
tDHSB  
HSB (OUT)  
RWI  
Figure 15. Soft Sequence Processing[29, 30]  
tSS  
tSS  
Soft Sequence  
Command  
Soft Sequence  
Command  
Address  
Address #1  
tSA  
Address #6  
tCW  
Address #1  
Address #6  
tCW  
CE  
VCC  
Notes  
29. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.  
30. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.  
Document #: 001-42879 Rev. *C  
Page 15 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Truth Table For SRAM Operations  
HSB must remain HIGH for SRAM operations.  
Table 3. Truth Table for x8 Configuration  
CE  
H
L
WE  
X
OE  
X
Inputs/Outputs[2]  
Mode  
Deselect/Power Down  
Power  
High Z  
Data Out (DQ0–DQ7);  
Standby  
Active  
Active  
Active  
H
L
Read  
L
H
H
High Z  
Output Disabled  
Write  
L
L
X
Data in (DQ0–DQ7);  
Table 4. Truth Table for x16 Configuration  
CE  
H
L
WE  
X
OE  
X
BHE[3] BLE[3]  
Inputs/Outputs[2]  
High-Z  
Mode  
Power  
X
H
L
X
H
L
Deselect/Power Down  
Output Disabled  
Read  
Standby  
Active  
Active  
Active  
X
X
High-Z  
L
H
L
Data Out (DQ0–DQ15)  
L
H
L
H
L
Data Out (DQ0–DQ7);  
DQ8–DQ15 in High-Z  
Read  
L
H
L
L
H
Data Out (DQ8–DQ15);  
DQ0–DQ7 in High-Z  
Read  
Active  
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z  
High-Z  
High-Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active  
Active  
Active  
Active  
Active  
L
Data In (DQ0–DQ15)  
L
H
Data In (DQ0–DQ7);  
DQ8–DQ15 in High-Z  
Write  
L
L
X
L
H
Data In (DQ8–DQ15);  
DQ0–DQ7 in High-Z  
Write  
Active  
Document #: 001-42879 Rev. *C  
Page 16 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Part Numbering Nomenclature  
CY 14 B 101L A-ZS P 20 X C T  
Option:  
T - Tape and Reel  
Blank - Std.  
Temperature:  
C - Commercial (0 to 70°C)  
I - Industrial (–40 to 85°C)  
Speed:  
Pb-Free  
20 - 20 ns  
25 - 25 ns  
45 - 45 ns  
P - 54 Pin  
Blank - 32/44/48  
Package:  
ZS - 44 TSOP II  
SP - 48 SSOP  
SZ - 32 SOIC  
Die revision:  
Blank: No Rev  
A - 1st Rev  
Data Bus:  
L - x8  
N - x16  
Density:  
101 - 1 Mb  
Voltage:  
B - 3.0V  
NVSRAM  
14 - AutoStore + Software STORE + Hardware STORE  
Cypress  
Document #: 001-42879 Rev. *C  
Page 17 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Ordering Information  
Speed  
Package  
Operating  
Ordering Code  
Package Type  
(ns)  
Diagram  
51-85087  
51-85087  
51-85061  
51-85061  
51-85127  
51-85127  
51-85087  
51-85087  
51-85160  
51-85160  
51-85087  
51-85087  
51-85061  
51-85061  
51-85127  
51-85127  
51-85087  
51-85087  
51-85160  
51-85160  
51-85087  
51-85087  
51-85061  
51-85061  
51-85127  
51-85127  
51-85087  
51-85087  
51-85160  
51-85160  
51-85087  
51-85087  
51-85061  
51-85061  
51-85127  
51-85127  
51-85087  
51-85087  
51-85160  
51-85160  
Range  
20  
CY14B101LA-ZS20XCT  
CY14B101LA-ZS20XC  
CY14B101LA-SP20XCT  
CY14B101LA-SP20XC  
CY14B101LA-SZ20XCT  
CY14B101LA-SZ20XC  
CY14B101NA-ZS20XCT  
CY14B101NA-ZS20XC  
CY14B101NA-ZSP20XCT  
CY14B101NA-ZSP20XC  
CY14B101LA-ZS20XIT  
CY14B101LA-ZS20XI  
CY14B101LA-SP20XIT  
CY14B101LA-SP20XI  
CY14B101LA-SZ20XIT  
CY14B101LA-SZ20XI  
CY14B101NA-ZS20XIT  
CY14B101NA-ZS20XI  
CY14B101NA-ZSP20XIT  
CY14B101NA-ZSP20XI  
CY14B101LA-ZS25XCT  
CY14B101LA-ZS25XC  
CY14B101LA-SP25XCT  
CY14B101LA-SP25XC  
CY14B101LA-SZ25XCT  
CY14B101LA-SZ25XC  
CY14B101NA-ZS25XCT  
CY14B101NA-ZS25XC  
CY14B101NA-ZSP25XCT  
CY14B101NA-ZSP25XC  
CY14B101LA-ZS25XIT  
CY14B101LA-ZS25XI  
CY14B101LA-SP25XIT  
CY14B101LA-SP25XI  
CY14B101LA-SZ25XIT  
CY14B101LA-SZ25XI  
CY14B101NA-ZS25XIT  
CY14B101NA-ZS25XI  
CY14B101NA-ZSP25XIT  
CY14B101NA-ZSP25XI  
44-pin TSOP II  
44-pin TSOP II  
48-pin SSOP  
48-pin SSOP  
32-pin SOIC  
Commercial  
32-pin SOIC  
44-pin TSOP II  
44-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-pin SSOP  
48-pin SSOP  
32-pin SOIC  
Industrial  
Commercial  
Industrial  
32-pin SOIC  
44-pin TSOP II  
44-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-pin SSOP  
48-pin SSOP  
32-pin SOIC  
25  
32-pin SOIC  
44-pin TSOP II  
44-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-pin SSOP  
48-pin SSOP  
32-pin SOIC  
32-pin SOIC  
44-pin TSOP II  
44-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
Document #: 001-42879 Rev. *C  
Page 18 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Ordering Information (continued)  
Speed  
Package  
Operating  
Ordering Code  
(ns)  
Package Type  
Diagram  
51-85087  
51-85087  
51-85061  
51-85061  
51-85127  
51-85127  
51-85087  
51-85087  
51-85160  
51-85160  
51-85087  
51-85087  
51-85061  
51-85061  
51-85127  
51-85127  
51-85087  
51-85087  
51-85160  
51-85160  
Range  
45  
CY14B101LA-ZS45XCT  
CY14B101LA-ZS45XC  
CY14B101LA-SP45XCT  
CY14B101LA-SP45XC  
CY14B101LA-SZ45XCT  
CY14B101LA-SZ45XC  
CY14B101NA-ZS45XCT  
CY14B101NA-ZS45XC  
CY14B101NA-ZSP45XCT  
CY14B101NA-ZSP45XC  
CY14B101LA-ZS45XIT  
CY14B101LA-ZS45XI  
CY14B101LA-SP45XIT  
CY14B101LA-SP45XI  
CY14B101LA-SZ45XIT  
CY14B101LA-SZ45XI  
CY14B101NA-ZS45XIT  
CY14B101NA-ZS45XI  
CY14B101NA-ZSP45XIT  
CY14B101NA-ZSP45XI  
44-pin TSOP II  
44-pin TSOP II  
48-pin SSOP  
48-pin SSOP  
32-pin SOIC  
Commercial  
32-pin SOIC  
44-pin TSOP II  
44-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-pin SSOP  
48-pin SSOP  
32-pin SOIC  
Industrial  
32-pin SOIC  
44-pin TSOP II  
44-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
All parts are Pb-free. This table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts.  
Document #: 001-42879 Rev. *C  
Page 19 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Package Diagrams  
Figure 16. 44-Pin TSOP II (51-85087)  
DIMENSION IN MM (INCH)  
MAX  
MIN.  
PIN 1 I.D.  
22  
1
R
O
E
K
A
X
S G  
EJECTOR PIN  
23  
44  
TOP VIEW  
BOTTOM VIEW  
10.262 (0.404)  
10.058 (0.396)  
0.400(0.016)  
0.300 (0.012)  
0.800 BSC  
(0.0315)  
BASE PLANE  
0.10 (.004)  
0.210 (0.0083)  
0.120 (0.0047)  
0°-5°  
18.517 (0.729)  
18.313 (0.721)  
0.597 (0.0235)  
0.406 (0.0160)  
SEATING  
PLANE  
51-85087-*A  
Document #: 001-42879 Rev. *C  
Page 20 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Package Diagrams (continued)  
Figure 17. 48-Pin SSOP (51-85061)  
51-85061 *C  
Figure 18. 32-Pin SOIC (51-85127)  
Document #: 001-42879 Rev. *C  
Page 21 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Package Diagrams (continued)  
Figure 19. 54-Pin TSOP II (51-85160)  
51-85160-**  
Document #: 001-42879 Rev. *C  
Page 22 of 24  
[+] Feedback  
CY14B101LA, CY14B101NA  
PRELIMINARY  
Document History Page  
Document Title: CY14B101LA, CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM  
Document Number: 001-42879  
Submission  
Date  
Orig. of  
Change  
Rev. ECN No.  
Description of Change  
**  
2050747  
See ECN  
UNC/PYRS  
New Data Sheet  
*A  
2607447 11/14/2008  
GVCH/AESA Removed 15 ns access speed  
Updated “Features”  
Updated Logic block diagram  
Added footnote 1 2, 3 and 7  
Pin definition: Updated WE, HSB and NC pin description  
Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description  
Updated Figure 4  
Page 4: Updated Hardware store operation and Hardware RECALL (Power  
up)description  
Page 4: Updated Software store and software recall description  
Footnote 1 and 11 referenced for Mode selection Table  
Added footnote 11  
Updated footnote 9 and 10  
Page 6: updated Data protection description  
Maximum Ratings:Added Max. Accumulated storage time  
Changed Output short circuit current parameter name to DC output current  
Changed ICC2 from 6mA to 10mA  
Changed ICC3 from 15mA to 35mA  
Changed ICC4 from 6mA to 5mA  
Changed ISB from 3mA to 5mA  
Added IIX for HSB  
Updated ICC1, CC3, SB and IOZ Test conditions  
I
I
Changed VCAP voltage min value from 68uF to 61uF  
Added VCAP voltage max value to 180uF  
Updated footnote 12 and 13  
Added footnote 14  
Added Data retention and Endurance Table  
Added thermal resistance value to 48-pin FBGA and 44-pin TSOP II packages  
Updated Input Rise and Fall time in AC test Conditions  
Referenced footnote 17 to tOHA parameter  
Updated All switching waveforms  
Updated footnote 17  
Added footnote 20  
Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled)  
Changed tSTORE max value from 12.5ms to 8ms  
Updated tDELAY value  
Added VHDIS, tHHHD and tLZHSB parameters  
Updated footnote 24  
Added footnote 26 and 27  
Software controlled STORE/RECALL Table: Changed tAS to tSA  
Changed tGHAX to tHA  
Changed tHA value from 1ns to 0 ns  
Added Figure 13  
Added tDHSB parameter  
Changed tHLHX to tPHSB  
Updated tSS from 70us to 100us  
Added truth table for SRAM operations  
Updated ordering information and part numbering nomenclature  
*B  
2654484  
02/05/09  
GVCH/PYRS Changed the data sheet from Advance information to Preliminary  
Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, HZOE, LZWE  
t
t
and tHZWE  
Updated Figure 12  
Document #: 001-42879 Rev. *C  
Page 23 of 24  
[+] Feedback  
PRELIMINARY  
CY14B101LA, CY14B101NA  
Document Title: CY14B101LA, CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM  
Document Number: 001-42879  
Submission  
Date  
Orig. of  
Change  
Rev. ECN No.  
*C 2733909  
Description of Change  
07/09/09  
GVCH/AESA Removed 48-ball FBGA package and added 54-pin TSOP II Package  
Corrected typo error in pin diagram of 48-pin SSOP  
Page 4; Added note to AutoStore Operation description  
Page 4; Updated Hardware STORE (HSB) Operation description  
Page 5; Updated Software STORE Operation description  
Added best practices  
Updated VHDIS parameter description  
Updated tDELAY parameter description  
Updated footnote 24 and added footnote 29  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at www.cypress.com/sales.  
Products  
PSoC  
psoc.cypress.com  
clocks.cypress.com  
wireless.cypress.com  
memory.cypress.com  
image.cypress.com  
Clocks & Buffers  
Wireless  
Memories  
Image Sensors  
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 001-42879 Rev. *C  
Revised July 09, 2009  
Page 24 of 24  
All products and company names mentioned in this document are the trademarks of their respective holders.  
[+] Feedback  
配单直通车
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!