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产品型号CY2305SI-1H的概述

CY2305SI-1H 概述 CY2305SI-1H 是一种来自芯片制造商 Cypress Semiconductor 的时钟发生器。该芯片被广泛应用于数据通讯、计算机和其它电子设备中。其主要功能是生成稳定的时钟信号，以便为各种数字电路提供同步时钟源。时钟信号是现代电子设备中必不可少的组成部分，它保证了不同组件之间的协调工作，从而提高了系统的整体性能。详细参数 CY2305SI-1H 的具体参数如下： - 工作电压：3.3V 和 2.5V - 工作频率范围：8MHz 到 133MHz - 输出信号类型：CMOS / LVTTL - 最大输出频率：可达 133MHz - 输出驱动能力：可连接到多个负载 - 相位噪声：典型值较低，表明信号稳定性好 - 最大功耗：约 150mA，具体取决于工作状态 - 环境温度范围：-40°C 到 +85°C 这些参数使得 CY2305SI-1H 成为一个...

产品型号CY2305SI-1H的Datasheet PDF文件预览

CY2305

CY2309

Low-cost 3.3V Zero Delay Buffer

up to 100-/133-MHz frequencies, and have higher drive than

the -1 devices. All parts have on-chip PLLs which lock to an

input clock on the REF pin. The PLL feedback is on-chip and

is obtained from the CLKOUT pad.

Features

• 10-MHz to 100-/133-MHz operating range, compatible

with CPU and PCI bus frequencies

• Zero input-output propagation delay

• Multiple low-skew outputs

The CY2309 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the “Select Input

Decoding” table on page 2. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the

input clock to be directly applied to the outputs for chip and

system testing purposes.

— Output-output skew less than 250 ps

— Device-device skew less than 700 ps

— One input drives five outputs (CY2305)

The CY2305 and CY2309 PLLs enter a power-down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off, resulting

in less than 12.0 µA of current draw for commercial temper-

ature devices and 25.0 µA for industrial temperature parts. The

CY2309 PLL shuts down in one additional case as shown in

the table below.

— One input drives nine outputs, grouped as 4 + 4 + 1

(CY2309)

• Less than 200 ps cycle-cycle jitter, compatible with

Pentium -based systems

• Test Mode to bypass phase-locked loop (PLL) (CY2309

only [see “Select Input Decoding” on page 2])

Multiple CY2305 and CY2309 devices can accept the same

input clock and distribute it. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

• Available in space-saving 16-pin 150-mil SOIC or

4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil

SOIC package (CY2305)

All outputs have less than 200 ps of cycle-cycle jitter. The input

to output propagation delay on both devices is guaranteed to

be less than 350 ps, and the output to output skew is

guaranteed to be less than 250 ps.

• 3.3V operation

• Industrial temperature available

Functional Description

The CY2305/CY2309 is available in two/three different config-

urations, as shown in the ordering information (page 10). The

CY2305-1/CY2309-1 is the base part. The CY2305-1H/

CY2309-1H is the high-drive version of the -1, and its rise and

fall times are much faster than the -1s.

The CY2309 is a low-cost 3.3V zero delay buffer designed to

distribute high-speed clocks and is available in a 16-pin SOIC

or TSSOP package. The CY2305 is an 8-pin version of the

CY2309. It accepts one reference input, and drives out five

low-skew clocks. The -1H versions of each device operate at

Block Diagram

Pin Configuration

SOIC/TSSOP

Top View

CLKOUT

PLL

MUX

REF

CLKOUT

REF

CLKA1

CLKA2

CLKA1

CLKA4

CLKA3

CLKA2

GND

CLKA3

CLKA4

CLKB4

CLKB3

CLKB1

CLKB2

2309-2

CLKB1

CLKB2

CLKB3

CLKB4

SOIC

Top View

Select Input

Decoding

CLKOUT

CLK4

REF

CLK2

CLK1

GND

2309-3

2309-1

CLK3

Cypress Semiconductor Corporation

Document #: 38-07140 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised December 14, 2002

CY2305

CY2309

Pin Description for CY2309

Signal

Description

Input reference frequency, 5V-tolerant input

REF^[1]

CLKA1^[2]

CLKA2^[2]

V_DD

Buffered clock output, Bank A

3.3V supply

GND

Ground

CLKB1^[2]

CLKB2^[2]

S2^[3]

Buffered clock output, Bank B

Select input, bit 2

S1^[3]

Select input, bit 1

CLKB3^[2]

CLKB4^[2]

GND

Buffered clock output, Bank B

Ground

V_DD

CLKA3^[2]

CLKA4^[2]

CLKOUT^[2]

3.3V supply

Buffered clock output, Bank A

Buffered output, internal feedback on this pin

Pin Description for CY2305

Signal

Description

Input reference frequency, 5V-tolerant input

Buffered clock output

REF^[1]

CLK2^[2]

CLK1^[2]

GND

Buffered clock output

Ground

CLK3^[2]

Buffered clock output

V_DD

3.3V supply

CLK4^[2]

Buffered clock output

CLKOUT^[2]

Buffered clock output, internal feedback on this pin

Select Input Decoding for CY2309

CLOCK A1–A4

Three-state

Driven

CLOCK B1–B4

Three-state

Driven

CLKOUT^[4]

Driven

Output Source

PLL

PLL Shutdown

Driven

PLL

Driven

Reference

PLL

Driven

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-ups on these inputs.

4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.

Document #: 38-07140 Rev. *C

Page 2 of 13

CY2305

CY2309

REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins

Zero Delay and Skew Control

All outputs should be uniformly loaded to achieve Zero Delay

between the input and output. Since the CLKOUT pin is the

internal feedback to the PLL, its relative loading can adjust the

input-output delay. This is shown in the above graph.

other outputs, for obtaining zero input-output delay. If input to

output delay adjustments are required, use the above graph to

calculate loading differences between the CLKOUT pin and

other outputs.

For applications requiring zero input-output delay, all outputs,

including CLKOUT, must be equally loaded. Even if CLKOUT

is not used, it must have a capacitive load, equal to that on

For zero output-output skew, be sure to load all outputs

equally. For further information refer to the application note

entitled “CY2305 and CY2309 as PCI and SDRAM Buffers.”

Document #: 38-07140 Rev. *C

Page 3 of 13

CY2305

CY2309

Maximum Ratings

Supply Voltage to Ground Potential............... –0.5V to +7.0V

DC Input Voltage (Except REF) ............–0.5V to V_DD+ 0.5V

DC Input Voltage REF......................................... –0.5V to 7V

Storage Temperature .................................–65°C to +150°C

Junction Temperature................................................. 150°C

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ...........................> 2,000V

Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices

Parameter

Description

Min.

3.0

Max.

3.6

Unit

V_DD

Supply Voltage

T_A

Operating Temperature (Ambient Temperature)

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance

°C

C_L

C_IN

Power-up time for all VDD's to reach minimum specified voltage

(power ramps must be monotonic)

t_PU

0.05

Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices

Parameter

Description

Input LOW Voltage^[5]

Input HIGH Voltage^[5]

Input LOW Current

Input HIGH Current

Output LOW Voltage^[6]

Test Conditions

Min.

Max.

Unit

V_IL

V_IH

I_IL

0.8

2.0

V_IN= 0V

50.0

100.0

0.4

µA

I_IH

V_IN= V_DD

V_OL

I_OL= 8 mA (–1)

_{OH =}12 mA (–1H)

I_OH= –8 mA (–1)

_OL= –12 mA (–1H)

Power Down Supply Current REF = 0 MHz

Supply Current Unloaded outputs at 66.67 MHz,

SEL inputs at V_DD

V_OH

Output HIGH Voltage^[6]

2.4

I_DD(PD mode)

I_DD

12.0

32.0

µA

Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices^[7]

Parameter

Name

Test Conditions

Min.

Typ.

Max.

Unit

Output Frequency

30-pF load

10-pF load

100

133.33

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

Fall Time^[6]

Measured at 1.4V, F_out= 66.67 MHz

Measured between 0.8V and 2.0V

All outputs equally loaded

40.0

50.0

60.0

2.50

250

t₄

t₅

Output to Output Skew^[6]

t_6A

Delay, REF Rising Edge to Measured at V_DD/2

CLKOUT Rising Edge^[6]

±350

t_6B

t₇

Delay, REF Rising Edge to Measured at V_DD/2. Measured in PLL

8.7

CLKOUT Rising Edge^[6]

Bypass Mode, CY2309 device only.

Device to Device Skew^[6]Measuredat V_DD/2ontheCLKOUT pins

of devices

700

t_J

Cycle to Cycle Jitter^[6]

PLL Lock Time^[6]

Measured at 66.67 MHz, loaded outputs

200

1.0

t_LOCK

Stable power supply, valid clock

presented on REF pin

Notes:

5. REF input has a threshold voltage of V_DD/2.

6. Parameter is guaranteed by design and characterization. Not 100% tested in production.

7. All parameters specified with loaded outputs.

Document #: 38-07140 Rev. *C

Page 4 of 13

CY2305

CY2309

Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices^[7]

Parameter

Name

Description

Min.

Typ.

Max.

Unit

Output Frequency

30-pF load

10-pF load

100

133.33

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

Fall Time^[6]

Output to Output Skew^[6]

Measured at 1.4V, F_out= 66.67 MHz

Measured at 1.4V, F_out<50.0 MHz

Measured between 0.8V and 2.0V

All outputs equally loaded

40.0

45.0

50.0

60.0

55.0

1.50

250

t₄

t₅

t_6A

Delay, REF Rising Edge to Measured at V_DD/2

CLKOUT Rising Edge^[6]

±350

t_6B

t₇

Delay, REF Rising Edge to Measured at V_DD/2. Measured in PLL

8.7

CLKOUT Rising Edge^[6]

Bypass Mode, CY2309 device only.

Device to Device Skew^[6]Measuredat V_DD/2ontheCLKOUT pins

of devices

Output Slew Rate^[6]

700

t₈

Measured between 0.8V and 2.0V using

Test Circuit #2

V/ns

t_J

Cycle to Cycle Jitter^[6]

PLL Lock Time^[6]

Measured at 66.67 MHz, loaded outputs

200

1.0

t_LOCK

Stable power supply, valid clock

presented on REF pin

Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices

Parameter

Description

Min.

Max.

3.6

Unit

V_DD

T_A

Supply Voltage

3.0

Operating Temperature (Ambient Temperature)

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance

–40

°C

C_L

C_IN

Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices

Parameter

Description

Input LOW Voltage^[5]

Input HIGH Voltage^[5]

Input LOW Current

Test Conditions

Min. Max. Unit

V_IL

V_IH

I_IL

0.8

2.0

V_IN= 0V

50.0

µA

I_IH

Input HIGH Current

Output LOW Voltage^[6]

V_IN= V_DD

100.0 µA

V_OL

I_OL= 8 mA (-1)

0.4

I_OH=12 mA (-1H)

V_OH

Output HIGH Voltage^[6]

I_OH= –8 mA (-1)

I_OL= –12 mA (-1H)

2.4

I_DD(PD mode)

I_DD

Power Down Supply Current

Supply Current

REF = 0 MHz

25.0

35.0

µA

Unloaded outputs at 66.67 MHz, SEL inputs at

V_DD

Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices^[7]

Parameter

Name

Test Conditions

Min.

Typ.

Max.

Unit

Output Frequency

30-pF load

10-pF load

100

133.33

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

Fall Time^[6]

Measured at 1.4V, F_out= 66.67 MHz

Measured between 0.8V and 2.0V

40.0

50.0

60.0

2.50

t₄

Document #: 38-07140 Rev. *C

Page 5 of 13

CY2305

CY2309

Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices^[7]

Parameter

Name

Test Conditions

Min.

Typ.

Max.

250

Unit

t₅

Output to Output Skew^[6]

All outputs equally loaded

t_6A

Delay, REF Rising Edge to Measured at V_DD/2

CLKOUT Rising Edge^[6]

±350

t_6B

Delay, REF Rising Edge to Measured at V_DD/2. Measured in

8.7

CLKOUT Rising Edge^[6]

Device to Device Skew^[6]

Cycle to Cycle Jitter^[6]

PLL Lock Time^[6]

PLL Bypass Mode, CY2309 device

only.

t₇

Measuredat V_DD/2 on the CLKOUT

pins of devices

700

200

1.0

t_J

Measured at 66.67 MHz, loaded

outputs

t_LOCK

Stable power supply, valid clock

presented on REF pin

Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices^[7]

Parameter

Name

Description

Min.

Typ.

Max.

Unit

t₁

Output Frequency

30-pF load

10-pF load

100

133.33

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

Fall Time^[6]

Output to Output Skew^[6]

Measured at 1.4V, F_out= 66.67 MHz

Measured at 1.4V, F_out< 50.0 MHz

Measured between 0.8V and 2.0V

All outputs equally loaded

40.0

45.0

50.0

60.0

55.0

1.50

250

t₃

t₄

t₅

t_6A

Delay, REF Rising Edge to Measured at V_DD/2

CLKOUT Rising Edge^[6]

±350

t_6B

Delay, REF Rising Edge to Measured at V_DD/2. Measured in

8.7

CLKOUT Rising Edge^[6]

Device to Device Skew^[6]

Output Slew Rate^[6]

Cycle to Cycle Jitter^[6]

PLL Lock Time^[6]

PLL Bypass Mode, CY2309 device

only.

t₇

Measured at V_DD/2 on the CLKOUT

pins of devices

700

V/ns

t₈

Measured between 0.8V and 2.0V

using Test Circuit #2

t_J

Measured at 66.67 MHz, loaded

outputs

200

1.0

t_LOCK

Stable power supply, valid clock

presented on REF pin

Switching Waveforms

Duty Cycle Timing

1.4V

Document #: 38-07140 Rev. *C

Page 6 of 13

CY2305

CY2309

Switching Waveforms (continued)

All Outputs Rise/Fall Time

3.3V

2.0V

0.8V

2.0V

0.8V

OUTPUT

Output-Output Skew

1.4V

OUTPUT

1.4V

OUTPUT

Input-Output Propagation Delay

INPUT

OUTPUT

Device-Device Skew

CLKOUT, Device 1

CLKOUT, Device 2

Document #: 38-07140 Rev. *C

Page 7 of 13

CY2305

CY2309

Typical Duty Cycle^[8]and I Trends^[9]for CY2305-1 and CY2309-1

Duty Cycle Vs VDD

(for 30 pF Loads over Frequency - 3.3V, 25C)

(for 15 pF Loads over Frequency - 3.3V, 25C)

33 MHz

66 MHz

100 MHz

133 MHz

33 MHz

66 MHz

100 MHz

3.1

3.2

3.3

3.4

3.5

3.6

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

Duty Cycle Vs Frequency

(for 30 pF Loads over Temperature - 3.3V)

Duty Cycle Vs Frequency

(for 15 pF Loads over Temperature - 3.3V)

-40C

25C

70C

85C

25C

70C

85C

100

120

140

100

120

140

Frequency (MHz)

IDD vs Number of Loaded Outputs

(for 30 pF Loads over Frequency - 3.3V, 25C)

IDD vs Number of Loaded Outputs

(for 15 pF Loads over Frequency - 3.3V, 25C)

140

120

100

140

120

100

33 MHz

66 MHz

100 MHz

33 MHz

66 MHz

100 MHz

# of Loaded Outputs

Notes:

8. Duty Cycle is taken from typical chip measured at 1.4V.

9. _DDdata is calculated from I_DD= I_CORE+ nCVf, where I_COREis the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply

Voltage (V); f = frequency (Hz)).

Document #: 38-07140 Rev. *C

Page 8 of 13

CY2305

CY2309

Typical Duty Cycle^[8]and IDD Trends^[9]for CY2305-1H and CY2309-1H

Duty Cycle Vs VDD

(for 30 pF Loads over Frequency - 3.3V, 25C)

(for 15 pF Loads over Frequency - 3.3V, 25C)

33 MHz

66 MHz

100 MHz

133 MHz

33 MHz

66 MHz

100 MHz

3.1

3.2

3.3

3.4

3.5

3.6

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

Duty Cycle Vs Frequency

(for 30 pF Loads over Temperature - 3.3V)

Duty Cycle Vs Frequency

(for 15 pF Loads over Temperature - 3.3V)

-40C

25C

70C

85C

25C

70C

85C

100

120

140

100

120

140

Frequency (MHz)

IDD vs Number of Loaded Outputs

(for 30 pF Loads over Frequency - 3.3V, 25C)

IDD vs Number of Loaded Outputs

(for 15 pF Loads over Frequency - 3.3V, 25C)

160

140

120

100

160

140

120

100

33 MHz

66 MHz

100 MHz

33 MHz

66 MHz

100 MHz

# of Loaded Outputs

Document #: 38-07140 Rev. *C

Page 9 of 13

CY2305

CY2309

Test Circuits

Test Circuit # 2

Test Circuit # 1

1 kΩ

0.1 µ F

CLK out

0.1 µ F

OUTPUTS

GND

OUTPUTS

10 pF

LOAD

0.1 µ F

GND

0.1 µ F

GND

For parameter t (output slew rate) on -1H devices

Ordering Information

Ordering Code

CY2305SC-1

Package Type

Operating Range

Commercial

8-pin 150-mil SOIC

CY2305SC-1T

CY2305SI-1

8-pin 150-mil SOIC–Tape and Reel

8-pin 150-mil SOIC

Commercial

Industrial

CY2305SI-1T

CY2305SC-1H

CY2305SC-1HT

CY2305SI-1H

CY2305SI-1HT

CY2305ZC-1

8-pin 150-mil SOIC–Tape and Reel

8-pin 150-mil SOIC

Industrial

Commercial

Industrial

8-pin 150-mil SOIC–Tape and Reel

8-pin 150-mil SOIC

8-pin 150-mil SOIC–Tape and Reel

8-pin 150-mil TSSOP

Industrial

Commercial

Industrial

CY2305ZC-1T

CY2309SC-1

8-pin 150-mil TSSOP–Tape and Reel

16-pin 150-mil SOIC

CY2309SC-1T

CY2309SI-1

16-pin 150-mil SOIC–Tape and Reel

16-pin 150-mil SOIC

CY2309SI-1T

CY2309SC-1H

CY2309SC-1HT

CY2309SI-1H

CY2309SI-1HT

CY2309ZC-1H

CY2309ZC-1HT

CY2309ZI-1H

CY2309ZI-1HT

16-pin 150-mil SOIC–Tape and Reel

16-pin 150-mil SOIC

Industrial

Commercial

Industrial

16-pin 150-mil SOIC–Tape and Reel

16-pin 150-mil SOIC

16-pin 150-mil SOIC–Tape and Reel

16-pin 4.4-mm TSSOP

Industrial

Commercial

Industrial

16-pin 4.4-mm TSSOP–Tape and Reel

16-pin 4.4-mm TSSOP

16-pin 4.4-mm TSSOP–Tape and Reel

Industrial

Document #: 38-07140 Rev. *C

Page 10 of 13

CY2305

CY2309

Package Diagrams

8-lead (150-Mil) SOIC S8

51-85066-A

16-lead (150-Mil) Molded SOIC S16

51-85068-A

Document #: 38-07140 Rev. *C

Page 11 of 13

CY2305

CY2309

Package Diagrams (continued)

16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16

51-85091-**

Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the

trademarks of their respective holders.

Document #: 38-07140 Rev. *C

Page 12 of 13

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY2305

CY2309

Document History Page

Document Title: CY2305/CY2309 Low-Cost 3.3V Zero Delay Buffer

Document Number: 38-07140

Orig. of

REV.

ECN NO. Issue Date Change

Description of Change

110249

111117

10/19/01

03/01/02

SZV

CKN

Change from Spec number: 38-00530 to 38-07140

Added t6B row to the Switching Characteristics Table; also added the letter

“A” to the t6A row

Corrected the table title from CY2305SC-IH and CY2309SC-IH to

CY2305SI-IH and CY2309SI-IH

117625

121828

10/21/02

12/14/02

HWT

RBI

Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the

ordering information table.

Added the Tape and Reel option to all the existing packages:

CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT,

CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT,

CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT

Power up requirements added to Operating Conditions Information

Document #: 38-07140 Rev. *C

Page 13 of 13

CY2305SI-1H相关文章

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CY2305SI-1H产品参数

型号:	CY2305SI-1H
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.31.00.01
风险等级：	5.57
系列：	2305
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0
长度：	4.889 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	1
功能数量：	1
反相输出次数：
端子数量：	8
实输出次数：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	220
电源：	3.3 V
传播延迟（tpd）：	8.7 ns
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.25 ns
座面最大高度：	1.727 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.8985 mm
最小 fmax：	133.33 MHz
Base Number Matches：	1

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