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产品型号CY2305SXC-1的概述

CY2305SXC-1芯片概述与应用分析 CY2305SXC-1是由Cypress Semiconductor（赛普拉斯半导体）生产的一款高性能时钟发生器。作为一种集成电路，该芯片旨在满足现代数字系统中对精确时钟信号的广泛需求。它主要被应用于各种电子设备中，尤其是那些对数据传输速率和时序精度要求较高的应用场景，如通信、计算机和各种消费电子产品。CY2305SXC-1的主要功能是提供稳定的时钟信号，同时具备灵活的频率输入和输出选项，能够适应不同的系统需求。 CY2305SXC-1的详细参数 1. 电源参数 - 工作电压范围: 通常为3.3V ± 10% - 最大功耗: 询问具体应用的功耗一般低于100mA ### 2. 输入输出参数 - 输入时钟频率范围: 支持从1 MHz到50 MHz - 输出时钟频率: 可通过内部分频器实现不同的输出频率选项，最大可达200 MHz - 时钟输出类...

产品型号CY2305SXC-1的Datasheet PDF文件预览

CY2305

CY2309

Low-Cost 3.3V Zero Delay Buffer

CY2309. It accepts one reference input, and drives out five

low-skew clocks. The -1H versions of each device operate at

up to 100-/133-MHz frequencies, and have higher drive than

the -1 devices. All parts have on-chip PLLs which lock to an

input clock on the REF pin. The PLL feedback is on-chip and

is obtained from the CLKOUT pad.

The CY2309 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the “Select Input

Decoding” table on page 2. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the

input clock to be directly applied to the outputs for chip and

system testing purposes.

The CY2305 and CY2309 PLLs enter a power-down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off, resulting

in less than 12.0 µA of current draw for commercial temper-

ature devices and 25.0 µA for industrial temperature parts. The

CY2309 PLL shuts down in one additional case as shown in

the table below.

Multiple CY2305 and CY2309 devices can accept the same

input clock and distribute it. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

Features

• 10-MHz to 100-/133-MHz operating range, compatible

with CPU and PCI bus frequencies

• Zero input-output propagation delay

• 60 ps typical cycle-to-cycle jitter (high drive)

• Multiple low-skew outputs

— 85 ps typical output-to-output skew

— One input drives five outputs (CY2305)

— One input drives nine outputs, grouped as 4 + 4 + 1

(CY2309)

• Compatible with Pentium^-based systems

• Test Mode to bypass phase-locked loop (PLL) (CY2309

only [see “Select Input Decoding” on page 2])

• Available in space-saving 16-pin 150-mil SOIC or

4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil

SOIC package (CY2305)

• 3.3V operation

• Industrial temperature available

The CY2305/CY2309 is available in two/three different config-

urations, as shown in the ordering information (page 10). The

CY2305-1/CY2309-1 is the base part. The CY2305-1H/

CY2309-1H is the high-drive version of the -1, and its rise and

fall times are much faster than the -1s.

Functional Description

The CY2309 is a low-cost 3.3V zero delay buffer designed to

distribute high-speed clocks and is available in a 16-pin SOIC

or TSSOP package. The CY2305 is an 8-pin version of the

Block Diagram

Pin Configuration

SOIC/TSSOP

Top View

CLKOUT

PLL

MUX

REF

CLKA1

CLKOUT

REF

CLKA1

CLKA2

CLKA4

CLKA3

V_DD

CLKA2

V_DD

GND

CLKB1

CLKA3

CLKA4

CLKB4

CLKB3

CLKB2

CLKB1

CLKB2

CLKB3

CLKB4

SOIC

Top View

Select Input

Decoding

CLKOUT

CLK4

REF

CLK2

CLK1

CLK3

GND

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07140 Rev. *G

Revised August 4, 2005

CY2305

CY2309

Pin Description for CY2309

Signal

Description

Input reference frequency, 5V-tolerant input

Buffered clock output, Bank A

3.3V supply

REF^[1]

CLKA1^[2]

CLKA2^[2]

V_DD

GND

Ground

CLKB1^[2]

CLKB2^[2]

S2^[3]

Buffered clock output, Bank B

Select input, bit 2

S1^[3]

Select input, bit 1

CLKB3^[2]

CLKB4^[2]

GND

Buffered clock output, Bank B

Ground

V_DD

3.3V supply

CLKA3^[2]

CLKA4^[2]

Buffered clock output, Bank A

Buffered output, internal feedback on this pin

CLKOUT^[2]

Pin Description for CY2305

Signal

Description

Input reference frequency, 5V-tolerant input

Buffered clock output

Ground

Buffered clock output

3.3V supply

Buffered clock output

Buffered clock output, internal feedback on this pin

REF^[1]

CLK2^[2]

CLK1^[2]

GND

CLK3^[2]

V_DD

CLK4^[2]

CLKOUT^[2]

Select Input Decoding for CY2309

CLOCK A1–A4

Three-state

Driven

CLOCK B1–B4

Three-state

Driven

CLKOUT^[4]

Driven

Output Source

PLL

PLL Shutdown

PLL

Reference

PLL

Driven

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-ups on these inputs.

4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.

Document #: 38-07140 Rev. *G

Page 2 of 14

CY2305

CY2309

REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins

Zero Delay and Skew Control

All outputs should be uniformly loaded to achieve Zero Delay

between the input and output. Since the CLKOUT pin is the

internal feedback to the PLL, its relative loading can adjust the

input-output delay. This is shown in the above graph.

other outputs, for obtaining zero input-output delay. If input to

output delay adjustments are required, use the above graph to

calculate loading differences between the CLKOUT pin and

other outputs.

For applications requiring zero input-output delay, all outputs,

including CLKOUT, must be equally loaded. Even if CLKOUT

is not used, it must have a capacitive load, equal to that on

For zero output-output skew, be sure to load all outputs

equally. For further information refer to the application note

entitled “CY2305 and CY2309 as PCI and SDRAM Buffers.”

Document #: 38-07140 Rev. *G

Page 3 of 14

CY2305

CY2309

Storage Temperature ................................. –65°C to +150°C

Junction Temperature................................................. 150°C

Absolute Maximum Conditions

Supply Voltage to Ground Potential............... –0.5V to +7.0V

DC Input Voltage (Except REF) ............–0.5V to V_DD+ 0.5V

DC Input Voltage REF......................................... –0.5V to 7V

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ...........................> 2,000V

Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices

Parameter

V_DD

Description

Min.

3.0

–

Max.

3.6

Unit

Supply Voltage

T_A

Operating Temperature (Ambient Temperature)

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance

°C

C_L

C_IN

t_PU

–

0.05

Power-up time for all V_DDs to reach minimum specified voltage

(power ramps must be monotonic)

Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices

Parameter

Description

Input LOW Voltage^[5]

Input HIGH Voltage^[5]

Input LOW Current

Input HIGH Current

Output LOW Voltage^[6]

Test Conditions

Min.

–

2.0

–

Max.

0.8

–

50.0

100.0

0.4

Unit

µA

V_IL

V_IH

I_IL

V_IN= 0V

V_IN= V_DD

I_IH

V_OL

I_OL= 8 mA (–1)

–

_{OH =}12 mA (–1H)

V_OH

Output HIGH Voltage^[6]

I_OH= –8 mA (–1)

2.4

–

_OL= –12 mA (–1H)

I_DD(PD mode)

I_DD

Power Down Supply Current REF = 0 MHz

Supply Current Unloaded outputs at 66.67 MHz,

SEL inputs at V_DD

–

12.0

32.0

µA

Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices^[7]

Parameter

Name

Test Conditions

Min.

Typ.

Max.

Unit

Output Frequency

30-pF load

10-pF load

Measured at 1.4V, F_out= 66.67 MHz

Measured between 0.8V and 2.0V

All outputs equally loaded

–

100

MHz

133.33

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

40.0

50.0

–

60.0

2.50

250

t₄

t₅

–

Fall Time^[6]

Output to Output Skew^[6]

t_6A

Delay, REF Rising Edge to Measured at V_DD/2

±350

CLKOUT Rising Edge^[6]

t_6B

t₇

Delay, REF Rising Edge to Measured at V_DD/2. Measured in PLL

–

8.7

CLKOUT Rising Edge^[6]

Bypass Mode, CY2309 device only.

Device to Device Skew^[6]Measured at V_DD/2 on the CLKOUT pins

of devices

700

t_J

t_LOCK

Cycle to Cycle Jitter^[6]

PLL Lock Time^[6]

Measured at 66.67 MHz, loaded outputs

–

200

1.0

Stable power supply, valid clock

presented on REF pin

Notes:

5. REF input has a threshold voltage of V /2.

6. Parameter is guaranteed by design and characterization. Not 100% tested in production.

7. All parameters specified with loaded outputs.

Document #: 38-07140 Rev. *G

Page 4 of 14

CY2305

CY2309

Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices^[7]

Parameter

Name

Description

Min.

Typ.

Max.

Unit

Output Frequency

30-pF load

10-pF load

–

100

MHz

133.33

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

Measured at 1.4V, F_out= 66.67 MHz

Measured at 1.4V, F_out< 50.0 MHz

Measured between 0.8V and 2.0V

All outputs equally loaded

40.0

45.0

–

50.0

–

60.0

55.0

1.50

250

t₄

t₅

Fall Time^[6]

Output to Output Skew^[6]

t_6A

Delay, REF Rising Edge to Measured at V_DD/2

–

±350

CLKOUT Rising Edge^[6]

t_6B

t₇

Delay, REF Rising Edge to Measured at V_DD/2. Measured in PLL

–

8.7

CLKOUT Rising Edge^[6]

Bypass Mode, CY2309 device only.

Device to Device Skew^[6]Measured at V_DD/2 on the CLKOUT pins

of devices

700

t₈

Output Slew Rate^[6]

Measured between 0.8V and 2.0V using

V/ns

Test Circuit #2

t_J

t_LOCK

Cycle to Cycle Jitter^[6]

PLL Lock Time^[6]

Measured at 66.67 MHz, loaded outputs

–

200

1.0

Stable power supply, valid clock

presented on REF pin

Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices

Parameter

Description

Min.

3.0

–40

–

Max.

3.6

Unit

°C

V_DD

T_A

C_L

C_IN

Supply Voltage

Operating Temperature (Ambient Temperature)

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance

Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices

Parameter

Description

Input LOW Voltage^[5]

Input HIGH Voltage^[5]

Input LOW Current

Test Conditions

Min. Max. Unit

V_IL

V_IH

I_IL

–

2.0

–

0.8

–

50.0

µA

V_IN= 0V

I_IH

V_OL

Input HIGH Current

V_IN= V_DD

–

100.0 µA

Output LOW Voltage^[6]

I_OL= 8 mA (–1)

0.4

I_OH=12 mA (–1H)

V_OH

Output HIGH Voltage^[6]

I_OH= –8 mA (–1)

2.4

–

I_OL= –12 mA (–1H)

I_DD(PD mode)

I_DD

Power-down Supply Current

Supply Current

REF = 0 MHz

–

25.0

35.0

µA

Unloaded outputs at 66.67 MHz, SEL inputs at

V_DD

Document #: 38-07140 Rev. *G

Page 5 of 14

CY2305

CY2309

Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices ^[7]

Parameter

Name

Test Conditions

Min.

Typ.

Max.

Unit

Output Frequency

30-pF load

–

100

MHz

10-pF load

133.33

60.0

2.50

250

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

Measured at 1.4V, F_out= 66.67 MHz

Measured between 0.8V and 2.0V

All outputs equally loaded

40.0

50.0

–

t₄

t₅

–

Fall Time^[6]

Output to Output Skew^[6]

t_6A

Delay, REF Rising Edge to Measured at V_DD/2

±350

CLKOUT Rising Edge^[6]

t_6B

Delay, REF Rising Edge to Measured at V_DD/2. Measured in

8.7

CLKOUT Rising Edge^[6]

Device to Device Skew^[6]

Cycle to Cycle Jitter^[6]

PLL Lock Time^[6]

PLL Bypass Mode, CY2309 device

only.

t₇

Measured at V_DD/2 on the CLKOUT

–

700

200

1.0

pins of devices

t_J

Measured at 66.67 MHz, loaded

outputs

t_LOCK

Stable power supply, valid clock

presented on REF pin

Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices^[7]

Parameter

Name

Description

Min.

Typ.

Max.

Unit

t₁

Output Frequency

30-pF load

10-pF load

–

100

MHz

133.33

MHz

Duty Cycle^[6]= t₂÷ t₁

Rise Time^[6]

Measured at 1.4V, F_out= 66.67 MHz

Measured at 1.4V, F_out< 50.0 MHz

Measured between 0.8V and 2.0V

All outputs equally loaded

40.0

45.0

–

50.0

–

60.0

55.0

1.50

250

t₃

t₄

t₅

t_6A

Fall Time^[6]

Output to Output Skew^[6]

Delay, REF Rising Edge to Measured at V_DD/2

–

±350

CLKOUT Rising Edge^[6]

t_6B

Delay, REF Rising Edge to Measured at V_DD/2. Measured in

8.7

CLKOUT Rising Edge^[6]

Device to Device Skew^[6]

Output Slew Rate^[6]

Cycle to Cycle Jitter^[6]

PLL Lock Time^[6]

PLL Bypass Mode, CY2309 device

only.

t₇

Measured at V_DD/2 on the CLKOUT

–

700

–

V/ns

pins of devices

t₈

Measured between 0.8V and 2.0V

using Test Circuit #2

t_J

Measured at 66.67 MHz, loaded

–

200

1.0

outputs

t_LOCK

Stable power supply, valid clock

presented on REF pin

Document #: 38-07140 Rev. *G

Page 6 of 14

CY2305

CY2309

Switching Waveforms

Duty Cycle Timing

1.4V

All Outputs Rise/Fall Time

3.3V

2.0V

0.8V

OUTPUT

0.8V

Output-Output Skew

1.4V

OUTPUT

1.4V

OUTPUT

Input-Output Propagation Delay

_DD/2

INPUT

V_DD/2

OUTPUT

Device-Device Skew

V_DD/2

CLKOUT, Device 1

CLKOUT, Device 2

V_DD/2

t₇

Document #: 38-07140 Rev. *G

Page 7 of 14

CY2305

CY2309

Typical Duty Cycle^[8]and I_DDTrends^[9]for CY2305-1 and CY2309-1

Duty Cycle Vs VDD

(for 30 pF Loads over Frequency - 3.3V, 25C)

Duty Cycle Vs VDD

(for 15 pF Loads over Frequency - 3.3V, 25C)

33 MHz

66 MHz

100 MHz

133 MHz

33 MHz

66 MHz

100 MHz

3.1

3.2

3.3

3.4

3.5

3.6

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

Duty Cycle Vs Frequency

(for 30 pF Loads over Temperature - 3.3V)

Duty Cycle Vs Frequency

(for 15 pF Loads over Temperature - 3.3V)

-40C

25C

70C

85C

25C

70C

85C

100

120

140

100

120

140

Frequency (MHz)

IDD vs Number of Loaded Outputs

(for 30 pF Loads over Frequency - 3.3V, 25C)

IDD vs Number of Loaded Outputs

(for 15 pF Loads over Frequency - 3.3V, 25C)

140

120

100

140

120

100

33 MHz

66 MHz

100 MHz

33 MHz

66 MHz

100 MHz

# of Loaded Outputs

Notes:

8. Duty Cycle is taken from typical chip measured at 1.4V.

9. I data is calculated from I = I

+ nCVf, where I

is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply

CORE

Voltage (V); f = frequency (Hz)).

Document #: 38-07140 Rev. *G

Page 8 of 14

CY2305

CY2309

Typical Duty Cycle^[8]and IDD Trends^[9]for CY2305-1H and CY2309-1H

Duty Cycle Vs VDD

(for 30 pF Loads over Frequency - 3.3V, 25C)

Duty Cycle Vs VDD

(for 15 pF Loads over Frequency - 3.3V, 25C)

33 MHz

66 MHz

100 MHz

133 MHz

33 MHz

66 MHz

100 MHz

3.1

3.2

3.3

3.4

3.5

3.6

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

Duty Cycle Vs Frequency

(for 30 pF Loads over Temperature - 3.3V)

Duty Cycle Vs Frequency

(for 15 pF Loads over Temperature - 3.3V)

-40C

25C

70C

85C

25C

70C

85C

100

120

140

100

120

140

Frequency (MHz)

IDD vs Number of Loaded Outputs

(for 30 pF Loads over Frequency - 3.3V, 25C)

IDD vs Number of Loaded Outputs

(for 15 pF Loads over Frequency - 3.3V, 25C)

160

140

120

100

160

140

120

100

33 MHz

66 MHz

100 MHz

33 MHz

66 MHz

100 MHz

# of Loaded Outputs

Document #: 38-07140 Rev. *G

Page 9 of 14

CY2305

CY2309

Test Circuits

Test Circuit # 2

Test Circuit # 1

1 kΩ

0.1 µ F

CLK out

0.1 µ F

OUTPUTS

GND

OUTPUTS

10 pF

LOAD

GND

For parameter t₈(output slew rate) on -1H devices

Ordering Information

Ordering Code

Package Type

Operating Range

CY2305SC-1

8-pin 150-mil SOIC

Commercial

CY2305SC-1T

CY2305SZC-1

CY2305SZC-1T

CY2305SXC-1

CY2305SXC-1T

CY2305SI-1

8-pin 150-mil SOIC – Tape and Reel

8-pin 150-mil SOIC – (Lead-free)

8-pin 150-mil SOIC – Tape and Reel – (Lead-free)

8-pin 150-mil SOIC – (Lead-free)

8-pin 150-mil SOIC – Tape and Reel – (Lead-free)

8-pin 150-mil SOIC

Commercial

Industrial

CY2305SI-1T

CY2305SZI-1

8-pin 150-mil SOIC – Tape and Reel

8-pin 150-mil SOIC – (Lead-free)

Industrial

CY2305SZI-1T

CY2305SXI-1

8-pin 150-mil SOIC – Tape and Reel – (Lead-free)

8-pin 150-mil SOIC – (Lead-free)

Industrial

CY2305SXI-1T

CY2305SC-1H

CY2305SC-1HT

CY2305SZC-1H

CY2305SZC-1HT

CY2305SXC-1H

CY2305SXC-1HT

CY2305SI-1H

8-pin 150-mil SOIC – Tape and Reel – (Lead-free)

8-pin 150-mil SOIC

8-pin 150-mil SOIC – Tape and Reel

8-pin 150-mil SOIC – (Lead-free)

8-pin 150-mil SOIC – Tape and Reel – (Lead-free)

8-pin 150-mil SOIC – (Lead-free)

8-pin 150-mil SOIC – Tape and Reel – (Lead-free)

8-pin 150-mil SOIC

Industrial

Commercial

Industrial

CY2305SI-1HT

CY2305SZI-1H

CY2305SZI-1HT

CY2305SXI-1H

CY2305SXI-1HT

CY2309SC-1

CY2309SC-1T

CY2309SZC-1

CY2309SZC-1T

CY2309SXC-1

CY2309SXC-1T

8-pin 150-mil SOIC – Tape and Reel

8-pin 150-mil SOIC – (Lead-free)

8-pin 150-mil SOIC – Tape and Reel – (Lead-free)

8-pin 150-mil SOIC – (Lead-free)

8-pin 150-mil SOIC – Tape and Reel – (Lead-free)

16-pin 150-mil SOIC

16-pin 150-mil SOIC – Tape and Reel

16-pin 150-mil SOIC – (Lead-free)

Industrial

Commercial

16-pin 150-mil SOIC – Tape and Reel – (Lead-free)

16-pin 150-mil SOIC – (Lead-free)

16-pin 150-mil SOIC – Tape and Reel – (Lead-free)

Document #: 38-07140 Rev. *G

Page 10 of 14

CY2305

CY2309

Ordering Information (continued)

Ordering Code

Package Type

Operating Range

CY2309SI-1

16-pin 150-mil SOIC

Industrial

CY2309SI-1T

CY2309SZI-1

16-pin 150-mil SOIC – Tape and Reel

16-pin 150-mil SOIC – (Lead-free)

Industrial

CY2309SZI-1T

CY2309SXI-1

16-pin 150-mil SOIC – Tape and Reel – (Lead-free)

16-pin 150-mil SOIC – (Lead-free)

Industrial

CY2309SXI-1T

CY2309SC-1H

CY2309SC-1HT

CY2309SZC-1H

CY2309SZC-1HT

CY2309SXC-1H

CY2309SXC-1HT

CY2309SI-1H

16-pin 150-mil SOIC – Tape and Reel – (Lead-free)

16-pin 150-mil SOIC

16-pin 150-mil SOIC – Tape and Reel

16-pin 150-mil SOIC – (Lead-free)

16-pin 150-mil SOIC – Tape and Reel – (Lead-free)

16-pin 150-mil SOIC – (Lead-free)

16-pin 150-mil SOIC – Tape and Reel – (Lead-free)

16-pin 150-mil SOIC

Industrial

Commercial

Industrial

CY2309SI-1HT

CY2309SZI-1H

CY2309SZI-1HT

CY2309SXI-1H

CY2309SXI-1HT

CY2309ZC-1H

CY2309ZC-1HT

CY2309ZXC-1H

CY2309ZXC-1HT

CY2309ZZC-1H

CY2309ZZC-1HT

CY2309ZI-1H

16-pin 150-mil SOIC – Tape and Reel

16-pin 150-mil SOIC – (Lead-free)

16-pin 150-mil SOIC – Tape and Reel – (Lead-free)

16-pin 150-mil SOIC – (Lead-free)

16-pin 150-mil SOIC – Tape and Reel – (Lead-free)

16-pin 4.4-mm TSSOP

16-pin 4.4-mm TSSOP – Tape and Reel

16-pin 4.4-mm TSSOP – (Lead-free)

16-pin 4.4-mm TSSOP – Tape and Reel – (Lead-free)

16-pin 4.4-mm TSSOP – (Lead-free)

16-pin 4.4-mm TSSOP – Tape and Reel – (Lead-free)

16-pin 4.4-mm TSSOP

Industrial

Commercial

Industrial

CY2309ZI-1HT

CY2309ZXI-1H

CY2309ZXI-1HT

CY2309ZZI-1H

CY2309ZZI-1HT

16-pin 4.4-mm TSSOP – Tape and Reel

16-pin 4.4-mm TSSOP – (Lead-free)

16-pin 4.4-mm TSSOP – Tape and Reel – (Lead-free)

16-pin 4.4-mm TSSOP – (Lead-free)

16-pin 4.4-mm TSSOP – Tape and Reel – (Lead-free)

Industrial

Document #: 38-07140 Rev. *G

Page 11 of 14

CY2305

CY2309

Package Drawing and Dimensions

8 Lead (150 Mil) SOIC - S08

8-lead (150-Mil) SOIC S8

PIN 1 ID

1. DIMENSIONS IN INCHES[MM] MIN.

MAX.

2. PIN 1 ID IS OPTIONAL,

ROUND ON SINGLE LEADFRAME

RECTANGULAR ON MATRIX LEADFRAME

0.150[3.810]

0.157[3.987]

3. REFERENCE JEDEC MS-012

4. PACKAGE WEIGHT 0.07gms

0.230[5.842]

0.244[6.197]

PART #

S08.15 STANDARD PKG.

SZ08.15 LEAD FREE PKG.

0.189[4.800]

0.196[4.978]

0.010[0.254]

0.016[0.406]

X 45°

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.004[0.102]

0°~8°

0.016[0.406]

0.035[0.889]

0.0098[0.249]

51-85066-*C

0.0138[0.350]

0.0192[0.487]

16-Lead (150-Mil) SOIC S16

PIN 1 ID

DIMENSIONS IN INCHES[MM] MIN.

MAX.

REFERENCE JEDEC MS-012

PACKAGE WEIGHT 0.15gms

0.150[3.810]

0.157[3.987]

0.230[5.842]

0.244[6.197]

PART #

S16.15 STANDARD PKG.

SZ16.15 LEAD FREE PKG.

0.010[0.254]

0.016[0.406]

X 45°

0.386[9.804]

0.393[9.982]

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.016[0.406]

0.035[0.889]

0°~8°

0.0138[0.350]

0.0192[0.487]

0.004[0.102]

0.0098[0.249]

51-85068-*B

Document #: 38-07140 Rev. *G

Page 12 of 14

CY2305

CY2309

Package Drawing and Dimensions (continued)

16-lead TSSOP 4.40 MM Body Z16.173

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN.

MAX.

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.05gms

6.25[0.246]

6.50[0.256]

4.30[0.169]

4.50[0.177]

0.65[0.025]

BSC.

0.25[0.010]

BSC

0.19[0.007]

0.30[0.012]

1.10[0.043] MAX.

GAUGE

PLANE

0°-8°

0.076[0.003]

0.50[0.020]

0.70[0.027]

0.05[0.002]

0.15[0.006]

0.85[0.033]

0.95[0.037]

0.09[[0.003]

0.20[0.008]

SEATING

PLANE

4.90[0.193]

5.10[0.200]

51-85091-*A

Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the

trademarks of their respective holders.

Document #: 38-07140 Rev. *G

Page 13 of 14

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY2305

CY2309

Document History Page

Document Title: CY2305/CY2309 Low-Cost 3.3V Zero Delay Buffer

Document Number: 38-07140

Orig. of

REV.

ECN NO. Issue Date Change

Description of Change

Change from Spec number: 38-00530 to 38-07140

110249

10/19/01

SZV

111117

03/01/02

CKN

Added t6B row to the Switching Characteristics Table; also added the letter

“A” to the t6A row

Corrected the table title from CY2305SC-IH and CY2309SC-IH to

CY2305SI-IH and CY2309SI-IH

117625

10/21/02

HWT

Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the

ordering information table.

Added the Tape and Reel option to all the existing packages:

CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT,

CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT,

CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT

121828

131503

214083

12/14/02

12/12/03

See ECN

RBI

RGL

Power-up requirements added to Operating Conditions information

Added Lead-free for all the devices in the ordering information table

Added a Lead-free with the new coding for all SOIC devices in the ordering

information table

291099

390582

See ECN

RGL

Added TSSOP Lead-free devices

Added typical values for jitter

Document #: 38-07140 Rev. *G

Page 14 of 14

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CY2305SXC-1产品参数

型号:	CY2305SXC-1
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	CYPRESS SEMICONDUCTOR CORP
零件包装代码：	SOIC
包装说明：	SOIC-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.31.00.01
Factory Lead Time：	1 week
风险等级：	1.55
Is Samacsys：	N
系列：	2305
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.889 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.008 A
湿度敏感等级：	3
功能数量：	1
反相输出次数：
端子数量：	8
实输出次数：	8
最高工作温度：	70 °C
最低工作温度：
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	3.3 V
传播延迟（tpd）：	8.7 ns
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.25 ns
座面最大高度：	1.727 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3.8985 mm
最小 fmax：	133.33 MHz
Base Number Matches：	1

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