CY2308SC-4原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号CY2308SC-4的概述

芯片CY2308SC-4的概述 CY2308SC-4是一款由Cypress Semiconductor Corporation研发的时钟发生器和时钟分配器芯片。这款芯片广泛应用于高性能的数字信号处理（DSP）、计算机系统和通信设备等场景。其功能主要是产生和分配多路的时钟信号，确保系统各个部分能够保持同步，进而提高整体的工作性能和稳定性。 CY2308SC-4采用了先进的CMOS工艺，具备高性能、低功耗的特点。其工作频率范围较宽，能够满足不同应用场景对时钟信号的需求。此外，芯片内置多种选项，以提供灵活的时钟输出配置，令人能够根据具体的系统需求进行调整。芯片CY2308SC-4的详细参数 CY2308SC-4的主要技术参数如下： - 工作电压范围：3.0V到3.6V - 工作温度范围：-40°C 到 +85°C - 输出频率范围：16MHz 到 100MHz - 输入频率：可支持23MH...

产品型号CY2308SC-4的Datasheet PDF文件预览

1CY2308

CY2308

3.3V Zero Delay Buffer

The CY2308 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the table “Select

Input Decoding.” If all output clocks are not required, Bank B

can be three-stated. The select inputs also allow the input

clock to be directly applied to the output for chip and system

testing purposes.

Features

• Zero input-output propagation delay, adjustable by

capacitive load on FBK input

• Multiple configurations, see “Available CY2308

Configurations” table

• Multiple low-skew outputs

— Output-output skew less than 200 ps

— Device-device skew less than 700 ps

The CY2308 PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

50 µA of current draw. The PLL shuts down in two additional

cases as shown in the “Select Input Decoding” table.

Multiple CY2308 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

The CY2308 is available in five different configurations, as

shown in the “Available CY2308 Configurations” table on page

2. The CY2308–1 is the base part, where the output

frequencies equal the reference if there is no counter in the

feedback path. The CY2308–1H is the high-drive version of

the –1, and rise and fall times on this device are much faster.

— Two banks of four outputs, three-stateable by two

select inputs

• 10-MHz to 133-MHz operating range

• Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4, –5H)

• Space-saving 16-pin 150-mil SOIC package or 16-pin

TSSOP

• 3.3V operation

• Industrial Temperature available

The CY2308–2 allows the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depends on which output drives the

feedback pin. The CY2308–3 allows the user to obtain 4X and

2X frequencies on the outputs.

The CY2308–4 enables the user to obtain 2X clocks on all

outputs. Thus, the part is extremely versatile, and can be used

in a variety of applications.

Functional Description

The CY2308 is a 3.3V Zero Delay Buffer designed to distribute

high-speed clocks in PC, workstation, datacom, telecom, and

other high-performance applications.

The part has an on-chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback is required to be

driven into the FBK pin, and can be obtained from one of the

outputs. The input-to-output skew is guaranteed to be less

than 350 ps, and output-to-output skew is guaranteed to be

less than 200 ps.

The CY2308–5H is a high-drive version with REF/2 on both

banks.

Pin Configuration

Block Diagram

FBK

PLL

SOIC

REF

MUX

Top View

CLKA1

CLKA2

CLKA3

CLKA4

REF

CLKA1

FBK

Extra Divider (–3, –4)

Extra Divider (–5H)

CLKA4

CLKA3

V_DD

CLKA2

V_DD

GND

CLKB1

Select Input

CLKB4

CLKB3

Decoding

CLKB2

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (–2, –3)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07146 Rev. *C

Revised June 16, 2004

CY2308

Pin Description

Signal

Description

Input reference frequency, 5V tolerant input

Clock output, Bank A

3.3V supply

REF^[1]

CLKA1^[2]

CLKA2^[2]

V_DD

GND

Ground

CLKB1^[2]

CLKB2^[2]

S2^[3]

Clock output, Bank B

Select input, bit 2

Select input, bit 1

Clock output, Bank B

Ground

S1^[3]

CLKB3^[2]

CLKB4^[2]

GND

V_DD

3.3V supply

CLKA3^[2]

CLKA4^[2]

FBK

Clock output, Bank A

PLL feedback input

Select Input Decoding

CLOCK A1–A4

CLOCK B1–B4

Three-State

Driven^[4]

Output Source

PLL

PLL Shutdown

Three-State

Driven

Driven^[4]

Driven

PLL

Reference

PLL

Driven

Available CY2308 Configurations

Device

CY2308–1

Feedback From

Bank A or Bank B

Bank A

Bank B

Bank A

Bank B

Bank A or Bank B

Bank A Frequency

Reference

2 X Reference

4 X Reference

2 X Reference

Reference /2

Bank B Frequency

Reference

Reference/2

Reference

Reference or Reference^[5]

2 X Reference

CY2308–1H

CY2308–2

CY2308–3

CY2308–4

CY2308–5H

2 X Reference

Reference /2

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-ups on these inputs.

4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0.

5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.

Document #: 38-07146 Rev. *C

Page 2 of 14

CY2308

Zero Delay and Skew Control

REF. Input to CLKA/CLKB Delay v/s Difference in Loading between FBK pin and CLKA/CLKB Pins

To close the feedback loop of the CY2308, the FBK pin can be

Maximum Ratings

driven from any of the eight available output pins. The output

driving the FBK pin will be driving a total load of 7 pF plus any

additional load that it drives. The relative loading of this output

(with respect to the remaining outputs) can adjust the input-

output delay. This is shown in the graph above.

For applications requiring zero input-output delay, all outputs

including the one providing feedback should be equally

loaded. If input-output delay adjustments are required, use the

above graph to calculate loading differences between the

feedback output and remaining outputs.

Supply Voltage to Ground Potential ...............–0.5V to +7.0V

DC Input Voltage (Except Ref) .............. –0.5V to V_DD+ 0.5V

DC Input Voltage REF........................................... –0.5 to 7V

Storage Temperature.................................. –65°C to +150°C

Junction Temperature...................................................150°C

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ............................. >2000V

For zero output-output skew, be sure to load outputs equally.

For further information on using CY2308, refer to the appli-

cation note “CY2308: Zero Delay Buffer.”

Operating Conditions for CY2308SC-XX Commercial Temperature Devices

Parameter

V_DD

Description

Min.

3.0

Max.

3.6

Unit

Supply Voltage

T_A

C_L

Operating Temperature (Ambient Temperature)

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance^[6]

°C

C_IN

t_PU

Power-up time for all V_DDs to reach minimum specified voltage

(power ramps must be monotonic)

0.05

Note:

6. Applies to both Ref Clock and FBK.

Document #: 38-07146 Rev. *C

Page 3 of 14

CY2308

Electrical Characteristics for CY2308SC-XX Commercial Temperature Devices

Parameter

V_IL

V_IH

I_IL

I_IH

V_OL

Description

Input LOW Voltage

Input HIGH Voltage

Input LOW Current

Input HIGH Current

Output LOW Voltage^[7]

Test Conditions

Min.

Max.

0.8

Unit

µA

2.0

V_IN= 0V

V_IN= V_DD

I_OL= 8 mA (–1, –2, –3, –4)

50.0

100.0

0.4

_OL= 12 mA (–1H, –5H)

V_OH

Output HIGH Voltage^[7]

I_OH= –8 mA (–1, –2, –3, –4)

2.4

I_OH= –12 mA (–1H, –5H)

_DD(PD mode)

Power Down Supply Current REF = 0 MHz

12.0

45.0

µA

I_DD

Supply Current

Unloaded outputs, 100-MHz REF,

Select inputs at V_DDor GND

70.0

(–1H,–5H)

Unloaded outputs, 66-MHz REF

(–1, –2, –3, –4)

32.0

Unloaded outputs, 33-MHz REF

18.0

(–1, –2, –3, –4)

Note:

7. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Document #: 38-07146 Rev. *C

Page 4 of 14

CY2308

Switching Characteristics for CY2308SC-XX Commercial Temperature Devices ^[8]

Parameter

t₁

Name

Test Conditions

30-pF load, All devices

Min.

40.0

Typ.

Max.

Unit

MHz

Output Frequency

Duty Cycle^[7]= t₂÷ t₁

100

133.3

60.0

20-pF load, –1H, –5H devices^[9]

15-pF load, –1, –2, –3, –4 devices

Measured at 1.4V, F_OUT= 66.66 MHz

50.0

(–1, –2, –3, –4, –1H, –5H) 30-pF load

Duty Cycle^[7]= t₂÷ t₁

Measured at 1.4V, F_OUT<50.0 MHz

45.0

55.0

2.20

1.50

2.20

1.50

1.25

200

(–1, –2, –3, –4, –1H, –5H) 15-pF load

t₃

t₄

t₅

Rise Time^[7]

Measured between 0.8V and 2.0V,

(–1, –2, –3, –4)

30-pF load

Rise Time^[7]

Measured between 0.8V and 2.0V,

(–1, –2, –3, –4)

15-pF load

Rise Time^[7]

(–1H, –5H)

Measured between 0.8V and 2.0V,

30-pF load

Fall Time^[7]

Measured between 0.8V and 2.0V,

(–1, –2, –3, –4)

30-pF load

Fall Time^[7]

Measured between 0.8V and 2.0V,

15-pF load

(–1, –2, –3, –4)

Fall Time^[7]

Measured between 0.8V and 2.0V,

(–1H, –5H)

30-pF load

Output to Output Skew on All outputs equally loaded

same Bank

(–1, –2, –3, –4)^[7]

Output to Output Skew

All outputs equally loaded

200

400

±250

700

(–1H, –5H)

Output Bank A to Output

Bank B Skew (–1, –4, –5H)

Output Bank A to Output

Bank B Skew (–2, –3)

t₆

t₇

t₈

t_J

Delay, REF Rising Edge to Measured at V_DD/2

FBK Rising Edge^[7]

Device to Device Skew^[7]Measured at V_DD/2 on the FBK pins of

devices

Output Slew Rate^[7]

Measured between 0.8V and 2.0V on –1H,

V/ns

–5H device using Test Circuit #2

Cycle to Cycle Jitter^[7]

(–1, –1H, –4, –5H)

Measured at 66.67 MHz, loaded outputs,

15-pF load

200

100

400

1.0

Measured at 66.67 MHz, loaded outputs,

30-pF load

Measured at 133.3 MHz, loaded outputs,

15-pF load

t_J

Cycle to Cycle Jitter^[7]

(–2, –3)

Measured at 66.67 MHz, loaded outputs

30-pF load

Measured at 66.67 MHz, loaded outputs

15-pF load

t_LOCK

PLL Lock Time^[7]

Stable power supply, valid clocks presented

on REF and FBK pins

Notes:

8. All parameters are specified with loaded outputs.

9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz.

Document #: 38-07146 Rev. *C

Page 5 of 14

CY2308

Operating Conditions for CY2308SI-XX Industrial Temperature Devices

Parameter

V_DD

Description

Min.

3.0

Max.

3.6

Unit

Supply Voltage

T_A

C_L

Operating Temperature (Ambient Temperature)

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance^[6]

–40

°C

C_IN

t_PU

Power-up time for all V_DDs to reach minimum specified voltage

0.05

(power ramps must be monotonic)

Electrical Characteristics for CY2308SI-XX Industrial Temperature Devices

Parameter

Description

Input LOW Voltage

Input HIGH Voltage

Input LOW Current

Input HIGH Current

Output LOW Voltage^[7]

Test Conditions

Min.

Max.

0.8

Unit

µA

V_IL

V_IH

I_IL

I_IH

V_OL

2.0

V_IN= 0V

V_IN= V_DD

50.0

100.0

0.4

I_OL= 8 mA (–1, –2, –3, –4)

I_OL= 12 mA (–1H, –5H)

V_OH

Output HIGH Voltage^[7]

I_OH= –8 mA (–1, –2, –3, –4)

I_OH= –12 mA (–1H, –5H)

2.4

_DD(PD mode)

Power Down Supply Current REF = 0 MHz

25.0

45.0

70(–1H,–5H)

35.0

µA

I_DD

Supply Current

Unloaded outputs, 100 MHz,

Select inputs at V_DDor GND

Unloaded outputs, 66-MHz REF

(–1, –2, –3, –4)

Unloaded outputs, 66-MHz REF

20.0

(–1, –2, –3, –4)

Document #: 38-07146 Rev. *C

Page 6 of 14

CY2308

Switching Characteristics for CY2308SI-XX Industrial Temperature Devices ^[8]

Parameter

t₁

Name

Output Frequency

Test Conditions

Min.

40.0

Typ.

Max.

Unit

MHz

30-pF load, All devices

100

133.3

60.0

20-pF load, –1H, –5H devices^[9]

15-pF load, –1, –2, –3, –4 devices

Duty Cycle^[7]= t₂÷ t₁

Measured at 1.4V, F_OUT= 66.66 MHz

50.0

(–1, –2, –3, –4, –1H, –5H)

30-pF load

Duty Cycle^[7]= t₂÷ t₁

Measured at 1.4V, F_OUT<50.0 MHz

15-pF load

45.0

55.0

2.50

1.50

2.50

1.50

1.25

200

V/ns

(–1, –2, –3, –4, –1H, –5H)

t₃

t₄

t₅

Rise Time^[7]

Measured between 0.8V and 2.0V,

(–1, –2, –3, –4)

30-pF load

Rise Time^[7]

Measured between 0.8V and 2.0V,

15-pF load

(–1, –2, –3, –4)

Rise Time^[7]

(–1H, –5H)

Measured between 0.8V and 2.0V,

30-pF load

Fall Time^[7]

Measured between 0.8V and 2.0V,

30-pF load

(–1, –2, –3, –4)

Fall Time^[7]

Measured between 0.8V and 2.0V,

(–1, –2, –3, –4)

15-pF load

Fall Time^[7]

Measured between 0.8V and 2.0V,

30-pF load

(–1H, –5H)

Output to Output Skew on

All outputs equally loaded

Measured at V_DD/2

same Bank (–1, –2, –3, –4)^[7]

Output to Output Skew

200

(–1H, –5H)

Output Bank A to Output

200

Bank B Skew (–1, –4, –5H)

Output Bank A to Output

400

Bank B Skew (–2, –3)

t₆

t₇

t₈

t_J

Delay, REF Rising Edge to

FBK Rising Edge^[7]

Device to Device Skew^[7]

±250

700

Measured at V_DD/2 on the FBK pins of

devices

Output Slew Rate^[7]

Measured between 0.8V and 2.0V on –1H,

–5H device using Test Circuit # 2

Cycle to Cycle Jitter^[7]

(–1, –1H, –4, –5H)

Measured at 66.67 MHz, loaded outputs,

15-pF load

200

100

400

1.0

Measured at 66.67 MHz, loaded outputs,

30-pF load

Measured at 133.3 MHz, loaded outputs,

15 pF load

t_J

Cycle to Cycle Jitter^[7]

(–2, –3)

Measured at 66.67 MHz, loaded outputs

30-pF load

Measured at 66.67 MHz, loaded outputs

15-pF load

Stable power supply, valid clocks

presented on REF and FBK pins

t_LOCK

PLL Lock Time^[7]

Document #: 38-07146 Rev. *C

Page 7 of 14

CY2308

Switching Waveforms

Duty Cycle Timing

1.4V

All Outputs Rise/Fall Time

3.3V

2.0V

0.8V

OUTPUT

0.8V

Output-Output Skew

1.4V

OUTPUT

1.4V

OUTPUT

Input-Output Propagation Delay

_DD/2

INPUT

FBK

V_DD/2

t₆

Device-Device Skew

V_DD/2

FBK, Device 1

FBK, Device 2

_DD/2

t₇

Document #: 38-07146 Rev. *C

Page 8 of 14

CY2308

Typical Duty Cycle^[10]and I_DDTrends^[11]for CY2308–1,2,3,4

Duty Cycle Vs VDD

(for 30 pF Loads over Frequency - 3.3V, 25C)

Duty Cycle Vs VDD

(for 15 pF Loads over Frequency - 3.3V, 25C)

33 MHz

66 MHz

100 MHz

133 MHz

33 MHz

66 MHz

100 MHz

3.1

3.2

3.3

3.4

3.5

3.6

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

DutyCycle Vs Frequency

(for 30 pF Loads over Temperature - 3.3V)

Duty Cycle Vs Frequency

(for 15 pF Loads over Temperature - 3.3V)

-40C

25C

70C

85C

25C

70C

85C

100

120

140

100

120

140

Frequency (MHz)

IDD vs Number of Loaded Outputs

(for 30 pF Loads over Frequency - 3.3V, 25C)

IDD vs Number of Loaded Outputs

(for 15 pF Loads over Frequency - 3.3V, 25C)

140

120

100

140

120

100

33 M Hz

66 M Hz

33 M Hz

66 M Hz

1 00 M Hz

of Loaded Out put s

of Loaded Outputs

Notes:

10. Duty Cycle is taken from typical chip measured at 1.4V.

11. I data is calculated from I = I

+ nCVf, where I

is the unloaded current.

CORE

(n = # of outputs; C = Capacitance load per output (F); V = Voltage Supply (V); f = frequency (Hz))

Document #: 38-07146 Rev. *C

Page 9 of 14

CY2308

Typical Duty Cycle^[10]and I_DDTrends^[11]for CY2308–1H, 5H

Duty Cycle Vs VDD

(for 30 pF Loads over Frequency - 3.3V, 25C)

Duty Cycle Vs VDD

(for 15 pF Loads over Frequency - 3.3V, 25C)

33 MHz

66 MHz

100 MHz

133 MHz

33 MHz

66 MHz

100 MHz

3.1

3.2

3.3

3.4

3.5

3.6

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

DutyCycle Vs Frequency

Duty Cycle Vs VDD

(for 15 pF Loads over Temperature - 3.3V)

(for 15 pF Loads over Frequency - 3.3V, 25C)

DutyCycle Vs Frequency

(for 30 pF Loads over Temperature - 3.3V)

6600

-40C

33 MHz

66 MHz

25C

70C

85C

100 MHz

70C

133 MHz

85C

3.2

3.3

100

3.4

120

3.5

140

3.6

100

120

140

3.1

Frequency (MHz)

VDD (V)

Frequency (MHz)

IDD vs Number of Loaded Outputs

(for 15 pF Loads over Frequency - 3.3V, 25C)

IDD vs Number of Loaded Outputs

(for 30 pF Loads over Frequency - 3.3V, 25C)

140

120

100

140

120

100

33MHz

66MHz

100MHz

33MHz

66MHz

100MHz

of Loaded Out put s

Document #: 38-07146 Rev. *C

Page 10 of 14

CY2308

Test Circuits

Test Circuit # 2

Test Circuit # 1

V_DD

1 KΩ

CLK

out

0.1 µF

CLK _OUT

C_LOAD

0.1 µF

OUTPUTS

10 pF

V_DD

GND

Test Circuit for all parameters except t₈

Test Circuit for t₈, Output slew rate on –1H, –5 device

Document #: 38-07146 Rev. *C

Page 11 of 14

CY2308

Ordering Information

Ordering Code

CY2308SC–1

CY2308SI–1

CY2308SC–1H

CY2308SI–1H

CY2308ZC–1H

CY2308ZI–1H

CY2308SC–2

CY2308SI–2

CY2308SC–3

CY2308SI–3

CY2308SC–4

CY2308SI–4

CY2308SC–5H

CY2308SI–5H

CY2308ZC–5H

CY2308ZI–5H

Lead Free

Package Name

S16

Package Type

16-pin 150-mil SOIC

Operating Range

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

S16

Z16

S16

Z16

16-pin 150-mil SOIC

16-pin 150-mil TSSOP

16-pin 150-mil SOIC

16-pin 150-mil TSSOP

Commercial

Industrial

CY2308SXC–1

CY2308SXI–1

CY2308SXC–1H

CY2308SXI–1H

CY2308ZXC–1H

CY2308ZXI–1H

CY2308SXC–2

CY2308SXI–2

CY2308SXC–3

CY2308SXI–3

CY2308SXC–4

CY2308SXI–4

CY2308SXC–5H

CY2308SXI–5H

CY2308ZXC–5H

CY2308ZXI–5H

S16

Z16

S16

Z16

16-pin 150-mil SOIC

16-pin 150-mil TSSOP

16-pin 150-mil SOIC

16-pin 150-mil TSSOP

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Document #: 38-07146 Rev. *C

Page 12 of 14

CY2308

Package Drawings and Dimensions

16-Lead (150-Mil) SOIC S16.15

16 Lead (150 Mil) SOIC

PIN 1 ID

DIMENSIONS IN INCHES[MM] MIN.

MAX.

REFERENCE JEDEC MS-012

PACKAGE WEIGHT 0.15gms

0.150[3.810]

0.157[3.987]

0.230[5.842]

0.244[6.197]

PART #

S16.15 STANDARD PKG.

SZ16.15 LEAD FREE PKG.

0.010[0.254]

0.016[0.406]

X 45°

0.386[9.804]

0.393[9.982]

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.016[0.406]

0.035[0.889]

0°~8°

0.0138[0.350]

0.0192[0.487]

0.004[0.102]

0.0098[0.249]

51-85068-*B

16-lead TSSOP 4.40 MM Body Z16.173

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN.

MAX.

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.05 gms

6.25[0.246]

6.50[0.256]

4.30[0.169]

4.50[0.177]

PART #

Z16.173 STANDARD PKG.

ZZ16.173 LEAD FREE PKG.

0.65[0.025]

BSC.

0.25[0.010]

BSC

0.19[0.007]

0.30[0.012]

1.10[0.043] MAX.

GAUGE

PLANE

0°-8°

0.076[0.003]

0.50[0.020]

0.70[0.027]

0.05[0.002]

0.15[0.006]

0.85[0.033]

0.95[0.037]

0.09[[0.003]

0.20[0.008]

SEATING

PLANE

4.90[0.193]

5.10[0.200]

51-85091-*A

All product and company names mentioned in this document may be the trademarks of their respective holders

Document #: 38-07146 Rev. *C

Page 13 of 14

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY2308

.Document History Page

Document Title: CY2308 3.3V Zero Delay Buffer

Document Number: 38-07146

Issue

Orig. of

REV.

ECN NO.

110255

118722

121832

235854

Date

Change

Description of Change

Change from Spec number: 38-00528 to 38-07146

Added Note 1 in page 2.

Power up requirements added to Operating Conditions Information

Added Lead Free Devices

12/17/01

10/31/02

12/14/02

See ECN

SZV

RGL

RBI

RGL

Document #: 38-07146 Rev. *C

Page 14 of 14

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CY2308SC-4产品参数

型号:	CY2308SC-4
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	CYPRESS SEMICONDUCTOR CORP
零件包装代码：	SOIC
包装说明：	0.150 INCH, MS-012, SOIC-16
针数：	16
Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	5.01
Is Samacsys：	N
系列：	2308
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0
长度：	9.893 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	3
功能数量：	1
反相输出次数：
端子数量：	16
实输出次数：	8
最高工作温度：	70 °C
最低工作温度：
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240
电源：	3.3 V
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.2 ns
座面最大高度：	1.727 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3.8985 mm
最小 fmax：	133.3 MHz
Base Number Matches：	1

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