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产品型号CY2309ZC-1H的概述

CY2309ZC-1H 芯片概述 CY2309ZC-1H是一款由Cypress Semiconductor(现为Infineon Technologies的一部分)设计和制造的时钟生成器和分频器。该芯片具备高性能和灵活性,广泛应用于各种电子产品中,例如计算机、通信设备、数字信号处理器和所有需要精确时钟信号的设备中。CY2309ZC-1H适用于需要多个时钟输出的系统,能够生成低抖动和高稳定性的时钟信号,提升系统的整体性能和可靠性。 CY2309ZC-1H 详细参数 CY2309ZC-1H的设计旨在满足现代电子设备对时钟信号稳定性和精度的要求。其主要特点和参数如下: - 频率范围: 输入时钟频率范围为8 MHz到100 MHz,输出频率可通过分频器设置,输出多个时钟。 - 输出数量: 该芯片提供多达9个低抖动的时钟输出。 - 供电电压: 该芯片支持1.8V、2.5V 和 3.3V的供电电压...

产品型号CY2309ZC-1H的Datasheet PDF文件预览

CY2305  
CY2309  
Low-cost 3.3V Zero Delay Buffer  
up to 100-/133-MHz frequencies, and have higher drive than  
the -1 devices. All parts have on-chip PLLs which lock to an  
input clock on the REF pin. The PLL feedback is on-chip and  
is obtained from the CLKOUT pad.  
Features  
• 10-MHz to 100-/133-MHz operating range, compatible  
with CPU and PCI bus frequencies  
• Zero input-output propagation delay  
• Multiple low-skew outputs  
The CY2309 has two banks of four outputs each, which can  
be controlled by the Select inputs as shown in the Select Input  
Decodingtable on page 2. If all output clocks are not required,  
BankB can be three-stated. The select inputs also allow the  
input clock to be directly applied to the outputs for chip and  
system testing purposes.  
— Output-output skew less than 250 ps  
— Device-device skew less than 700 ps  
— One input drives five outputs (CY2305)  
The CY2305 and CY2309 PLLs enter a power-down mode  
when there are no rising edges on the REF input. In this state,  
the outputs are three-stated and the PLL is turned off, resulting  
in less than 12.0 µA of current draw for commercial temper-  
ature devices and 25.0 µA for industrial temperature parts. The  
CY2309 PLL shuts down in one additional case as shown in  
the table below.  
— One input drives nine outputs, grouped as 4 + 4 + 1  
(CY2309)  
• Less than 200 ps cycle-cycle jitter, compatible with  
Pentium -based systems  
• Test Mode to bypass phase-locked loop (PLL) (CY2309  
only [see “Select Input Decoding” on page 2])  
Multiple CY2305 and CY2309 devices can accept the same  
input clock and distribute it. In this case, the skew between the  
outputs of two devices is guaranteed to be less than 700 ps.  
• Available in space-saving 16-pin 150-mil SOIC or  
4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil  
SOIC package (CY2305)  
All outputs have less than 200 ps of cycle-cycle jitter. The input  
to output propagation delay on both devices is guaranteed to  
be less than 350 ps, and the output to output skew is  
guaranteed to be less than 250 ps.  
• 3.3V operation  
• Industrial temperature available  
Functional Description  
The CY2305/CY2309 is available in two/three different config-  
urations, as shown in the ordering information (page 10). The  
CY2305-1/CY2309-1 is the base part. The CY2305-1H/  
CY2309-1H is the high-drive version of the -1, and its rise and  
fall times are much faster than the -1s.  
The CY2309 is a low-cost 3.3V zero delay buffer designed to  
distribute high-speed clocks and is available in a 16-pin SOIC  
or TSSOP package. The CY2305 is an 8-pin version of the  
CY2309. It accepts one reference input, and drives out five  
low-skew clocks. The -1H versions of each device operate at  
Block Diagram  
Pin Configuration  
SOIC/TSSOP  
Top View  
CLKOUT  
PLL  
MUX  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
REF  
CLKOUT  
REF  
CLKA1  
CLKA2  
CLKA1  
CLKA4  
CLKA3  
CLKA2  
V
V
DD  
DD  
GND  
GND  
CLKA3  
CLKA4  
CLKB4  
CLKB3  
S1  
CLKB1  
CLKB2  
S2  
2309-2  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
S2  
SOIC  
Top View  
Select Input  
Decoding  
1
8
CLKOUT  
CLK4  
V
DD  
REF  
CLK2  
CLK1  
GND  
S1  
2
3
4
7
6
2309-3  
2309-1  
5
CLK3  
Cypress Semiconductor Corporation  
Document #: 38-07140 Rev. *C  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised December 14, 2002  
CY2305  
CY2309  
Pin Description for CY2309  
Pin  
1
Signal  
Description  
Input reference frequency, 5V-tolerant input  
REF[1]  
2
CLKA1[2]  
CLKA2[2]  
VDD  
Buffered clock output, Bank A  
Buffered clock output, Bank A  
3.3V supply  
3
4
5
GND  
Ground  
6
CLKB1[2]  
CLKB2[2]  
S2[3]  
Buffered clock output, Bank B  
Buffered clock output, Bank B  
Select input, bit 2  
7
8
9
S1[3]  
Select input, bit 1  
10  
11  
12  
13  
14  
15  
16  
CLKB3[2]  
CLKB4[2]  
GND  
Buffered clock output, Bank B  
Buffered clock output, Bank B  
Ground  
VDD  
CLKA3[2]  
CLKA4[2]  
CLKOUT[2]  
3.3V supply  
Buffered clock output, Bank A  
Buffered clock output, Bank A  
Buffered output, internal feedback on this pin  
Pin Description for CY2305  
Pin  
1
Signal  
Description  
Input reference frequency, 5V-tolerant input  
Buffered clock output  
REF[1]  
CLK2[2]  
CLK1[2]  
GND  
2
3
Buffered clock output  
4
Ground  
5
CLK3[2]  
Buffered clock output  
6
VDD  
3.3V supply  
7
CLK4[2]  
Buffered clock output  
8
CLKOUT[2]  
Buffered clock output, internal feedback on this pin  
Select Input Decoding for CY2309  
S2  
0
S1  
0
CLOCK A1A4  
Three-state  
Driven  
CLOCK B1B4  
Three-state  
Three-state  
Driven  
CLKOUT[4]  
Driven  
Output Source  
PLL  
PLL Shutdown  
N
N
Y
N
0
1
Driven  
PLL  
1
0
Driven  
Driven  
Reference  
PLL  
1
1
Driven  
Driven  
Driven  
Notes:  
1. Weak pull-down.  
2. Weak pull-down on all outputs.  
3. Weak pull-ups on these inputs.  
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.  
Document #: 38-07140 Rev. *C  
Page 2 of 13  
CY2305  
CY2309  
REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins  
Zero Delay and Skew Control  
All outputs should be uniformly loaded to achieve Zero Delay  
between the input and output. Since the CLKOUT pin is the  
internal feedback to the PLL, its relative loading can adjust the  
input-output delay. This is shown in the above graph.  
other outputs, for obtaining zero input-output delay. If input to  
output delay adjustments are required, use the above graph to  
calculate loading differences between the CLKOUT pin and  
other outputs.  
For applications requiring zero input-output delay, all outputs,  
including CLKOUT, must be equally loaded. Even if CLKOUT  
is not used, it must have a capacitive load, equal to that on  
For zero output-output skew, be sure to load all outputs  
equally. For further information refer to the application note  
entitled CY2305 and CY2309 as PCI and SDRAM Buffers.”  
Document #: 38-07140 Rev. *C  
Page 3 of 13  
CY2305  
CY2309  
Maximum Ratings  
Supply Voltage to Ground Potential............... 0.5V to +7.0V  
DC Input Voltage (Except REF) ............0.5V to VDD + 0.5V  
DC Input Voltage REF......................................... 0.5V to 7V  
Storage Temperature .................................65°C to +150°C  
Junction Temperature................................................. 150°C  
Static Discharge Voltage  
(per MIL-STD-883, Method 3015) ...........................> 2,000V  
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices  
Parameter  
Description  
Min.  
3.0  
0
Max.  
3.6  
70  
Unit  
VDD  
Supply Voltage  
V
TA  
Operating Temperature (Ambient Temperature)  
Load Capacitance, below 100 MHz  
Load Capacitance, from 100 MHz to 133 MHz  
Input Capacitance  
°C  
pF  
pF  
pF  
CL  
CL  
CIN  
30  
10  
7
Power-up time for all VDD's to reach minimum specified voltage  
(power ramps must be monotonic)  
tPU  
0.05  
50  
ms  
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices  
Parameter  
Description  
Input LOW Voltage[5]  
Input HIGH Voltage[5]  
Input LOW Current  
Input HIGH Current  
Output LOW Voltage[6]  
Test Conditions  
Min.  
Max.  
Unit  
VIL  
VIH  
IIL  
0.8  
V
2.0  
V
VIN = 0V  
50.0  
100.0  
0.4  
µA  
µA  
V
IIH  
VIN = VDD  
VOL  
IOL = 8 mA (1)  
I
OH = 12 mA (1H)  
IOH = 8 mA (1)  
OL = 12 mA (1H)  
Power Down Supply Current REF = 0 MHz  
Supply Current Unloaded outputs at 66.67 MHz,  
SEL inputs at VDD  
VOH  
Output HIGH Voltage[6]  
2.4  
V
I
IDD (PD mode)  
IDD  
12.0  
32.0  
µA  
mA  
Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices[7]  
Parameter  
Name  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
t1  
Output Frequency  
30-pF load  
10-pF load  
10  
10  
100  
133.33  
MHz  
MHz  
Duty Cycle[6] = t2 ÷ t1  
Rise Time[6]  
Fall Time[6]  
Measured at 1.4V, Fout = 66.67 MHz  
Measured between 0.8V and 2.0V  
Measured between 0.8V and 2.0V  
All outputs equally loaded  
40.0  
50.0  
60.0  
2.50  
2.50  
250  
%
ns  
ns  
ps  
ps  
t3  
t4  
t5  
Output to Output Skew[6]  
t6A  
Delay, REF Rising Edge to Measured at VDD/2  
CLKOUT Rising Edge[6]  
0
5
0
±350  
t6B  
t7  
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL  
1
8.7  
ns  
ps  
CLKOUT Rising Edge[6]  
Bypass Mode, CY2309 device only.  
Device to Device Skew[6] Measuredat VDD/2ontheCLKOUT pins  
of devices  
700  
tJ  
Cycle to Cycle Jitter[6]  
PLL Lock Time[6]  
Measured at 66.67 MHz, loaded outputs  
200  
1.0  
ps  
tLOCK  
Stable power supply, valid clock  
presented on REF pin  
ms  
Notes:  
5. REF input has a threshold voltage of VDD/2.  
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
7. All parameters specified with loaded outputs.  
Document #: 38-07140 Rev. *C  
Page 4 of 13  
CY2305  
CY2309  
Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices[7]  
Parameter  
Name  
Description  
Min.  
Typ.  
Max.  
Unit  
t1  
Output Frequency  
30-pF load  
10-pF load  
10  
10  
100  
133.33  
MHz  
MHz  
Duty Cycle[6] = t2 ÷ t1  
Duty Cycle[6] = t2 ÷ t1  
Rise Time[6]  
Fall Time[6]  
Output to Output Skew[6]  
Measured at 1.4V, Fout = 66.67 MHz  
Measured at 1.4V, Fout <50.0 MHz  
Measured between 0.8V and 2.0V  
Measured between 0.8V and 2.0V  
All outputs equally loaded  
40.0  
45.0  
50.0  
50.0  
60.0  
55.0  
1.50  
1.50  
250  
%
%
t3  
t4  
ns  
ns  
ps  
ps  
t5  
t6A  
Delay, REF Rising Edge to Measured at VDD/2  
CLKOUT Rising Edge[6]  
0
5
0
±350  
t6B  
t7  
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL  
1
1
8.7  
ns  
ps  
CLKOUT Rising Edge[6]  
Bypass Mode, CY2309 device only.  
Device to Device Skew[6] Measuredat VDD/2ontheCLKOUT pins  
of devices  
Output Slew Rate[6]  
700  
t8  
Measured between 0.8V and 2.0V using  
Test Circuit #2  
V/ns  
tJ  
Cycle to Cycle Jitter[6]  
PLL Lock Time[6]  
Measured at 66.67 MHz, loaded outputs  
200  
1.0  
ps  
tLOCK  
Stable power supply, valid clock  
presented on REF pin  
ms  
Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices  
Parameter  
Description  
Min.  
Max.  
3.6  
85  
Unit  
VDD  
TA  
Supply Voltage  
3.0  
V
Operating Temperature (Ambient Temperature)  
Load Capacitance, below 100 MHz  
Load Capacitance, from 100 MHz to 133 MHz  
Input Capacitance  
40  
°C  
pF  
pF  
pF  
CL  
30  
CL  
10  
CIN  
7
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices  
Parameter  
Description  
Input LOW Voltage[5]  
Input HIGH Voltage[5]  
Input LOW Current  
Test Conditions  
Min. Max. Unit  
VIL  
VIH  
IIL  
0.8  
V
V
2.0  
VIN = 0V  
50.0  
µA  
IIH  
Input HIGH Current  
Output LOW Voltage[6]  
VIN = VDD  
100.0 µA  
VOL  
IOL = 8 mA (-1)  
0.4  
V
IOH =12 mA (-1H)  
VOH  
Output HIGH Voltage[6]  
IOH = 8 mA (-1)  
IOL = 12 mA (-1H)  
2.4  
V
IDD (PD mode)  
IDD  
Power Down Supply Current  
Supply Current  
REF = 0 MHz  
25.0  
35.0  
µA  
Unloaded outputs at 66.67 MHz, SEL inputs at  
VDD  
mA  
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices[7]  
Parameter  
Name  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
t1  
Output Frequency  
30-pF load  
10-pF load  
10  
10  
100  
133.33  
MHz  
MHz  
Duty Cycle[6] = t2 ÷ t1  
Rise Time[6]  
Fall Time[6]  
Measured at 1.4V, Fout = 66.67 MHz  
Measured between 0.8V and 2.0V  
Measured between 0.8V and 2.0V  
40.0  
50.0  
60.0  
2.50  
2.50  
%
ns  
ns  
t3  
t4  
Document #: 38-07140 Rev. *C  
Page 5 of 13  
CY2305  
CY2309  
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices[7]  
Parameter  
Name  
Test Conditions  
Min.  
Typ.  
Max.  
250  
Unit  
ps  
t5  
Output to Output Skew[6]  
All outputs equally loaded  
t6A  
Delay, REF Rising Edge to Measured at VDD/2  
CLKOUT Rising Edge[6]  
0
5
±350  
ps  
t6B  
Delay, REF Rising Edge to Measured at VDD/2. Measured in  
1
8.7  
ns  
CLKOUT Rising Edge[6]  
Device to Device Skew[6]  
Cycle to Cycle Jitter[6]  
PLL Lock Time[6]  
PLL Bypass Mode, CY2309 device  
only.  
t7  
Measuredat VDD/2 on the CLKOUT  
pins of devices  
0
700  
200  
1.0  
ps  
ps  
tJ  
Measured at 66.67 MHz, loaded  
outputs  
tLOCK  
Stable power supply, valid clock  
presented on REF pin  
ms  
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices[7]  
Parameter  
Name  
Description  
Min.  
Typ.  
Max.  
Unit  
t1  
Output Frequency  
30-pF load  
10-pF load  
10  
10  
100  
133.33  
MHz  
MHz  
Duty Cycle[6] = t2 ÷ t1  
Duty Cycle[6] = t2 ÷ t1  
Rise Time[6]  
Fall Time[6]  
Output to Output Skew[6]  
Measured at 1.4V, Fout = 66.67 MHz  
Measured at 1.4V, Fout < 50.0 MHz  
Measured between 0.8V and 2.0V  
Measured between 0.8V and 2.0V  
All outputs equally loaded  
40.0  
45.0  
50.0  
50.0  
60.0  
55.0  
1.50  
1.50  
250  
%
%
t3  
ns  
ns  
ps  
ps  
t4  
t5  
t6A  
Delay, REF Rising Edge to Measured at VDD/2  
CLKOUT Rising Edge[6]  
0
5
±350  
t6B  
Delay, REF Rising Edge to Measured at VDD/2. Measured in  
1
1
8.7  
ns  
CLKOUT Rising Edge[6]  
Device to Device Skew[6]  
Output Slew Rate[6]  
Cycle to Cycle Jitter[6]  
PLL Lock Time[6]  
PLL Bypass Mode, CY2309 device  
only.  
t7  
Measured at VDD/2 on the CLKOUT  
pins of devices  
0
700  
ps  
V/ns  
ps  
t8  
Measured between 0.8V and 2.0V  
using Test Circuit #2  
tJ  
Measured at 66.67 MHz, loaded  
outputs  
200  
1.0  
tLOCK  
Stable power supply, valid clock  
presented on REF pin  
ms  
Switching Waveforms  
Duty Cycle Timing  
t
1
t
2
1.4V  
1.4V  
1.4V  
Document #: 38-07140 Rev. *C  
Page 6 of 13  
CY2305  
CY2309  
Switching Waveforms (continued)  
All Outputs Rise/Fall Time  
3.3V  
0V  
2.0V  
0.8V  
2.0V  
0.8V  
OUTPUT  
t
3
t
4
Output-Output Skew  
1.4V  
OUTPUT  
1.4V  
OUTPUT  
t
5
Input-Output Propagation Delay  
V
/2  
DD  
INPUT  
V
/2  
DD  
OUTPUT  
t
6
Device-Device Skew  
CLKOUT, Device 1  
CLKOUT, Device 2  
V
/2  
DD  
V
/2  
DD  
t
7
Document #: 38-07140 Rev. *C  
Page 7 of 13  
CY2305  
CY2309  
Typical Duty Cycle[8] and I Trends[9] for CY2305-1 and CY2309-1  
DD  
Duty Cycle Vs VDD  
Duty Cycle Vs VDD  
(for 30 pF Loads over Frequency - 3.3V, 25C)  
(for 15 pF Loads over Frequency - 3.3V, 25C)  
60  
60  
58  
56  
58  
56  
54  
52  
50  
48  
46  
44  
42  
40  
54  
52  
50  
48  
46  
44  
42  
40  
33 MHz  
66 MHz  
100 MHz  
133 MHz  
33 MHz  
66 MHz  
100 MHz  
3
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
VDD (V)  
VDD (V)  
Duty Cycle Vs Frequency  
(for 30 pF Loads over Temperature - 3.3V)  
Duty Cycle Vs Frequency  
(for 15 pF Loads over Temperature - 3.3V)  
60  
58  
56  
54  
52  
50  
48  
46  
44  
42  
40  
60  
58  
56  
54  
52  
50  
48  
46  
44  
42  
40  
-40C  
0C  
-40C  
0C  
25C  
70C  
85C  
25C  
70C  
85C  
20  
40  
60  
80  
100  
120  
140  
20  
40  
60  
80  
100  
120  
140  
Frequency (MHz)  
Frequency (MHz)  
IDD vs Number of Loaded Outputs  
(for 30 pF Loads over Frequency - 3.3V, 25C)  
IDD vs Number of Loaded Outputs  
(for 15 pF Loads over Frequency - 3.3V, 25C)  
140  
120  
100  
80  
140  
120  
100  
80  
33 MHz  
66 MHz  
100 MHz  
33 MHz  
66 MHz  
100 MHz  
60  
60  
40  
40  
20  
20  
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs  
# of Loaded Outputs  
Notes:  
8. Duty Cycle is taken from typical chip measured at 1.4V.  
9. DD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply  
Voltage (V); f = frequency (Hz)).  
I
Document #: 38-07140 Rev. *C  
Page 8 of 13  
CY2305  
CY2309  
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1H and CY2309-1H  
Duty Cycle Vs VDD  
Duty Cycle Vs VDD  
(for 30 pF Loads over Frequency - 3.3V, 25C)  
(for 15 pF Loads over Frequency - 3.3V, 25C)  
60  
60  
58  
56  
58  
56  
54  
52  
50  
48  
46  
44  
42  
40  
54  
52  
50  
48  
46  
44  
42  
40  
33 MHz  
66 MHz  
100 MHz  
133 MHz  
33 MHz  
66 MHz  
100 MHz  
3
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
VDD (V)  
VDD (V)  
Duty Cycle Vs Frequency  
(for 30 pF Loads over Temperature - 3.3V)  
Duty Cycle Vs Frequency  
(for 15 pF Loads over Temperature - 3.3V)  
60  
58  
56  
54  
52  
50  
48  
46  
44  
42  
40  
60  
58  
56  
54  
52  
50  
48  
46  
44  
42  
40  
-40C  
0C  
-40C  
0C  
25C  
70C  
85C  
25C  
70C  
85C  
20  
40  
60  
80  
100  
120  
140  
20  
40  
60  
80  
100  
120  
140  
Frequency (MHz)  
Frequency (MHz)  
IDD vs Number of Loaded Outputs  
(for 30 pF Loads over Frequency - 3.3V, 25C)  
IDD vs Number of Loaded Outputs  
(for 15 pF Loads over Frequency - 3.3V, 25C)  
160  
140  
120  
100  
80  
160  
140  
120  
100  
80  
33 MHz  
66 MHz  
100 MHz  
33 MHz  
66 MHz  
100 MHz  
60  
60  
40  
40  
20  
20  
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs  
# of Loaded Outputs  
Document #: 38-07140 Rev. *C  
Page 9 of 13  
CY2305  
CY2309  
Test Circuits  
Test Circuit # 2  
Test Circuit # 1  
V
DD  
V
1 k  
1 kΩ  
DD  
0.1 µ F  
CLK out  
0.1 µ F  
OUTPUTS  
GND  
OUTPUTS  
10 pF  
C
LOAD  
V
DD  
V
DD  
0.1 µ F  
GND  
0.1 µ F  
GND  
GND  
For parameter t (output slew rate) on -1H devices  
8
Ordering Information  
Ordering Code  
CY2305SC-1  
Package Type  
Operating Range  
Commercial  
8-pin 150-mil SOIC  
CY2305SC-1T  
CY2305SI-1  
8-pin 150-mil SOICTape and Reel  
8-pin 150-mil SOIC  
Commercial  
Industrial  
CY2305SI-1T  
CY2305SC-1H  
CY2305SC-1HT  
CY2305SI-1H  
CY2305SI-1HT  
CY2305ZC-1  
8-pin 150-mil SOICTape and Reel  
8-pin 150-mil SOIC  
Industrial  
Commercial  
Commercial  
Industrial  
8-pin 150-mil SOICTape and Reel  
8-pin 150-mil SOIC  
8-pin 150-mil SOICTape and Reel  
8-pin 150-mil TSSOP  
Industrial  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
CY2305ZC-1T  
CY2309SC-1  
8-pin 150-mil TSSOPTape and Reel  
16-pin 150-mil SOIC  
CY2309SC-1T  
CY2309SI-1  
16-pin 150-mil SOICTape and Reel  
16-pin 150-mil SOIC  
CY2309SI-1T  
CY2309SC-1H  
CY2309SC-1HT  
CY2309SI-1H  
CY2309SI-1HT  
CY2309ZC-1H  
CY2309ZC-1HT  
CY2309ZI-1H  
CY2309ZI-1HT  
16-pin 150-mil SOICTape and Reel  
16-pin 150-mil SOIC  
Industrial  
Commercial  
Commercial  
Industrial  
16-pin 150-mil SOICTape and Reel  
16-pin 150-mil SOIC  
16-pin 150-mil SOICTape and Reel  
16-pin 4.4-mm TSSOP  
Industrial  
Commercial  
Commercial  
Industrial  
16-pin 4.4-mm TSSOPTape and Reel  
16-pin 4.4-mm TSSOP  
16-pin 4.4-mm TSSOPTape and Reel  
Industrial  
Document #: 38-07140 Rev. *C  
Page 10 of 13  
CY2305  
CY2309  
Package Diagrams  
8-lead (150-Mil) SOIC S8  
51-85066-A  
16-lead (150-Mil) Molded SOIC S16  
51-85068-A  
Document #: 38-07140 Rev. *C  
Page 11 of 13  
CY2305  
CY2309  
Package Diagrams (continued)  
16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16  
51-85091-**  
Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the  
trademarks of their respective holders.  
Document #: 38-07140 Rev. *C  
Page 12 of 13  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CY2305  
CY2309  
Document History Page  
Document Title: CY2305/CY2309 Low-Cost 3.3V Zero Delay Buffer  
Document Number: 38-07140  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
110249  
111117  
10/19/01  
03/01/02  
SZV  
CKN  
Change from Spec number: 38-00530 to 38-07140  
*A  
Added t6B row to the Switching Characteristics Table; also added the letter  
Ato the t6A row  
Corrected the table title from CY2305SC-IH and CY2309SC-IH to  
CY2305SI-IH and CY2309SI-IH  
*B  
117625  
121828  
10/21/02  
12/14/02  
HWT  
RBI  
Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the  
ordering information table.  
Added the Tape and Reel option to all the existing packages:  
CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT,  
CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT,  
CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT  
*C  
Power up requirements added to Operating Conditions Information  
Document #: 38-07140 Rev. *C  
Page 13 of 13  
配单直通车
CY2309ZC-1HT产品参数
型号:CY2309ZC-1HT
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Obsolete
零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25
针数:16
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8542.31.00.01
Factory Lead Time:1 week
风险等级:5.57
系列:2309
输入调节:STANDARD
JESD-30 代码:R-PDSO-G16
JESD-609代码:e0
长度:5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3
功能数量:1
反相输出次数:
端子数量:16
实输出次数:8
最高工作温度:70 °C
最低工作温度:
输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225
电源:3.3 V
传播延迟(tpd):8.7 ns
认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.1 mm
子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:TIN LEAD
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:20
宽度:4.4 mm
最小 fmax:133.33 MHz
Base Number Matches:1
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