amily
CY62128V Family
128K x 8 Static RAM
LOW Output Enable (OE) and three-state drivers. These de-
vices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Features
• Low voltage range:
— 2.7V–3.6V (CY62128V)
— 2.3V–2.7V (CY62128V25)
Writing to the device is accomplished by taking Chip Enable
one (CE ) and Write Enable (WE) inputs LOW and the Chip
— 1.6V–2.0V (CY62128V18)
1
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Enable two (CE ) input HIGH. Data on the eight I/O pins (I/O
2
0
through I/O ) is then written into the location specified on the
7
address pins (A through A ).
0
16
Reading from the device is accomplished by taking Chip En-
able one (CE ) and Output Enable (OE) LOW while forcing
1
Write Enable (WE) and Chip Enable two (CE ) HIGH. Under
2
Functional Description
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The CY62128V family is composed of three high-performance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
The eight input/output pins (I/O through I/O ) are placed in a
0
7
high-impedance state when the device is deselected (CE
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or
2
Enable (CE ), an active HIGH Chip Enable (CE ), an active
1
2
during a write operation (CE LOW, CE HIGH, and WE LOW).
1
2
Logic Block Diagram
Pin
Configurations
Top View
SOIC
V
NC
32
31
30
1
CC
A
16
A
14
A
12
A
15
2
3
4
CE
2
29
28
WE
5
A
A
A
A
7
13
27
26
A
6
6
8
A
5
7
9
I/O0
I/O1
I/O2
25
24
23
22
21
A
A
3
INPUT BUFFER
8
9
10
11
12
13
4
A
11
OE
A
0
A
A
10
2
A
1
A
1
CE
1
I/O
7
A
2
A
0
I/O
0
I/O
1
I/O
2
I/O
6
A
3
20
19
A
4
I/O
I/O3
I/O4
I/O5
I/O6
5
4
3
14
15
16
512x256x 8
ARRAY
A
5
I/O
I/O
18
17
A
62128V-2
6
GND
A
7
A
8
POWER
DOWN
COLUMN
DECODER
CE
1
CE
WE
2
I/O7
62128V-1
OE
A
A
A
A
A
A
A
A
WE
CE
A
1
2
4
5
A
3
32
31
11
OE
16
15
14
13
12
11
10
9
8
7
6
5
4
3
17
A
A
9
8
18
19
20
21
22
23
24
25
26
27
28
29
30
2
10
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
1
CE
I/O
I/O
I/O
6
7
1
A
13
0
7
6
5
A
A
I/O
0
I/O
I/O
2
GND
I/O
I/O
4
I/O
I/O
6
I/O
CE
1
12
14
TSOP I
2
1
TSOP I / STSOP
Top View
(not to scale)
A
15
I/O
I/O
16
4
3
Reverse Pinout
V
NC
CC
CC
Top View
V
NC
A
A
A
A
A
6
A
A
4
9
GND
3
(not to scale)
I/O
A
10
11
12
13
14
15
16
16
2
15
I/O
1
CE
WE
5
14
12
2
I/O
0
A
0
A
7
7
13
A
A
A
9
1
8
A
A
2
10
31
32
2
1
5
A
A
OE
3
11
62128V-4
62128V-3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 27, 2000