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    产品型号CY7C1024AV33-12BGC的Datasheet PDF文件预览

    024AV33  
    CY7C1024AV33  
    128K x 24 Static RAM  
    Writing to the device is accomplished by taking Chip Enable  
    (CE1, CE2, CE3) active and Write Enable (WE) inputs LOW.  
    Data on the 24 I/O pins (I/O0 through I/O23) is then written into  
    the location specified on the address pins (A0 through A16).  
    Features  
    • High speed  
    — tAA = 10 ns  
    Reading from the device is accomplished by taking Chip  
    Enable (CE1, CE2, CE3) active and Output Enable (OE) LOW  
    while forcing Write Enable (WE) HIGH. Under these condi-  
    tions, the contents of the memory location specified by the  
    address pins will appear on the I/O pins.  
    • CMOS for optimum speed/power  
    • Center power/ground pinout  
    • Automatic power-down when deselected  
    • Easy memory expansion with CE1, CE2, CE3 and OE  
    options  
    The 24 input/output pins (I/O0 through I/O23) are placed in a  
    high-impedance state when the device is deselected (CE  
    HIGH), the outputs are disabled (OE HIGH), or during a write  
    operation (CE1, CE3 LOW, CE2 HIGH, and WE LOW).  
    Functional Description[1]  
    The CY7C1024AV33 is a high-performance CMOS static RAM  
    organized as 131,072 words by 24 bits. Easy memory expan-  
    sion is provided by an active LOW CE1, CE3, active HIGH  
    CE2, an active LOW Output Enable (OE), and three-state driv-  
    ers. This device has an automatic power-down feature that  
    significantly reduces power consumption when deselected.  
    The CY7C1024AV33 is available in a standard 119-ball BGA  
    package and a 100-pin TQFP package.  
    Functional Block Diagram  
    VCC  
    VSS  
    A0  
    DQ  
    0
    MEMORY ARRAY  
    128K X 24  
    DQ  
    23  
    CE#  
    CE1#  
    CE2  
    WE#  
    OE#  
    COLUMN  
    DECODER  
    CONTROL  
    A16  
    Selection Guide  
    7C1024AV33-10  
    7C1024AV33-12  
    7C1024AV33-15  
    Maximum Access Time (ns)  
    10  
    275  
    15  
    12  
    250  
    15  
    15  
    225  
    15  
    Maximum Operating Current (mA)  
    Maximum Standby Current (mA)  
    Note:  
    1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
    Cypress Semiconductor Corporation  
    Document #: 38-05149 Rev. *B  
    •
    3901 North First Street  
    •
    San Jose, CA 95134  
    •
    408-943-2600  
    Revised November 13, 2002  
    CY7C1024AV33  
    Pin Configurations  
    119 BGA  
    Top View  
    1
    2
    3
    4
    5
    6
    7
    A
    NC  
    NC  
    DQ  
    DQ  
    DQ  
    DQ  
    DQ  
    DQ  
    NC  
    DQ  
    DQ  
    DQ  
    DQ  
    DQ  
    DQ  
    NC  
    NC  
    A
    A
    A
    A
    A
    NC  
    NC  
    DQ  
    DQ  
    DQ  
    DQ  
    DQ  
    DQ  
    NC  
    DQ  
    DQ  
    DQ  
    DQ  
    DQ  
    DQ  
    NC  
    NC  
    B
    C
    D
    E
    F
    A
    A
    CE1  
    NC  
    A
    A
    NC  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    NC  
    A
    CE2  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    NC  
    A
    CE3  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    NC  
    A
    NC  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    VSS  
    VCC  
    NC  
    A
    VSS  
    VSS  
    VSS  
    VSS  
    VSS  
    VSS  
    VSS  
    VSS  
    VSS  
    VSS  
    VSS  
    NC  
    G
    H
    J
    K
    L
    M
    N
    P
    R
    T
    WE  
    OE  
    U
    A
    A
    A
    A
    Document #: 38-05149 Rev. *B  
    Page 2 of 11  
    CY7C1024AV33  
    Pin Configurations (continued)  
    100-pin TQFP  
    Top View  
    NC  
    VCC  
    VSS  
    DQ16  
    DQ17  
    VSS  
    VCC  
    DQ18  
    DQ19  
    VSS  
    VCC  
    DQ20  
    DQ21  
    VCC  
    NC  
    NC  
    1
    2
    3
    4
    5
    6
    7
    8
    80  
    79  
    78  
    77  
    76  
    75  
    74  
    73  
    72  
    71  
    70  
    69  
    68  
    67  
    66  
    65  
    64  
    63  
    62  
    61  
    60  
    59  
    58  
    57  
    56  
    55  
    54  
    53  
    52  
    51  
    VCC  
    VSS  
    DQ0  
    DQ1  
    VSS  
    VCC  
    DQ2  
    DQ3  
    VSS  
    VCC  
    DQ4  
    DQ5  
    VCC  
    NC  
    9
    10  
    11  
    12  
    13  
    14  
    15  
    16  
    17  
    18  
    19  
    20  
    21  
    22  
    23  
    24  
    25  
    26  
    27  
    28  
    29  
    30  
    NC  
    VSS  
    NC  
    VSS  
    DQ6  
    DQ7  
    VCC  
    VSS  
    DQ8  
    DQ9  
    VCC  
    VSS  
    DQ10  
    DQ11  
    VCC  
    VSS  
    NC  
    DQ22  
    DQ23  
    VCC  
    VSS  
    DQ12  
    DQ13  
    VCC  
    VSS  
    DQ14  
    DQ15  
    VCC  
    VSS  
    NC  
    Current into Outputs (LOW) ........................................ 20 mA  
    Maximum Ratings  
    Static Discharge Voltage............................................ >2001V  
    (per MIL-STD-883, Method 3015)  
    (Above which the useful life may be impaired. For user guide-  
    lines, not tested.)  
    Latch-Up Current..................................................... >200 mA  
    Storage Temperature .................................–65°C to +150°C  
    Ambient Temperature with  
    Power Applied.............................................–55°C to +125°C  
    Operating Range  
    Ambient  
    Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V  
    Range  
    Commercial  
    Industrial  
    Temperature  
    0°C to +70°C  
    –40°C to +85°C  
    VCC  
    DC Voltage Applied to Outputs  
    3.3V ±10%  
    3.3V ±10%  
    in High Z State[2] ....................................–0.5V to VCC + 0.5V  
    DC Input Voltage[2].................................–0.5V to VCC + 0.5V  
    Note:  
    2. Minimum Voltage is = –2.0V for pulse durations of less than 20 ns.  
    Document #: 38-05149 Rev. *B  
    Page 3 of 11  
    CY7C1024AV33  
    Electrical Characteristics Over the Operating Range  
    1024AV33-10  
    1024AV33-12  
    1024AV33-15  
    Parameter  
    VOH  
    Description  
    Test Conditions[3]  
    Min.  
    Max.  
    Min.  
    Max.  
    Min.  
    Max.  
    Unit  
    Output HIGH Voltage  
    VCC = Min.,  
    IOH = –4.0 mA  
    2.4  
    2.4  
    2.4  
    V
    VOL  
    VIH  
    Output LOW Voltage  
    Input HIGH Voltage  
    VCC = Min.,  
    IOL = 8.0 mA  
    0.4  
    0.4  
    0.4  
    V
    V
    2.2  
    VCC  
    + 0.3  
    2.2  
    VCC  
    + 0.3  
    2.2  
    VCC  
    + 0.3  
    VIL  
    IIX  
    Input LOW Voltage[2]  
    Input Load Current  
    –0.3  
    –3  
    0.8  
    +3  
    +5  
    –0.3  
    –3  
    0.8  
    +3  
    +5  
    –0.3  
    –3  
    0.8  
    +3  
    +5  
    V
    GND < VI < VCC  
    µA  
    µA  
    IOZ  
    Output Leakage  
    Current  
    GND < VI < VCC  
    ,
    –5  
    –5  
    –5  
    Output Disabled  
    ICC  
    VCC Operating  
    Supply Current  
    VCC = Max.,  
    IOUT = 0 mA,  
    f = fMAX = 1/tRC  
    275  
    60  
    250  
    60  
    225  
    60  
    mA  
    mA  
    mA  
    ISB1  
    Automatic CE  
    Power-Down Current  
    —TTL Inputs  
    Max. VCC, CE > VIH  
    VIN > VIH or  
    VIN < VIL, f = fMAX  
    ISB2  
    Automatic CE  
    Max. VCC  
    ,
    15  
    15  
    15  
    Power-Down Current  
    —CMOS Inputs  
    CE > VCC – 0.3V,  
    VIN > VCC – 0.3V,  
    or VIN < 0.3V, f = 0  
    Capacitance[4]  
    Parameter  
    Description  
    Input Capacitance  
    Output Capacitance  
    Test Conditions  
    TA = 25°C, f = 1 MHz,  
    VCC = 3.3V  
    Max.  
    10  
    Unit  
    CIN  
    pF  
    pF  
    COUT  
    8
    AC Test Loads and Waveforms  
    R1 480 Ω  
    ALL INPUT PULSES  
    90%  
    R1 480 Ω  
    3.3V  
    3.3V  
    OUTPUT  
    3.0V  
    GND  
    90%  
    10%  
    OUTPUT  
    10%  
    R2  
    255Ω  
    R2  
    255Ω  
    30 pF  
    5 pF  
    ≤ 3 ns  
    ≤ 3 ns  
    INCLUDING  
    JIG AND  
    SCOPE  
    INCLUDING  
    JIG AND  
    SCOPE  
    (b)  
    (a)  
    THÉ  
    Equivalent to:  
    VENIN EQUIVALENT  
    167 Ω  
    1.73V  
    OUTPUT  
    Notes:  
    3. CE is a combination of CE1, CE2, and CE3  
    4. Tested initially and after any design or process changes that may affect these parameters.  
    Document #: 38-05149 Rev. *B  
    Page 4 of 11  
    CY7C1024AV33  
    Switching Characteristics[5] Over the Operating Range  
    7C1024AV33-10  
    7C1024AV33-12  
    7C1024AV33-15  
    Parameter  
    Description[3]  
    Min.  
    10  
    Max.  
    Min.  
    Max.  
    Min.  
    15  
    3
    Max.  
    Unit  
    READ CYCLE  
    tRC  
    Read Cycle Time  
    12  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    tAA  
    Address to Data Valid  
    Data Hold from Address Change  
    CE active to Data Valid  
    OE LOW to Data Valid  
    OE LOW to Low Z  
    OE HIGH to High Z[6, 7]  
    CE active to Low Z[7]  
    CE inactive to High Z[6, 7]  
    CE active to Power-Up  
    CE inactive to Power-Down  
    10  
    12  
    15  
    tOHA  
    tACE  
    tDOE  
    tLZOE  
    tHZOE  
    tLZCE  
    tHZCE  
    tPU  
    3
    3
    10  
    5
    12  
    6
    15  
    7
    0
    3
    0
    0
    3
    0
    0
    3
    0
    5
    5
    6
    6
    6
    6
    tPD  
    10  
    12  
    15  
    WRITE CYCLE[8, 9]  
    tWC  
    tSCE  
    tAW  
    tHA  
    Write Cycle Time  
    10  
    8
    12  
    9
    15  
    9
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    CE active to Write End  
    Address Set-Up to Write End  
    Address Hold from Write End  
    Address Set-Up to Write Start  
    WE Pulse Width  
    7
    8
    8
    0
    0
    0
    tSA  
    0
    0
    0
    tPWE  
    tSD  
    7
    8
    8
    Data Set-Up to Write End  
    Data Hold from Write End  
    WE HIGH to Low Z[7]  
    5
    6
    6
    tHD  
    0
    0
    0
    tLZWE  
    3
    3
    3
    tHZWE  
    WE LOW to High Z[6, 7]  
    5
    6
    6
    Notes:  
    5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
    OL/IOH and 30-pF load capacitance.  
    I
    6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
    7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
    8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these  
    signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
    9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
    .
    Document #: 38-05149 Rev. *B  
    Page 5 of 11  
    CY7C1024AV33  
    Switching Waveforms  
    Read Cycle No. 1[10, 11]  
    t
    RC  
    ADDRESS  
    t
    AA  
    t
    OHA  
    DATA OUT  
    PREVIOUS DATA VALID  
    DATA VALID  
    Read Cycle No. 2 (OE Controlled)[3, 11, 12]  
    ADDRESS  
    CE  
    t
    RC  
    t
    ACE  
    OE  
    t
    HZOE  
    t
    DOE  
    t
    HZCE  
    t
    LZOE  
    HIGH  
    IMPEDANCE  
    HIGH IMPEDANCE  
    DATA OUT  
    DATA VALID  
    t
    LZCE  
    t
    PD  
    I
    t
    PU  
    CC  
    V
    CC  
    50%  
    50%  
    SUPPLY  
    CURRENT  
    I
    SB  
    Write Cycle No. 1 (CE Controlled)[3, 13, 14]  
    t
    WC  
    ADDRESS  
    CE  
    t
    SCE  
    t
    SA  
    t
    SCE  
    t
    t
    HA  
    AW  
    t
    PWE  
    WE  
    t
    t
    HD  
    SD  
    DATA I/O  
    DATA VALID  
    Notes:  
    10. Device is continuously selected. OE, CE = VIL.  
    11. WE is HIGH for read cycle.  
    12. Address valid prior to or coincident with CE transition LOW.  
    13. Data I/O is high impedance if OE = VIH  
    .
    14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
    Document #: 38-05149 Rev. *B  
    Page 6 of 11  
    CY7C1024AV33  
    Switching Waveforms (continued)  
    Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]  
    t
    WC  
    ADDRESS  
    CE  
    t
    SCE  
    t
    t
    HA  
    AW  
    t
    SA  
    t
    PWE  
    WE  
    OE  
    t
    t
    SD  
    HD  
    DATA I/O  
    DATA VALID  
    IN  
    NOTE 15  
    t
    HZOE  
    Write Cycle No. 3 (WE Controlled, OE LOW)[3, 14]  
    t
    WC  
    ADDRESS  
    CE  
    t
    SCE  
    t
    t
    HA  
    AW  
    t
    SA  
    t
    PWE  
    WE  
    t
    t
    HD  
    SD  
    NOTE 15  
    DATA I/O  
    DATA VALID  
    t
    t
    LZWE  
    HZWE  
    Note:  
    15. During this period the I/Os are in the output state and input signals should not be applied.  
    Document #: 38-05149 Rev. *B  
    Page 7 of 11  
    CY7C1024AV33  
    Truth Table  
    CE1  
    H
    CE2  
    CE3  
    X
    OE  
    X
    WE  
    X
    I/O0–I/O23  
    High Z  
    Mode  
    Power  
    X
    L
    Power-Down  
    Power-Down  
    Power-Down  
    Read  
    Standby (ISB  
    Standby (ISB  
    Standby (ISB  
    Active (ICC  
    Active (ICC  
    Active (ICC  
    )
    X
    X
    X
    X
    High Z  
    High Z  
    Data Out  
    Data In  
    High Z  
    )
    X
    X
    H
    H
    H
    H
    X
    X
    )
    L
    L
    L
    H
    )
    L
    L
    X
    L
    Write  
    )
    L
    L
    H
    H
    Selected, Outputs Disabled  
    )
    Ordering Information  
    Speed  
    (ns)  
    Package  
    Name  
    Operating  
    Range  
    Ordering Code  
    Package Type  
    10  
    CY7C1024AV33-10AC  
    CY7C1024AV33-10BGC  
    CY7C1024AV33-12AC  
    CY7C1024AV33-12BGC  
    CY7C1024AV33-12BGI  
    CY7C1024AV33-15AC  
    CY7C1024AV33-15BGC  
    CY7C1024AV33-15BGI  
    A101  
    100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) Commercial  
    119-Ball PBGA  
    BG119  
    A101  
    12  
    15  
    100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm)  
    119-Ball PBGA  
    BG119  
    BG119  
    A101  
    119-Ball PBGA  
    Industrial  
    100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) Commercial  
    119-Ball PBGA  
    BG119  
    BG119  
    119-Ball PBGA  
    Industrial  
    Document #: 38-05149 Rev. *B  
    Page 8 of 11  
    CY7C1024AV33  
    Package Diagrams  
    100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101  
    51-85050-*A  
    Document #: 38-05149 Rev. *B  
    Page 9 of 11  
    CY7C1024AV33  
    Package Diagrams (continued)  
    119-Lead PBGA (14 x 22 x 2.4 mm) BG119  
    51-85115-*B  
    All product and company names mentioned in this document may be the trademarks of their respective holders.  
    Document #: 38-05149 Rev. *B  
    Page 10 of 11  
    © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
    of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
    its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
    Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
    CY7C1024AV33  
    Document History Page  
    Document Title: CY7C1024AV33 128K x 24 Static RAM  
    Document Number: 38-05149  
    Issue  
    Date  
    Orig. of  
    REV.  
    **  
    ECN NO.  
    109893  
    116473  
    121472  
    Change Description of Change  
    09/22/01  
    09/16/02  
    11/14/02  
    SZV  
    CEA  
    DSG  
    Change from Spec number: 38-00983 to 38-05149  
    Add applications foot note to data sheet, page 1.  
    Update package diagram 51-85115 (BG119) to rev. *B  
    *A  
    *B  
    Document #: 38-05149 Rev. *B  
    Page 11 of 11  
    配单直通车
    CY7C1024AV33-12BGC产品参数
    型号:CY7C1024AV33-12BGC
    是否Rohs认证： 不符合
    生命周期：Obsolete
    零件包装代码：BGA
    包装说明：14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
    针数：119
    Reach Compliance Code：not_compliant
    ECCN代码：3A991.B.2.A
    HTS代码：8542.32.00.41
    风险等级：5.74
    最长访问时间：12 ns
    I/O 类型：COMMON
    JESD-30 代码：R-PBGA-B119
    JESD-609代码：e0
    长度：19.5 mm
    内存密度：3145728 bit
    内存集成电路类型：STANDARD SRAM
    内存宽度：24
    湿度敏感等级：3
    功能数量：1
    端子数量：119
    字数：131072 words
    字数代码：128000
    工作模式：ASYNCHRONOUS
    最高工作温度：70 °C
    最低工作温度：
    组织：128KX24
    输出特性：3-STATE
    封装主体材料：PLASTIC/EPOXY
    封装代码：BGA
    封装等效代码：BGA119,7X17,50
    封装形状：RECTANGULAR
    封装形式：GRID ARRAY
    并行/串行：PARALLEL
    峰值回流温度（摄氏度）：220
    电源：3.3 V
    认证状态：Not Qualified
    座面最大高度：2.4 mm
    最大待机电流：0.015 A
    最小待机电流：3 V
    子类别：SRAMs
    最大压摆率：0.25 mA
    最大供电电压 (Vsup)：3.6 V
    最小供电电压 (Vsup)：3 V
    标称供电电压 (Vsup)：3.3 V
    表面贴装：YES
    技术：CMOS
    温度等级：COMMERCIAL
    端子面层：Tin/Lead (Sn/Pb)
    端子形式：BALL
    端子节距：1.27 mm
    端子位置：BOTTOM
    处于峰值回流温度下的最长时间：NOT SPECIFIED
    宽度：12 mm
    Base Number Matches：1
    •  
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