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产品型号CY7C106B-15VCT的概述

CY7C106B-15VCT芯片概述 CY7C106B-15VCT是一种高性能、低功耗的静态随机存取存储器（SRAM），由Cyprus Semiconductor Corporation制造。这款芯片在电子设备中被广泛应用，因其结构简单、速度快、功耗低而受到青睐。该芯片的静态设计允许快速的数据读取和写入操作，使其在需要快速存储和访问的应用场合表现优异。该芯片采用了CMOS技术，提供了在高频率下工作的能力。由于其较低的功耗和较高的速度，CY7C106B-15VCT经常用于对动力和效率有高要求的工业设备、消费电子产品及通信设备等领域。 CY7C106B-15VCT的详细参数 - 存储容量：1 Mbit（128K x 8） - 访问时间：15 ns（最小） - 工作电压：2.7V至5.5V - 功耗： - 启动功耗：220 mW（最大） - 待机功耗：1 μA（最大） - I/O端...

产品型号CY7C106B-15VI的Datasheet PDF文件预览

1CY7C1006B

CY7C106B

CY7C1006B

256K x 4 Static RAM

Enable (CE), an active LOW Output Enable (OE), and

three-state drivers. These devices have an automatic pow-

er-down feature that reduces power consumption by more

than 65% when the devices are deselected.

Features

• High speed

— t_AA= 12 ns

• CMOS for optimum speed/power

• Low active power

Writing to the devices is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the four I/O

pins (I/O₀through I/O₃) is then written into the location speci-

fied on the address pins (A₀through A₁₇).

— 495 mW

• Low standby power

— 275 mW

Reading from the devices is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the four I/O pins.

• 2.0V data retention (optional)

— 100 µW

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

The four input/output pins (I/O₀through I/O₃) are placed in a

high-impedance state when the devices are deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE and WE LOW).

Functional Description

The CY7C106B and CY7C1006B are high-performance

CMOS static RAMs organized as 262,144 words by 4 bits.

Easy memory expansion is provided by an active LOW Chip

The CY7C106B is available in a standard 400-mil-wide SOJ;

the CY7C1006B is available in a standard 300-mil-wide SOJ.

Logic Block Diagram

Pin Configuration

SOJ

Top View

INPUTBUFFER

I/O

GND

512 x 512 x 4

ARRAY

C106B–2

POWER

DOWN

COLUMN

DECODER

C106B–1

Selection Guide

7C106B-12

7C1006B-12

7C106B-15

7C1006B-15

7C106B-20

7C1006B-20

7C106B-25

7C1006B-25

7C106B-35

Maximum Access Time (ns)

Maximum Operating

Current (mA)

Maximum Standby

Current (mA)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05037 Rev. **

Revised August 24, 2001

CY7C106B

CY7C1006B

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Latch-Up Current..................................................... >200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V_CCRelative to GND^[1].... –0.5V to +7.0V

Operating Range

Ambient

Range

Commercial

Industrial

Temperature^[2]

0°C to +70°C

V_CC

DC Voltage Applied to Outputs

in High Z State^[1]....................................–0.5V to V_CC+ 0.5V

5V ± 10%

DC Input Voltage^[1].................................–0.5V to V_CC+ 0.5V

–45°C to +85°C

Document #: 38-05037 Rev. **

Page 2 of 10

CY7C106B

CY7C1006B

Electrical Characteristics Over the Operating Range

7C106B-12

7C106B-15

7C106B-20

7C1006B-12 7C1006B-15 7C1006B-20

Parameter

V_OH

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Test Conditions

V_CC= Min., I_OH= –4.0 mA

V_CC= Min., I_OL= 8.0 mA

Min. Max. Min. Max. Min. Max. Unit

2.4

2.2

2.4

V_OL

0.4

V_IH

V_CC

2.2

V_CC

2.2

V_CC

+0.3

V_IL

I_IX

Input LOW Voltage^[1]

Input Load Current

–0.3

–1

0.8

–0.3

–1

0.8

–0.3

–1

0.8

GND < V_I< V_CC

µA

I_OZ

Output Leakage Current GND < V_I< V_CC

–5

Output Disabled

I_OS

I_CC

Output Short

V_CC= Max., V_OUT= GND

–300

–300 mA

Circuit Current^[3]

V_CCOperating

Supply Current

V_CC= Max.,

I_OUT= 0 mA,

f = f_MAX= 1/t_RC

I_SB1

Automatic CE

Power-Down Current

—TTL Inputs

Max. V_CC, CE > V_IH,

V_IN> V_IHor V_IN< V_IL,

f = f_MAX

I_SB2

Automatic CE

Max. V_CC

Com’l

Power-Down Current

—CMOS Inputs

CE > V_CC– 0.3V,

V_IN> V_CC– 0.3V

or V_IN< 0.3V, f=0

V_OH

V_OL

V_IH

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

V_CC= Min., I_OH= –4.0 mA

V_CC= Min., I_OL= 8.0 mA

2.4

0.4

2.2 V_CC

0.3

2.2 V_CC

0.3

V_IL

I_IX

Input LOW Voltage^[1]

Input Load Current

–0.3

–1

0.8

–0.3

–1

0.8

GND < V_I< V_CC

µA

I_OZ

Output Leakage Current GND < V_I< V_CC

–5

Output Disabled

I_OS

I_CC

Output Short

V_CC= Max., V_OUT= GND

–300

–300 mA

Circuit Current^[3]

V_CCOperating

Supply Current

V_CC= Max.,

I_OUT= 0 mA,

f = f_MAX= 1/t_RC

I_SB1

Automatic CE

Power-Down Current

—TTL Inputs

Max. V_CC, CE > V_IH,

V_IN> V_IHor V_IN< V_IL,

f = f_MAX

I_SB2

Automatic CE

Max. V_CC

Com’l

Power-Down Current

—CMOS Inputs

CE > V_CC– 0.3V,

V_IN> V_CC– 0.3V

or V_IN< 0.3V, f = 0

Notes:

1. V_IL(min.) = –2.0V for pulse durations of less than 20 ns.

2. T_Ais the “instant on” case temperature.

3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

Document #: 38-05037 Rev. **

Page 3 of 10

CY7C106B

CY7C1006B

Capacitance^[4]

Parameter

C_IN: Addresses

C_IN: Controls

C_OUT

Description

Test Conditions

T_A= 25°C, f = 1 MHz,

V_CC= 5.0V

Max.

Unit

Input Capacitance

Output Capacitance

AC Test Loads and Waveforms

ALL INPUT PULSES

90%

R1 480Ω

3.0V

GND

OUTPUT

90%

10%

OUTPUT

10%

255Ω

30 pF

5 pF

Rise Time < 1V/ns

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

Fall Time < 1V/ns

C106B–4

C106B–3

(a)

(b)

Equivalent to:

THÉVENIN EQUIVALENT

167Ω

1.73V

OUTPUT

Note:

4. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-05037 Rev. **

Page 4 of 10

CY7C106B

CY7C1006B

Switching Characteristics Over the Operating Range^[5]

7C106B-12 7C106B-15 7C106B-20 7C106B-25

7C1006B-12 7C1006B-15 7C1006B-20 7C1006B-25 7C106B-35

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

t_RC

Read Cycle Time

t_AA

Address to Data Valid

Data Hold from Address Change

CE LOW to Data Valid

OE LOW to Data Valid

OE LOW to Low Z

OE HIGH to High Z^{[6, 7]}

CE LOW to Low Z^[7]

CE HIGH to High Z^{[6, 7]}

CE LOW to Power-Up

CE HIGH to Power-Down

t_OHA

t_ACE

t_DOE

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_PU

t_PD

WRITE CYCLE^{[8, 9]}

t_WC

t_SCE

t_AW

t_HA

Write Cycle Time

CE LOW to Write End

Address Set-Up to Write End

Address Hold from Write End

Address Set-Up to Write Start

WE Pulse Width

t_SA

t_PWE

t_SD

Data Set-Up to Write End

Data Hold from Write End

WE HIGH to Low Z^[7]

t_HD

t_LZWE

t_HZWE

WE LOW to High Z^{[6, 7]}

Notes:

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

_OL/I_OHand 30–pF load capacitance.

6. t_HZOE, t_HZCE, and t_HZWEare specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

7. At any given temperature and voltage condition, t_HZCEis less than t_LZCE, t_HZOEis less than t_LZOE, and t_HZWEis less than t_LZWEfor any given device.

8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these

signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t_HZWEand t_SD

Document #: 38-05037 Rev. **

Page 5 of 10

CY7C106B

CY7C1006B

Data Retention Characteristics Over the Operating Range

Parameter

V_DR

I_CCDR

Description

V_CCfor Data Retention

Conditions^[10]

Min.

Max.

Unit

2.0

Data Retention Current

V_CC= V_DR= 2.0V,

CE > V_CC– 0.3V,

V_IN> V_CC– 0.3V or

V_IN< 0.3V

250

µA

[4]

t_CDR

Chip Deselect to Data Retention Time

Operation Recovery Time

[4]

t_R

200

µs

Data Retention Waveform

DATA RETENTION MODE

> 2V

4.5V

CDR

C106B–5

Switching Waveforms

Read Cycle No.1^{[11, 12]}

ADDRESS

OHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

C106B–6

Read Cycle No. 2 (OE Controlled)^{[12, 13]}

ADDRESS

ACE

HZOE

DOE

HZCE

LZOE

HIGH

IMPEDANCE

HIGH IMPEDANCE

DATA VALID

DATA OUT

LZCE

SUPPLY

CURRENT

50%

C106B–7

Notes:

10. No input may exceed V_CC+0.5V.

11. Device is continuously selected, OE and CE = V_IL.

12. WE is HIGH for read cycle.

13. Address valid prior to or coincident with CE transition LOW.

Document #: 38-05037 Rev. **

Page 6 of 10

CY7C106B

CY7C1006B

Switching Waveforms (continued)

Write Cycle No. 1 (CE Controlled)^{[14, 15]}

ADDRESS

SCE

PWE

DATA I/O

DATA VALID

C106B–8

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)^{[14, 15]}

ADDRESS

SCE

PWE

DATA I/O

DATA VALID

HZOE

C106B–9

Notes:

14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

15. Data I/O is high impedance if OE = V_IH

Document #: 38-05037 Rev. **

Page 7 of 10

CY7C106B

CY7C1006B

Switching Waveforms (continued)

Write Cycle No. 3 (WE Controlled, OE LOW)^{[9, 15]}

ADDRESS

SCE

PWE

DATA I/O

DATA VALID

LZWE

HZWE

C106B–10

Truth Table

Input/Output

High Z

Mode

Power

Power-Down

Read

Standby (I_SB

)

Data Out

Data In

High Z

Active (I_CC

Active (I_CC)

)

Write

)

Selected, Outputs Disabled

Ordering Information

Speed

Package

Name

Operating

Range

(ns)

Ordering Code

CY7C106B-12VC

Package Type

V28

V21

V28

V21

V28

V21

V28

V21

V28

V21

V28

V21

V28

V21

V28

28-Lead (400-Mil) Molded SOJ

28-Lead (300-Mil) Molded SOJ

28-Lead (400-Mil) Molded SOJ

28-Lead (300-Mil) Molded SOJ

28-Lead (400-Mil) Molded SOJ

28-Lead (300-Mil) Molded SOJ

28-Lead (400-Mil) Molded SOJ

28-Lead (300-Mil) Molded SOJ

28-Lead (400-Mil) Molded SOJ

28-Lead (300-Mil) Molded SOJ

28-Lead (400-Mil) Molded SOJ

28-Lead (300-Mil) Molded SOJ

28-Lead (400-Mil) Molded SOJ

28-Lead (300-Mil) Molded SOJ

28-Lead (400-Mil) Molded SOJ

Commercial

Industrial

CY7C1006B-12VC

CY7C106B-15VC

CY7C1006B-15VC

CY7C106B-15VI

CY7C1006B-15VI

CY7C106B-20VC

CY7C1006B-20VC

CY7C106B-20VI

CY7C1006B-20VI

CY7C106B-25VC

CY7C1006B-25VC

CY7C106B-25VI

CY7C1006B-25VI

CY7C106B-35VC

CY7C106B-35VI

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Document #: 38-05037 Rev. **

Page 8 of 10

CY7C106B

CY7C1006B

Package Diagrams

28-Lead (300-Mil) Molded SOJ V21

51-85031-B

28-Lead (400-Mil) Molded SOJ V28

51-85032-A

Document #: 38-05037 Rev. **

Page 9 of 10

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C106B

CY7C1006B

Document Title: CY7C106B, CY7C1006B 256K x 4 Static RAM

Document Number: 38-05037

Issue

ECN NO. Date

Orig. of

Change

REV.

Description of Change

106831

09/17/01

SZV

Change from Spec number: 38-00955 to 38-05037

Document #: 38-05037 Rev. **

Page 10 of 10

CY7C106B-15VCT相关文章

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CY7C106B-15VI产品参数

型号:	CY7C106B-15VI
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	CYPRESS SEMICONDUCTOR CORP
零件包装代码：	SOJ
包装说明：	0.400 INCH, SOJ-28
针数：	28
Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41
风险等级：	5.54
Is Samacsys：	N
最长访问时间：	15 ns
I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-J28
JESD-609代码：	e0
长度：	18.415 mm
内存密度：	1048576 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	4
湿度敏感等级：	1
功能数量：	1
端子数量：	28
字数：	262144 words
字数代码：	256000
工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-45 °C
组织：	256KX4
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOJ
封装等效代码：	SOJ28,.44
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	3.7592 mm
最大待机电流：	0.00025 A
最小待机电流：	2 V
子类别：	SRAMs
最大压摆率：	0.155 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	TIN LEAD
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm
Base Number Matches：	1

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