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产品型号CY7C185-15VC的概述

CY7C185-15VC芯片的概述 CY7C185-15VC是一款高性能的静态随机存取存储器（SRAM），由意法半导体（Cypress Semiconductor）公司设计和制造。该芯片专为高速数据处理和存储需求而设计，广泛应用于各种嵌入式系统、通信设备、网络设备以及工业自动化等领域。由于其卓越的性能和高可靠性，CY7C185-15VC在市场上获得了良好的声誉。这款SRAM芯片采用了150毫微米的工艺技术，具有较快的访问时间和较低的功耗，使其在快速存取数据的场合中表现出色。CY7C185-15VC的存储容量为512K位，通常以64K × 8位的架构来组织，这使其适合需要大量数据读取和写入的应用。 CY7C185-15VC的详细参数 CY7C185-15VC的主要参数包括： - 存储类型：静态随机存取存储器（SRAM） - 存储容量：512K位（64K × 8位） - 访问速度：15纳...

产品型号CY7C185-15VC的Datasheet PDF文件预览

185

CY7C185

8K x 8 Static RAM

provided by an active LOW chip enable (CE₁), an active HIGH

chip enable (CE₂), and active LOW output enable (OE) and

three-state drivers. This device has an automatic power-down

feature (CE₁or CE₂), reducing the power consumption by 70%

when deselected. The CY7C185 is in a standard 300-mil-wide

DIP, SOJ, or SOIC package.

Features

• High speed

— 15 ns

• Fast t_DOE

• Low active power

An active LOW write enable signal (WE) controls the writ-

ing/reading operation of the memory. When CE₁and WE in-

puts are both LOW and CE₂is HIGH, data on the eight data

input/output pins (I/O₀through I/O₇) is written into the memory

location addressed by the address present on the address

pins (A₀through A₁₂). Reading the device is accomplished by

selecting the device and enabling the outputs, CE₁and OE

active LOW, CE₂active HIGH, while WE remains inactive or

HIGH. Under these conditions, the contents of the location ad-

dressed by the information on address pins are present on the

eight data input/output pins.

— 715 mW

• Low standby power

— 220 mW

• CMOS for optimum speed/power

• Easy memory expansion with CE₁, CE₂, and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

Functional Description^[1]

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH. A die coat is used to insure alpha immunity.

The CY7C185 is a high-performance CMOS static RAM orga-

nized as 8192 words by 8 bits. Easy memory expansion is

Logic Block Diagram

Pin Configurations

DIP/SOJ/SOIC

Top View

I/O

INPUT BUFFER

I/O

GND

256 x 32 x 8

ARRAY

I/O

POWER

DOWN

COLUMN DECODER

Selection Guide^[2]

7C185-15

7C185-20

7C185-25

7C185-35

Maximum Access Time (ns)

Maximum Operating Current (mA)

130

110

100

Maximum Standby Current (mA)

40/15

20/15

Note:

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

2. For military specifications, see the CY7C185A data sheet.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05043 Rev. *A

Revised September 13, 2002

CY7C185

Output Current into Outputs (LOW)............................. 20 mA

Maximum Ratings

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current.................................................... >200 mA

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Ambient

Supply Voltage to Ground Potential............... –0.5V to +7.0V

Range

Commercial

Industrial

Temperature

0°C to +70°C

–40°C to +85°C

V_CC

DC Voltage Applied to Outputs

5V ± 10%

in High Z State^[3]............................................ –0.5V to +7.0V

DC Input Voltage^[3]......................................... –0.5V to +7.0V

Electrical Characteristics Over the Operating Range

7C185-15

7C185-20

Min. Max.

Parameter

V_OH

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Test Conditions

Min.

Max.

Unit

V_CC= Min., I_OH= –4.0 mA

2.4

V_OL

V_IH

V_CC= Min., I_OL= 8.0 mA

0.4

2.2

V_CC

2.2

V_CC+

0.3V

0.8

0.3V

0.8

V_IL

I_IX

Input LOW Voltage^[3]

Input Load Current

–0.5

–5

–0.5

–5

GND ≤ V_I≤ V_CC

µA

I_OZ

Output Leakage

Current

GND ≤ V_I≤ V_CC

–5

Output Disabled

I_OS

Output Short

V_CC= Max.,

V_OUT= GND

–300

Circuit Current^[4]

I_CC

V_CCOperating

Supply Current

V_CC= Max.,

I_OUT= 0 mA

130

110

I_SB1

I_SB2

Automatic

Power-Down Current

Max. V_CC, CE₁≥ V_IHor CE₂≤ V_IL

Min. Duty Cycle = 100%

Automatic

Power-Down Current

Max. V_CC, CE₁≥ V_CC– 0.3V,

or CE₂≤ 0.3V

V_IN≥ V_CC– 0.3V or V_IN≤ 0.3V

Notes:

3. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.

4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

Document #: 38-05043 Rev. *A

Page 2 of 11

CY7C185

Electrical Characteristics Over the Operating Range (continued)

7C185-25

7C185-35

Parameter

V_OH

Description

Test Conditions

V_CC= Min., I_OH= –4.0 mA

V_CC= Min., I_OL= 8.0 mA

Min.

Max.

Min.

Max.

Unit

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

2.4

V_OL

0.4

V_IH

2.2

V_CC

2.2

V_CC

0.3V

V_IL

I_IX

Input LOW Voltage^[3]

Input Load Current

–0.5

–5

0.8

–0.5

–5

0.8

GND ≤ V_I≤ V_CC

µA

I_OZ

Output Leakage

Current

GND ≤ V_I≤ V_CC

–5

Output Disabled

I_OS

Output Short

V_CC= Max.,

V_OUT= GND

–300

100

–300

100

Circuit Current^[4]

I_CC

V_CCOperating

Supply Current

V_CC= Max.,

I_OUT= 0 mA

I_SB1

I_SB2

Automatic

Power-Down Current

Max. V_CC, CE₁≥ V_IHor CE₂≤ V_IL

Min. Duty Cycle = 100%

Automatic

Power-Down Current

Max. V_CC, CE₁≥ V_CC– 0.3V

or CE₂≤ 0.3V

V_IN≥ V_CC– 0.3V or V_IN≤ 0.3V

Capacitance^[5]

Parameter

Description

Input Capacitance

Output Capacitance

Test Conditions

Max.

Unit

C_IN

T_A= 25°C, f = 1 MHz,

V_CC= 5.0V

C_OUT

Note:

5. Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

R1 481Ω

ALL INPUT PULSES

90%

OUTPUT

3.0V

GND

90%

10%

30 pF

5 pF

255Ω

10%

INCLUDING

JIG AND

SCOPE

INCLUDING

JIGAND

≤ 5 ns

SCOPE

(a)

(b)

Equivalent to:

THÉVENIN EQUIVALENT

167Ω

OUTPUT

1.73V

Document #: 38-05043 Rev. *A

Page 3 of 11

CY7C185

Switching Characteristics Over the Operating Range^[6]

7C185-15

Min. Max.

7C185-20

Min. Max.

7C185-25

Min. Max.

7C185-35

Min. Max.

Parameter

Read Cycle

t_RC

Description

Unit

Read Cycle Time

t_AA

Address to Data Valid

Data Hold from Address Change

CE₁LOW to Data Valid

CE₂HIGH to Data Valid

OE LOW to Data Valid

OE LOW to Low Z

OE HIGH to High Z^[7]

CE₁LOW to Low Z^[8]

CE₂HIGH to Low Z

t_OHA

t_ACE1

t_ACE2

t_DOE

t_LZOE

t_HZOE

t_LZCE1

t_LZCE2

t_HZCE

CE₁HIGH to High Z^{[7, 8]}

CE₂LOW to High Z

t_PU

t_PD

CE₁LOW to Power-Up

CE₂to HIGH to Power-Up

CE₁HIGH to Power-Down

CE₂LOW to Power-Down

Write Cycle^[9]

t_WC

Write Cycle Time

t_SCE1

t_SCE2

t_AW

CE₁LOW to Write End

CE₂HIGH to Write End

Address Set-up to Write End

Address Hold from Write End

Address Set-up to Write Start

WE Pulse Width

t_HA

t_SA

t_PWE

t_SD

Data Set-up to Write End

Data Hold from Write End

WE LOW to High Z^[7]

t_HD

t_HZWE

t_LZWE

WE HIGH to Low Z

Notes:

6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

I_OL/I_OHand 30-pF load capacitance.

7. t_HZOE,t_HZCE, and t_HZWEare specified with C_L= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.

8. At any given temperature and voltage condition, t_HZCEis less than t_LZCE1and t_LZCE2for any given device.

9. The internal write time of the memory is defined by the overlap of CE₁LOW, CE₂HIGH, and WE LOW. All 3 signals must be active to initiate a write and either

signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

Document #: 38-05043 Rev. *A

Page 4 of 11

CY7C185

Switching Waveforms

Read Cycle No.1^[10,11]

ADDRESS

OHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Read Cycle No.2^[12,13]

ACE

OOEE

HZOE

DOE

HZCE

LZOE

HIGH

IMPEDANCE

HIGH IMPEDANCE

DATA OUT

DATA VALID

LZCE

ICC

ISB

SUPPLY

CURRENT

50%

[11,13]

Write Cycle No. 1 (WE Controlled)

ADDRESS

SCEI

SCE2

PWE

DATA VALID

NOTE 14

DATA I/O

HZOE

10. Device is continuously selected. OE, CE₁= V_IL. CE₂= V_IH

11. WE is HIGH for read cycle.

12. Data I/O is High Z if OE = V_IH, CE₁= V_IH, WE = V_IL, or CE₂=V_IL

13. The internal write time of the memory is defined by the overlap of CE₁LOW, CE₂HIGH and WE LOW. CE₁and WE must be LOW and CE₂must be HIGH

to initiate write. A write can be terminated by CE₁or WE going HIGH or CE₂going LOW. The data input set-up and hold timing should be referenced to the

rising edge of the signal that terminates the write.

14. During this period, the I/Os are in the output state and input signals should not be applied.

Document #: 38-05043 Rev. *A

Page 5 of 11

CY7C185

Switching Waveforms (continued)

rite Cycle No. 2 (CE Controlled)^[13,14,15]

ADDRESS

SCE1

SCE2

DATA VALID

DATA I/O

Write Cycle No. 3 (WE Controlled, OE LOW)^{[13,14,15,16]}

ADDRESS

SCE1

SCE2

DATA I/O

DATA VALID

NOTE 14

LZWE

HZWE

Notes:

15. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t_HZWEand t_SD

16. If CE₁goes HIGH or CE₂goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.

Document #: 38-05043 Rev. *A

Page 6 of 11

CY7C185

Typical DC and AC Characteristics

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

NORMALIZED SUPPLY CURRENT

vs. SUPPLY VOLTAGE

120

100

1.4

1.2

1.0

1.2

1.0

0.8

0.6

0.4

=5.0V

=25°C

0.6

0.4

=5.0V

0.2

0.0

0.2

0.0

–55

125

0.0

1.0

2.0

3.0

4.0

4.5

5.0

5.5

6.0

AMBIENT TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIME

vs. AMBIENT TEMPERATURE

OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE

NORMALIZED ACCESS TIME

vs. SUPPLY VOLTAGE

140

120

1.6

1.4

1.3

1.2

100

=5.0V

1.2

1.0

T =25°C

1.1

1.0

T =25°C

=5.0V

0.8

0.9

0.8

0.6

–55

0.0

1.0

2.0

3.0

4.0

125

4.0

4.5

5.0

5.5

6.0

OUTPUT VOLTAGE (V)

SUPPLY VOLTAGE (V)

AMBIENT TEMPERATURE (°C)

TYPICAL POWER-ON CURRENT

vs. SUPPLY VOLTAGE

TYPICAL ACCESS TIME CHANGE

vs. OUTPUT LOADING

NORMALIZED I vs. CYCLE TIME

3.0

2.5

2.0

1.5

30.0

25.0

20.0

15.0

1.25

1.00

0.75

0.50

=5.0V

T =25°C

=0.5V

1.0

0.5

0.0

10.0

5.0

=4.5V

T =25°C

0.0

1.0

2.0

3.0

4.0

5.0

200 400

600 800 1000

SUPPLY VOLTAGE (V)

CAPACITANCE (pF)

CYCLE FREQUENCY (MHz)

Document #: 38-05043 Rev. *A

Page 7 of 11

CY7C185

Truth Table

CE₁

CE₂

Input/Output

Mode

Deselect/Power-Down

High Z

Deselect/Power-Down

Data Out

Data In

High Z

Read

Write

Deselect

Address Designators

Address

Name

Address

Function

Number

A10

A11

A12

Ordering Information

Speed

(ns)

Package

Name

Operating

Range

Ordering Code

Package Type

CY7C185-15PC

CY7C185-15SC

CY7C185-15VC

CY7C185-15VI

CY7C185-20PC

CY7C185-20SC

CY7C185-20VC

CY7C185-20VI

CY7C185-25PC

CY7C185-25SC

CY7C185-25VC

CY7C185-25VI

CY7C185-35PC

CY7C185-35SC

CY7C185-35VC

CY7C185-35VI

P21

S21

V21

P21

S21

V21

P21

S21

V21

P21

S21

V21

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOIC

28-Lead Molded SOJ

Commercial

28-Lead Molded SOJ

Industrial

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOIC

28-Lead Molded SOJ

Commercial

28-Lead Molded SOJ

Industrial

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOIC

28-Lead Molded SOJ

Commercial

28-Lead Molded SOJ

Industrial

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOIC

28-Lead Molded SOJ

Commercial

28-Lead Molded SOJ

Industrial

Document #: 38-05043 Rev. *A

Page 8 of 11

CY7C185

Package Diagrams

28-Lead (300-Mil) Molded DIP P21

51-85014-*B

28-Lead (300-Mil) Molded SOIC S21

51-85026-*A

Document #: 38-05043 Rev. *A

Page 9 of 11

CY7C185

Package Diagrams (continued)

28-Lead (300-Mil) Molded SOJ V21

51-85031-*B

All product and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05043 Rev. *A

Page 10 of 11

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C185

Document History Page

Document Title: CY7C185 8K x 8 Static RAM

Document Number: 38-05043

Issue

Orig. of

Change

REV.

ECN NO. Date

Description of Change

107145

116470

09/10/01

09/16/02

SZV

CEA

Change from Spec number: 38-00037 to 38-05043

Add applications foot note to data sheet.

Document #: 38-05043 Rev. *A

Page 11 of 11

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