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产品型号CY7C53120E4-40SXI的概述

CY7C53120E4-40SXI概述 CY7C53120E4-40SXI是一款由赛普拉斯半导体公司（Cypress Semiconductor）生产的高性能FPGA（现场可编程门阵列）芯片。这种芯片广泛应用于各种数字系统和应用中，如通信、汽车电子、工业控制和嵌入式系统。CY7C53120E4-40SXI的特性使其可以在可靠性、灵活性和可扩展性方面表现出色，从而满足各种复杂的设计要求。详细参数 CY7C53120E4-40SXI的主要技术参数如下： - 工作电压：3.3V ±10% - 输入电压范围：0V至5.5V，适应多种逻辑水平 - 门数：内置100K逻辑门，提供可编程的逻辑单元。 - 引脚数量：144引脚LQFP封装 - 工作频率：支持高达40MHz的操作频率 - 存储类型：内部EEPROM，提供非易失性存储功能 - 编程接口：支持JTAG和SPI编程 - 数据传输速率：支持...

产品型号CY7C53120E4-40SXI的Datasheet PDF文件预览

CY7C53150

CY7C53120

Neuron^®Chip Network Processor

Features

• Three 8-bit pipelined processors for concurrent processing

of application code and network traffic

• 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM

containing LonTalk^®network protocol firmware

• 11-pin IO port programmable in 34 modes for fast appli-

cation program development

• Maximum input clock operation of 20 MHz (CY7C53150),

10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a

–40°C to 85°C^[2]temperature range

• Two 16-bit timer/counters for measuring and generating IO

device waveforms

• 64-pin TQFP package (CY7C53150)

• 5-pin communication port that supports direct connect and

network transceiver interfaces

• 32-pin SOIC or 44-pin TQFP package (CY7C53120)

Functional Description

• Programmable pull ups on IO4–IO7 and 20 mA sink current

on IO0–IO3

The CY7C531x0 Neuron^®chip implements a node for

LonWorks^®distributed intelligent control networks. It incorpo-

rates, on a single chip, the necessary communication and

control functions, both in hardware and firmware, that facilitate

the design of a LonWorks node.

• Unique48-bitIDnumberineverydevicetofacilitatenetwork

installation and management

• Low operating current; sleep mode operation for reduced

current consumption^[1]

• 0.35 μm Flash process technology

• 5.0V operation

The CY7C531x0 contains a very flexible 5-pin communication

port that can be configured to interface with a wide variety of

media transceivers at a wide range of data rates. The most

common transceiver types are twisted-pair, powerline, RF, IR,

fiber-optics, and coaxial.

• On-chip LVD circuit to prevent nonvolatile memory

corruption during voltage drops

• 2,048 bytes of SRAM for buffering network data, system,

and application data storage

The CY7C531x0 is manufactured using state of the art

0.35-μm Flash technology, providing to designers the most

cost-effective Neuron chip solution.

• 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2),

4096 bytes (CY7C53120E4) of Flash memory with on-chip

charge pump for flexible storage of configuration data and

application code

Services at every layer of the OSI networking reference model

are implemented in the LonTalk firmware based protocol

stored in 10-KB ROM (CY7C53120E2), 12-KB ROM

(CY7C53120E4), or off-chip memory (CY7C53150). The

• Addresses up to 58 KB of external memory (CY7C53150)

Logic Block Diagram

CP4

CP0

Media Access

Control Processor

Communications

Port

IO10

IO0

Network

Internal

IO Block

Processor

Data Bus

(0:7)

Application

Processor

2 Timer/

Counters

Internal

Address Bus

(0:15)

2 KB RAM

CLK1

Oscillator,

Clock, and

Control

CLK2

SERVICE

RESET

Flash

External

Address/Data Bus

(CY7C53150)

ROM

(CY7C53120)

Notes

1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. For details, refer to Cypress’s Neuron

Metastability Description application note.

2. Maximum Junction Temperature is 105°C. T

= T

+ V•I•θ_JA. 32-pin SOIC θ_JA= 51C/W. 44-pin TQFP θ_JA= 43C/W. 64-pin TQFP θ_JA= 44C/W.

Junction

Ambient

Cypress Semiconductor Corporation

Document #: 38-10001 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 14, 2007

[+] Feedback

CY7C53150

CY7C53120

firmware also contains 34 preprogrammed IO drivers, greatly

simplifying application programming. The application program

is stored in the Flash memory (CY7C53120) and/or off-chip

memory (CY7C53150), and may be updated by downloading

over the network.

cation programs can take advantage of this external memory

capability.

The CY7C53150 Neuron chip is an exact replacement for the

Motorola MC143150Bx and Toshiba TMPN3150B1 devices.

The CY7C53120E2 Neuron chip is an exact replacement for

the Motorola MC143120E2 device since it contains the same

firmware in ROM.

The CY7C53150 incorporates an external memory interface

that can address up to 64 KB with 6 KB of the address space

mapped internally. LonWorks nodes that require large appli-

Pin Configurations

CY7C53150

64-lead Thin Quad Flat Pack

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

NC^[4]

A14

CP4

CP3

A13

A12

A11

CP2

CP1

CP0

NC^[4]

V_DD

A10

V_SS

CLK1

CY7C53150-20AI

CLK2

V_DD

V_SS

V_DD

V_SS

NC^[4]

SERVICE

2 3 4 5 6 7 8 9 10 11 1213 14 15 16

Pin 1

Indicator ^[3]

Notes

3. The smaller dimple at the bottom left of the marking indicates pin 1.

4. No Connect (NC) — Must not be used. (These pins may be used for internal testing.)

Document #: 38-10001 Rev. *E

Page 2 of 14

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CY7C53150

CY7C53120

Pin Configurations (continued)

44-lead QFP

32-lead SOIC

RESET

V_DD

V_SS

IO5

NC^[4]

IO6

IO4

CP1

CP0

V_DD

IO3

IO6

IO5

IO2

IO7

IO1

IO8

V_SS

IO0

IO9

CP2

NC^[4]

V_SS

V_DD

CY7C53120Ex-yyAI

SERVICE

V_SS

V_DD

IO10

V_SS

CP4

CP3

CP1

CP0

V_DD

CP2

NC^[4]

RESET

V_DD

V_pp

CLK1

CLK2

V_SS

V_DD

IO4

V_DD

V_SS

IO3

NC^[4]

CLK2

CLK1

V_SS

PIN 1

INDICATOR

Document #: 38-10001 Rev. *E

Page 3 of 14

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CY7C53150

CY7C53120

Pin Descriptions

CY7C53150

CY7C53120xx

Pin Name

Pin Function

TQFP-64 Pin No. SOIC-32 Pin No. TQFP-44 Pin No.

CLK1

Input

Oscillator connection or external clock

input.

CLK2

Output

Oscillator connection. Leave open when

external clock is input to CLK1. Maximum

of one external load.

RESET

SERVICE

IO0–IO3

IO (Built-In

Pull up)

Reset pin (active LOW). Note The

allowable external capacitance connected

to the RESET pin is 100–1000 pF.

IO (Built-In

Service pin (active LOW). Alternates

Configurable between input and output at a 76-Hz rate.

Pull up)

Large current-sink capacity (20 mA).

General IO port. The output of timer/

counter 1 may be routed to IO0. The output

of Timer/Counter 2 may be routed to IO1.

2, 3, 4, 5

7, 6, 5, 4

4, 3, 2, 43

IO4–IO7

IO (Built-In

General IO port. The input to

10, 11, 12, 13

14, 15, 16

3, 30, 29, 28

42, 36, 35, 32

Configurable Timer/Counter 1 may be derived from one

Pull ups)

of IO4–IO7. The input to Timer/Counter 2

may be derived from IO4.

IO8–IO10

D0–D7

R/W

General IO port. May be used for serial

communication under firmware control.

27, 26, 24

N/A

31, 30, 27

N/A

Bidirectional memory data bus.

43, 42, 38, 37,

36, 35, 34, 33

Output

Read/write control output for external

memory.

N/A

Enable clock control output for external

memory.

N/A

A0–A15

Memory address output port.

64, 63, 62, 61, 60,

59, 58, 57, 56, 55,

54, 53, 52, 51, 50,

N/A

V_DD

V_SS

Vpp

Input

Power input (5V nom). All V_DDpins must

be connected together externally.

7, 20, 22, 26,

40, 41, 44

2, 11, 12,

18, 25, 32

9, 10, 19,

29, 38, 41

Power input (0V, GND). All V_SSpins must 8,19, 21, 25, 39 9, 13, 16, 23, 31 7,13, 16, 26, 37

be connected together externally.

In-circuittestmodecontrol. IfVppishigh

when RESET is asserted, the IO, address

and data buses become Hi-Z.

CP0–CP4 Communication Bidirectional port supporting communi- 28, 29, 30, 31, 32 19, 20, 17, 21, 22 20, 21, 18, 24, 25

Network

Interface

cations in three modes.

—

No connect. Must not be connected on the 1, 18, 27, 48, 49

user’s PC board, since they may be

connected internal to the chip.

N/A

1, 6, 11, 12, 17,

22, 23, 28, 33, 34,

39, 44

Document #: 38-10001 Rev. *E

Page 4 of 14

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CY7C53150

CY7C53120

Memory Usage

40 MHz 3120 Operation

All Neuron chips require system firmware to be present when

they are powered up. In the case of the CY7C53120 family,

this firmware is preprogrammed in the factory in an on-chip

ROM. In the case of the CY7C53150, the system firmware

must be present in the first 16 KB of an off-chip nonvolatile

memory such as Flash, EPROM, EEPROM, or NVRAM.

These devices must be programmed in a device programmer

before board assembly. Because the system firmware imple-

ments the network protocol, it cannot itself be downloaded

over the network.

The CY7C53120E4-40 device was designed to run at

frequencies up to 40 MHz using an external clock oscillator. It

is important to note that external oscillators may typically take

on the order of 5 ms to stabilize after power-up. The Neuron

chip must be held in reset until the CLK1 input is stable. With

some oscillators, this may require the use of a reset-stretching

Low-Voltage Detection chip/circuit. Check the oscillator

vendor’s specification for more information about start-up

stabilization times.

Low-Voltage Inhibit Operation

For the CY7C53120 family, the user application program is

stored in on-chip Flash memory. It may be programmed using

a device programmer before board assembly, or may be

downloaded and updated over the LonTalk network from an

external network management tool.

The on-chip Low-voltage Inhibit circuit trips the Neuron chip

whenever the V_DDinput is less than 4.1 ± 0.3V. This feature

prevents the corruption of nonvolatile memory during voltage

drops.

For the CY7C53150, the user application program is stored in

on-chip Flash Memory and also in off-chip memory. The user

program may initially be programmed into the off-chip memory

device using a device programmer.

Communications Port

The Neuron chip includes a versatile 5-pin communications

port that can be configured in three different ways. In

Single-Ended Mode, pin CP0 is used for receiving serial data,

pin CP1 for transmitting serial data, and pin CP2 enables an

external transceiver. Data is communicated using Differential

Manchester encoding.

Flash Memory Retention and Endurance

Data and code stored in Flash Memory is guaranteed to be

retained for at least 10 years for programming temperature

range of –25°C to 85°C.

In Special Purpose Mode, pin CP0 is used for receiving serial

data, pin CP1 for transmitting serial data, pin CP2 transmits a

bit clock, and pin CP4 transmits a frame clock for use by an

external intelligent transceiver. In this mode, the external

transceiver is responsible for encoding and decoding the data

stream.

The Flash Memory can typically be written 100,000 times

without any data loss.^[5]An erase/write cycle takes 20 ms. The

system firmware extends the effective endurance of Flash

memory in two ways. If the data being written to a byte of Flash

memory is the same as the data already present in that byte,

the firmware does not perform the physical write. So for

example, an application that sets its own address in Flash

memory after every reset does not use up any write cycles if

the address has not changed. In addition, system firmware

version 13.1 or higher is able to aggregate writes to eight

In Differential Mode, pins CP0 and CP1 form a differential

receiver with built-in programmable hysteresis and low pass

filtering. Pins CP2 and CP3 form a differential driver. Serial

data is communicated using Differential Manchester encoding.

The following tables describe the communications port when

used in Differential Mode.

successive address locations into

a single write for

CY7C53120E4 devices. For example, if 4 KB of code is

downloaded over the network, the firmware would execute

only 512 writes rather than 4,096.

Note

5. For detailed information about data retention after 100K cycles, see the Cypress qualification report.

Document #: 38-10001 Rev. *E

Page 5 of 14

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CY7C53150

CY7C53120

Programmable Hysteresis Values

(Expressed as differential peak-to-peak voltages in terms of V_DD

Receiver^[8](End-to-End) Absolute Asymmetry

(Worst case across hysteresis)

)

Hysteresis^[6]

V_hysMin.

0.019 V_DD

0.040 V_DD

0.061 V_DD

0.081 V_DD

0.101 V_DD

0.121 V_DD

0.142 V_DD

0.162 V_DD

V_hysTyp.

0.027 V_DD

0.054 V_DD

0.081 V_DD

0.108 V_DD

0.135 V_DD

0.162 V_DD

0.189 V_DD

0.216 V_DD

V_hysMax.

0.035 V_DD

0.068 V_DD

0.101 V_DD

0.135 V_DD

0.169 V_DD

0.203 V_DD

0.236 V_DD

0.270 V_DD

Filter (F)

Max (⎢t_PLH– t_PHL⎜)

Unit

150

250

400

Figure 1. Receiver Input Waveform

⎮CP0 – CP1⎮ ≥

V_hys+ 200 mV

Programmable Glitch Filter Values^[7]

(Receiver (end-to-end) filter values expressed as transient

pulse suppression times)

CP0

V_DD/2

CP1

≤ 3 ns

Filter (F)

Min.

Typ.

Max.

140

Unit

Differential Receiver (End-to-End) Absolute Symmetry^{[9, 10]}

120

240

480

410

800

1500

700

Filter (F)

Hysteresis (H) Max (⎢t_PLH– t_PHL⎜) Unit

24 ns

1350

2600

Notes

6. Hysteresis values are on the condition that the input signal swing is 200 mV greater than the programmed value.

7. Must be disabled if data rate is 1.25 Mbps or greater.

8. Receiver input, V = V

– V

, at least 200 mV greater than hysteresis levels. See Figure 1.

CP0

CP1

9. CPO and CP1 inputs each 0.60 Vp – p, 1.25 MHz sine wave 180° out of phase with each other as shown in Figure 8. V = 5.00 V ± 5%.

10. t

: Time from input switching states from low to high to output switching states. t

: Time from input switching states from high to low to output switching states.

PLH

PHL

Document #: 38-10001 Rev. *E

Page 6 of 14

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CY7C53150

CY7C53120

Electrical Characteristics (V_DD= 4.5V–5.5V)

Parameter

Description

Min.

Typ.

Max.

Unit

V_IL

Input Low Voltage

IO0–IO10, CP0, CP3, CP4, SERVICE, D0-D7, RESET

CP0, CP1 (Differential)

—

0.8

Programmable

V_IH

Input High Voltage

IO0–IO10, CP0, CP3, CP4, SERVICE, D0-D7, RESET

CP0, CP1 (Differential)

2.0

—

Programmable

V_OL

Low-Level Output Voltage

_out< 20 μA

—

0.1

0.4

0.8

0.4

1.0

0.4

Standard Outputs (I_OL= 1.4 mA)^[11]

High Sink (IO0–IO3), SERVICE, RESET (I_OL= 20 mA)

High Sink (IO0–IO3), SERVICE, RESET (I_OL= 10 mA)

Maximum Sink (CP2, CP3) (I_OL= 40 mA)

Maximum Sink (CP2, CP3) (I_OL= 15 mA)

V_OH

High-Level Output Voltage

_out< 20 μA

V_DD– 0.1

V_DD– 0.4

—

Standard Outputs (I_OH= –1.4 mA)^[11]

High Sink (IO0 – IO3), SERVICE (I_OH= –1.4 mA)

Maximum Source (CP2, CP3) (I_OH= –40 mA)

Maximum Source (CP2, CP3) (I_OH= –15 mA)

_DD– 0.4

_DD– 1.0

V_DD– 0.4

V_hys

I_in

Hysteresis (Excluding CLK1)

175

—

μA

[12]

Input Current (Excluding Pull Ups) (V_SSto V_DD

Pull Up Source Current (V_out= 0 V, Output = High-Z)^[12]

)

±10

260

I_pu

μA

I_DD

Operating Mode Supply Current^[13]40-MHz Clock^[14]

20-MHz Clock

10-MHz Clock

5-MHz Clock

2.5-MHz Clock

—

1.25-MHz Clock

0.625-MHz Clock^[14]

I_DDsleep

Sleep Mode Supply Current^{[1, 13]}

—

100

μA

LVI Trip Point (V_DD

)

Part Number

Min.

Typ.

Max.

Unit

CY7C53120E2, CY7C53120E4, and CY7C53150

3.8

4.1

4.4

Notes

11. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < 15 pF load.) For CY7C53150, standard outputs

also include A0–A15, D0–D7, E, and R/W.

12. IO4–IO7 and SERVICE have configurable pull ups. RESET has a permanent pull up.

13. Supply current measurement conditions: V = 5V, all outputs under no-load conditions, all inputs < 0.2V or > (V – 0.2V), configurable pull ups off, crystal

oscillator clock input, differential receiver disabled. The differential receiver adds approximately 200 µA typical and 600 µA maximum when enabled. It is enabled

on either of the following conditions:

• Neuron chip in Operating mode and Comm Port in Differential mode.

• Neuron chip in Sleep mode and Comm Port in Differential mode and Comm Port Wake-up not masked.

14. Supported through an external oscillator only.

Document #: 38-10001 Rev. *E

Page 7 of 14

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CY7C53150

CY7C53120

External Memory Interface Timing — CY7C53150, V_DD± 10% (V_DD= 4.5V to 5.5 V, T_A= –40°C to+ 85°C ^[2]

)

Parameter

t_cyc

Description

Memory Cycle Time (System Clock Period)^[15]

Pulse Width, E High^[16]

Min.

Max.

Unit

100

3200

PW_EH

PW_EL

t_AD

t_cyc/2 – 5

t_cyc/2 + 5

Pulse Width, E Low^[16]

t_cyc/2 – 5

t_cyc/2 + 5

Delay, E High to Address Valid^[20]

Address Hold Time After E High^[20]

Delay, E High to R/W Valid Read^[20]

R/W Hold Time Read After E High

Delay, E High to R/W Valid Write

R/W Hold Time Write After E High

Read Data Setup Time to E High

Data Hold Time Read After E High

Data Hold Time Write After E High^{[17, 18]}

Delay, E Low to Data Valid

—

t_AH

—

t_RD

t_RH

—

t_WR

—

t_WH

—

t_DSR

t_DHR

t_DHW

t_DDW

t_DHZ

t_DDZ

t_acc

—

Data Three State Hold Time After E Low^[19]

Delay, E High to Data Three-State^[18]

—

External Memory Access Time (t_acc= t_cyc– t_AD– t_DSR) at

20-MHz input clock

—

Differential Transceiver Electrical Characteristics

Characteristic

Receiver Common Mode Voltage Range to maintain hysteresis^[21]

Receiver Common Mode Range to operate with unspecified hysteresis

Input Offset Voltage

Min.

Max.

V_DD– 2.2

V_DD– 1.75

0.05V_hys+ 35

230 ns

—

Unit

1.2

0.9

–0.05V_hys– 35

MΩ

μs

Propagation Delay (F = 0, V_ID= V_hys/2 + 200 mV)

Input Resistance

—

Wake-up Time

Differential Output Impedance for CP2 and CP3^[22]

—

Figure 2. Signal Loading for Timing Specifications Unless Otherwise Specified

TEST SIGNAL

C_L= 20 pF for E

C_L= 30 pF for A0–A15, D0–D7, and R/W

C_L

C_L= 50 pF for all other signals

Figure 3. Test Point Levels for E Pulse Width Measurements

PW_EH

2.0V

PW_EL

2.0V

0.8V

Notes

15. t = 2(1/f), where f is the input clock (CLK1) frequency (20, 10, 5, 2.5, 1.25, or 0.625 MHz).

cyc

16. Refer to Figure 3 for detailed measurement information.

17. The data hold parameter, t

, is measured to the disable levels shown in Figure 5, rather than to the traditional data invalid levels.

DHW

18. Refer to Figure 6 and Figure 5 for detailed measurement information.

19. The three-state condition is when the device is not actively driving data. Refer to Figure 2 and Figure 5 for detailed measurement information.

20. To meet the timing above for 20-MHz operation, the loading on A0–A15, D0–D7, and R/W is 30 pF. Loading on E is 20 pF.

21. Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs.

22. Z = |V[CP2]-V[CP3] |/40 mA for 4.75 < V < 5.25V.

Document #: 38-10001 Rev. *E

Page 8 of 14

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CY7C53150

CY7C53120

Figure 4. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified

DRIVE TO 2.4V

2.0V

0.8V

DRIVE TO 0.4V

2.0V

0.8V

A — Signal valid-to-signal valid specification (maximum or minimum)

B — Signal valid-to-signal invalid specification (maximum or minimum)

Figure 5. Test Point Levels for Driven-to-Three-State Time Measurements

V_OH– 0.5 V

V_OL+ 0.5 V

V_OH– Measured high output drive level

_OL– Measured low output drive level

Figure 6. Signal Loading for Driven-to-Three-State Time Measurements

V_DD/2

I_LOAD= 1.4 mA

TEST SIGNAL

C_L= 30 pF

Figure 7. External Memory Interface Timing Diagram

t_cyc

PW_EH

PW_EL

20 pF Load

t_AD

Address

(A0 – A15)

30 pF Load

Address

t_AH

t_WR

t_RD

R/W

30 pF Load

t_RH

t_WH

t_DSR

Data In

t_DHR

t_DSR

Data (In)

(D0 – D7)

Data In

t_DDW

t_DHR

t_DDZ

t_DHZ

t_DHW

Data Out

t_DDW

t_DHW

Data Out

Data (Out)

t_DHZ

(D0 – D7)

30 pF Load

Memory READ

Memory WRITE

Document #: 38-10001 Rev. *E

Page 9 of 14

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CY7C53150

CY7C53120

Figure 8. Differential Receiver Input Hysteresis Voltage Measurement Waveforms

Voltage

V(CP0)

Vcm

V(CP1)

V(CP0)-V(CP1)

Tim e

Vtrip+

Vtrip-

- 1

Neuron Chip's

Internal

Com parator

Com m on-M ode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2

Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]

Ordering Information^[23]

Max. Input

Clock

Flash

(KB)

ROM

(KB)

Firmware

Version

Package

Name

Part Number

Package Type

(MHz)

CY7C53150-20AXI

CY7C53150-20AXIT

0.5

N/A

20^[25]

A64SA 64-lead Thin Plastic Quad Flat Pack

Tape and Reel

CY7C53120E2-10SXI^[24]

CY7C53120E4-40SXI^[26]

CY7C53120E4-40SXIT

S32.45 32-lead (450 mil) Molded SOIC

S32.45 32-lead (450 mil) Molded SOIC Tape

and Reel

CY7C53120E2-10AXI^[24]

CY7C53120E4-40AXI^[26]

A44

44-lead Thin Plastic Quad Flat Pack

Notes

23. All parts contain 2 KB of SRAM.

24. CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 firmware.

25. CY7C53150 may be used with 20-MHz input clock only if the firmware in external memory is version 13 or later.

26. CY7C53120E4 requires upgraded LonBuilder® and NodeBuilder® software.

Document #: 38-10001 Rev. *E

Page 10 of 14

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CY7C53150

CY7C53120

Package Diagrams

Figure 9. 44-Lead Thin Plastic Quad Flat Pack A44

12.00 0.2ꢀ SQ

10.00 0.10 SQ

0° MIN.

0.37 0.0ꢀ

R. 0.08 MIN.

0.20 MAX.

STAND-OFF

0.0ꢀ MIN.

0.1ꢀ MAX.

0.2ꢀ

GAUGE PLANE

R. 0.08 MIN.

0.20 MIN.

0-7°

0.20 MIN.

0.60 0.1ꢀ

1.00 REF.

0.80

B.S.C.

DETAIL

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.2ꢀ mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

12° 1°

(8X)

SEATING PLANE

1.60 MAX.

1.40 0.0ꢀ

3. DIMENSIONS IN MILLIMETERS

0.10

0.20 MAX.

51-85064-*C

SEE DETAIL

Document #: 38-10001 Rev. *E

Page 11 of 14

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CY7C53150

CY7C53120

Package Diagrams (continued)

Figure 10. 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A64SA

16.00 0.2ꢀ SQ

14.00 0.0ꢀ SQ

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.2ꢀ mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0.3ꢀ 0.0ꢀ

0.80 TYP.

0° MIN.

R 0.08 MIN.

0.20 MAX.

STAND-OFF

0.0ꢀ MIN.

0.1ꢀ MAX.

0.2ꢀ

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

SEATING PLANE

12° 1°

(8X)

0°-7°

1.40 0.0ꢀ

1.60 MAX.

0.20 MIN.

0.60 0.1ꢀ

1.00 REF.

0.10

0.20 MAX

DETAIL

51-85046-*C

SEE DETAIL

Document #: 38-10001 Rev. *E

Page 12 of 14

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CY7C53150

CY7C53120

Package Diagrams (continued)

Figure 11. 32-Lead (450-Mil) SOIC S32.45

32 LD (4ꢀ0 Mil) SOIC

0.ꢀ46[13.868]

0.ꢀ66[14.376]

0.440[11.176]

0.4ꢀ0[11.430]

MIN.

DIMENSIONS IN INCHES[MM]

MAX.

PACKAGE WEIGHT 1.42gms

PART #

S32.4ꢀ STANDARD PKG.

SZ32.4ꢀ LEAD FREE PKG.

0.793[20.142]

0.817[20.7ꢀ1]

0.006[0.1ꢀ2]

0.012[0.304]

0.101[2.ꢀ6ꢀ]

0.111[2.819]

0.118[2.997]

MAX.

0.004[0.102]

0.047[1.193]

0.063[1.600]

0.004[0.102]

0.0ꢀ0[1.270]

0.023[0.ꢀ84]

0.039[0.990]

MIN.

BSC.

0.014[0.3ꢀꢀ]

0.020[0.ꢀ08]

SEATING PLANE

51-85081-*B

LonWorks, LonTalk, LonBuilder, NodeBuilder, and Neuron are registered trademarks of Echelon Corporation. All product and

company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-10001 Rev. *E

Page 13 of 14

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C53150

CY7C53120

Document History Page

Document Title: CY7C53150/CY7C53120 Neuron^®Chip Network Processor

Document Number: 38-10001

Orig. of

Change

REV.

ECN NO. Issue Date

Description of Change

111472

111990

11/28/01

02/06/02

DSG

Change from Spec number: 38-00891 to 38-10001

Changed the max. cur rent values

CFB

Specified the Flash endurance of “100K typical” with reference to qual report

Fixed some incorrect footnotes and figure numbering

114465

04/24/02

KBO

Added Sleep Metastability footnote

Added Junction Temperature footnote

Added maximum sleep current footnote

Changed “EEPROM” references to “Flash Memory”

115269

124450

04/26/02

03/25/03

KBO

Repositioned Note 3

Removed Note 2 regarding data retention

Removed Note 16 regarding max sleep current

Changed the system image firmware version from V12 to V13.1

837840

3/14/07

BOO

Implemented new template. Modified the Ordering Information table; added an

“X” to indicate the part numbers are Pb-free; two tape-and-reel options are

available now.

Document #: 38-10001 Rev. *E

Page 14 of 14

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CY7C53120E4-40SXI产品参数

型号:	CY7C53120E4-40SXI
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP, SOP32,.55
针数：	32
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.31.00.01
Factory Lead Time：	1 week
风险等级：	1.55
地址总线宽度：	16
边界扫描：	NO
最大时钟频率：	40 MHz
数据编码/解码方法：	DIFF BIPHASE-LEVEL
外部数据总线宽度：	8
JESD-30 代码：	R-PDSO-G32
JESD-609代码：	e4
长度：	20.4465 mm
低功率模式：	NO
湿度敏感等级：	3
串行 I/O 数：	5
端子数量：	32
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP32,.55
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	2.997 mm
子类别：	Serial IO/Communication Controllers
最大压摆率：	55 mA
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	11.303 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：	1

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