CYUSB3065-BZXC全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

CYUSB306X

EZ-USB^®CX3: MIPI CSI-2 to

SuperSpeed USB Bridge Controller

EZ-USB^®CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller

Features

Applications

■ Universal Serial Bus (USB) integration

❐ USB 3.0 and USB 2.0 peripherals, compliant with USB 3.0

specification 1.0

❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0

❐ Thirty-two physical endpoints

■ Digital video cameras

■ Digital still cameras

■ Webcams

■ Scanners

■ MIPI CSI-2 RX interface

■ Video conference systems

❐ MIPI CSI-2 compliant (Version 1.01, Revision 0.04 – 2^ndApril

2009)

■ Gesture-based control

■ Surveillance cameras

■ Medical imaging devices

■ Video IP phones

❐ Supports up to four data lanes (CYUSB3065 supports up to

four lanes; CYUSB3064 supports up to two lanes)

❐ Each lane supports up to 1 Gbps (CYUSB3065 supports up

to four lanes; CYUSB3064 supports up to two lanes)

❐ CCI interface for image sensor configuration

■ USB microscopes

■ Supports the following video data formats:

❐ User-defined 8-bit

❐ RAW8/10/12/14

■ Industrial cameras

❐ YUV422 (CCIR/ITU 8/10bit), YUV444

❐ RGB888/666/565

■ Fully accessible 32-bit CPU

❐ ARM926EJ-S core with 200-MHz operation

❐ 512-KB or 256-KB embedded SRAM

■ Additional connectivity to the following peripherals:

❐ I²C master controller at 1 MHz

❐ I²S master (transmitter only) at sampling frequencies of

32 kHz, 44.1 kHz, and 48 kHz

❐ UART support of up to 4 Mbps

❐ SPI master at 33 MHz

■ Twelve GPIOs

■ Ultra-low-power in core power-down mode

■ Independent power domains for core and I/O

❐ Core operation at 1.2 V

❐ I²S, UART, and SPI operation at 1.8 to 3.3 V

❐ I²C, I/O operation at 1.8 to 3.3 V

■ 10 × 10 mm, 0.8-mm pitch Pb-free ball grid array (BGA)

package

■ EZ-USB^®software development kit (SDK) for easy code

development

Cypress Semiconductor Corporation

Document Number: 001-87516 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 22, 2017

CYUSB306X

Logic Block Diagram

JTAG

CPU

ARM926EJ-S

SSRX-

SSRX+

CP / CM

SS

Peripheral

SSTX-

D0P / D0M

USB

Port

32

EPs

MIPI CSI-2 RX

interface

D1P / D1M

SSTX+

HS/FS

Peripheral

D2P / D2M

D3P / D3M

D+

D-

MCLK

XRST

XSHUTDOWN

Program

RAM

RESET#

CLKIN

CLKIN_32

REFCLK

I2S

SPI

UART

I2C

Document Number: 001-87516 Rev. *L

Page 2 of 37

CYUSB306X

More Information

Cypress provides a wealth of data at www.cypress.com to help

you to select the right device for your design, and to help you to

quickly and effectively integrate the device into your design. For

a comprehensive list of resources refer to the cypress web page

for CX3 at www.cypress.com/CX3.

■ Knowledge Base Articles:

❐ CX3 Firmware: Frequently Asked Questions - KBA91297

❐ CX3 Hardware: Frequently Asked Questions - KBA91295

❐ CX3 Application Software / USB Driver: Frequently Asked

Questions - KBA91298

❐ Knowledge Base - Cypress Semiconductor Cage Code -

■ Overview: USB Portfolio, USB Roadmap

KBA89258

■ USB 3.0 Product Selectors: FX3, FX3S, CX3, GX3, HX3, West

Bridge Benicia

■ Development Kits:

❐ Ascella - Cypress® CX3™ THine® ISP 13MP reference de-

sign kit (RDK)

■ Application notes: Cypress offers a large number of USB appli-

cation notes covering a broad range of topics, from basic to

advanced level. Recommended application notes for getting

started with CX3 are:

❐ Denebola - USB 3.0 UVC Reference Design Kit (RDK)

■ Models:

❐ CX3 Device OrCad Schematic Symbol

❐ CYUSB306x - IBIS

❐ AN75705 - Getting Started with EZ-USB FX3

❐ AN90369 - How to Interface a MIPI CSI-2 Image Sensor With

EZ-USB® CX3

❐ AN75779-HowtoImplementanImageSensorInterfacewith

EZ-USB® FX3™ in a USB Video Class (UVC) Framework

❐ AN76405 - EZ-USB FX3 Boot Options

❐ AN70707 - EZ-USB FX3/FX3S Hardware Design Guidelines

and Schematic Checklist

❐ AN86947 - Optimizing USB 3.0 Throughput with EZ-USB

FX3

EZ-USB Software Development Kit

Cypress delivers the complete firmware stack for CX3, in order

to easily integrate SuperSpeed USB into any embedded MIPI

image sensor application. The Software Development Kit (FX3

SDK) comes with tools, drivers and application examples, which

help accelerate application development. The FX3 SDK Setup

includes CX3 APIs and example firmware for OmniVision

OV5640 and Aptina AS0260 image sensor interface. The eclipse

plugin for the FX3 SDK accelerates CX3 firmware development

for any other image sensor.

■ Code Examples:

❐ USB SuperSpeed

■ Technical Reference Manual (TRM):

❐ EZ-USB® CX3 Technical Reference Manual

Document Number: 001-87516 Rev. *L

Page 3 of 37

CYUSB306X

Contents

Functional Overview ........................................................5

Application Examples ..................................................5

USB Interface ....................................................................6

ReNumeration .............................................................6

VBUS Overvoltage Protection .....................................6

MIPI CSI-2 RX Interface ....................................................7

Additional Outputs .......................................................7

CPU ....................................................................................7

JTAG Interface ..................................................................7

Other Interfaces ................................................................7

UART Interface ............................................................7

I2C Interface ................................................................7

I2S Interface ................................................................8

SPI Interface ................................................................8

Boot Options .....................................................................8

Reset ..................................................................................8

Hard Reset ..................................................................8

Soft Reset ....................................................................8

Clocking ............................................................................9

32-kHz Watchdog Timer Clock Input ...........................9

Power ...............................................................................10

Power Modes ............................................................10

Configuration Options ...................................................13

Digital I/Os .......................................................................13

GPIOs ...............................................................................13

EMI ...................................................................................13

System-level ESD ...........................................................13

Pin Configuration ...........................................................14

Pin Description ...............................................................15

Absolute Maximum Ratings ..........................................17

Operating Conditions .....................................................17

DC Specifications ...........................................................17

MIPI D-PHY Electrical Characteristics ..........................18

AC Timing Parameters ...................................................19

MIPI Data to Clock Timing Reference .......................19

Reference Clock Specifications .................................19

MIPI CSI Signal Low Power AC Characteristics .......20

AC Specifications ......................................................20

Serial Peripherals Timing ..........................................21

Reset Sequence ..............................................................26

Ordering Information ......................................................27

Ordering Code Definitions .........................................27

Package Diagram ............................................................28

Acronyms ........................................................................29

Document Conventions .................................................29

Units of Measure .......................................................29

Errata ...............................................................................30

Part Numbers Affected ..............................................30

Qualification Status ...................................................30

Errata Summary ........................................................30

Document History Page .................................................34

Sales, Solutions, and Legal Information ......................37

Worldwide Sales and Design Support .......................37

Products ....................................................................37

PSoC®Solutions .......................................................37

Cypress Developer Community .................................37

Technical Support .....................................................37

Document Number: 001-87516 Rev. *L

Page 4 of 37

CYUSB306X

CX3 comes with application development tools. The software

development kit comes with application examples for acceler-

ating time-to-market.

Functional Overview

Cypress’s EZ-USB CX3 is the next-generation bridge controller

that can connect devices with the Mobile Industry Processor

Interface – Camera Serial Interface 2 (MIPI CSI-2) interface to

any USB 3.0 Host.

CX3 complies with the USB 3.0 v1.0 specification and is also

backward compatible with USB 2.0. It also complies with the

MIPI CSI-2 v1.01, revision 0.04 specification dated 2^ndApril

2009.

CX3 has a 4-lane CSI-2 receiver with up to 1 Gbps on each lane.

It supports video data formats such as RAW8/10/12/14, YUV422

(CCIR/ITU 8/10-bit), RGB888/666/565, and user-defined 8-bit.

Application Examples

In a typical application (see Figure 1), CX3 acts as the main

processor and connects to an image sensor, an audio device, or

camera control devices amongst others.

CX3 has integrated the USB 3.0 and USB 2.0 physical layers

(PHYs) along with a 32-bit ARM926EJ-S microprocessor for

powerful data processing and for building custom applications.

CX3 contains 512 KB of on-chip SRAM (see Ordering

Information on page 27) for code and data. EZ-USB CX3 also

provides interfaces to connect to serial peripherals such as

UART, SPI, I²C, and I²S.

Figure 1. EZ-USB CX3 Example Application

Clock

Power

6-40 MHz

19.2 MHz

subsystem

V_DD

REFCLK

CLKIN

MIPI CSI-2

RX

U

S

B

USB

Host

EZ-USB CX3

Image

sensor

I²C

I²S

SPI

Audio

output

Audio

input

Autofocus, Pan, Tilt, Zoom,

Shutter control, Lighting, etc.

Document Number: 001-87516 Rev. *L

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CYUSB306X

VBUS Overvoltage Protection

USB Interface

The maximum input voltage on CX3's VUSB pin is 6 V. A charger

can supply up to 9 V on VUSB. In this case, an external

overvoltage protection (OVP) device is required to protect CX3

from damage on VUSB. Figure 3 shows the system application

diagram with an OVP device connected on VUSB. Refer to DC

Specifications on page 17 for the operating range of VUSB.

CX3 complies with the following specifications and supports the

following features:

■ Supports USB peripheral functionality compliant with USB 3.0

Specification, Revision 1.0, and is also backward compatible

with the USB 2.0 Specification.

Note: The VBUS pin of the USB connector should be connected

to the VUSB pin of CX3.

■ As a peripheral, CX3 is capable of SuperSpeed, High-Speed,

and Full-Speed.

Figure 3. System Diagram with OVP Device For VUSB

■ Supports up to 16 IN and 16 OUT endpoints

■ Supports the USB 3.0 Streams feature

POWER SUBSYSTEM

■ As a USB peripheral, CX3 supports USB-attached storage

(UAS), USB Video Class (UVC), and Media Transfer Protocol

(MTP) USB peripheral classes. As a USB peripheral, all other

device classes are supported only in pass-through mode when

handled entirely by a host processor external to the device.

Figure 2. USB Interface Signals

EZ-USB CX3

VUSB

1

2

OVP device

SSRX-

SSRX+

SSTX-

SSTX+

D-

3

4

5

VUSB

SSRX-

SSRX+

SSTX-

SSTX+

D-

6

7

8

9

D+

GND

D+

ReNumeration

Because of CX3’s soft configuration, one chip can take on the

identities of multiple distinct USB devices.

When first plugged into USB, CX3 enumerates automatically

with the Cypress Vendor ID (0x04B4) and downloads the

firmware and USB descriptors over the USB interface. The

downloaded firmware executes an electrical disconnect and

connect. CX3 enumerates again, this time as a device defined

by the downloaded information. This patented two-step process,

called ReNumeration, happens instantly when the device is

plugged in.

Document Number: 001-87516 Rev. *L

Page 6 of 37

CYUSB306X

Examples of the CX3 firmware are available with the Cypress

EZ-USB CX3 Development Kit. Software APIs that can be ported

to an external processor are available with the Cypress EZ-USB

CX3 Software Development Kit.

MIPI CSI-2 RX Interface

The Mobile Industry Processor Interface (MIPI) association

defined the Camera Serial Interface 2 (CSI-2) standard to enable

image data to be sent on high-bandwidth serial lines.

JTAG Interface

CX3 implements a MIPI CSI-2 Receiver with the following

features:

CX3’s JTAG interface has a standard five-pin interface to

connect to a JTAG debugger in order to debug firmware through

the CPU-core's on-chip-debug circuitry.

1. It can receive clock and data in 1, 2, 3, or 4 lanes.

(CYUSB3065 part supports up to four lanes; CYUSB3064 part

supports up to two lanes)

Industry-standard debugging tools for the ARM926EJ-S core

can be used for the CX3 application development.

2. Up to 1 Gbps of data on each CSI lane is supported (total

maximum bandwidth should not exceed 2.4 Gbps).

3. Video formats such as RAW8/10/12/14, YUV422 (CCIR/ITU

8/10-bit), RGB888/666/565, and User-Defined 8-bit are

supported

Other Interfaces

CX3 supports the following serial peripherals:

2

4. A CCI interface (compatible with 100-kHz or 400-kHz I C

interface with 7-bit addressing) is provided to configure the

sensor.

■ UART

2

■ I C

5. GPIOs are available for synchronization of external flash or

lighting system with image sensors to illuminate the scene

that improves the image quality by improving Signal to noise

ratio.

2

■ I S

■ SPI

The CYUSB306X Pin List on page 15 shows the details of how

these interfaces are mapped.

6. GPIOs can also be used to synchronize the image sensor with

external events, so that image can be captured based on

external event.

UART Interface

2

7. Serial interfaces (such as I C, I S, SPI, UART) are available

to implement camera functions such as Auto focus and Pan,

Tilt, Zoom (PTZ)

The UART interface of CX3 supports full-duplex communication.

It includes the signals noted in Table 1.

Table 1. UART Interface Signals

Additional Outputs

Signal

TX

Description

Output signal

Input signal

Flow control

In addition to the standard MIPI CSI-2 signals, the following three

additional outputs are provided:

RX

1. XRST: this can be used to reset the image sensor

CTS

RTS

2. XSHUTDOWN: this pin can be used to put the sensor to a

standby/shutdown mode

3. MCLK: this pin can provide the clock output. It can be used

only for testing the image sensor. For production, use an

external clock generator as clock input for image sensors.

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then CX3's UART only transmits data when the CTS

input is asserted. In addition to this, CX3's UART asserts the RTS

output signal, when it is ready to receive data.

CPU

CX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.

The core has direct access to 16 kB of Instruction Tightly

Coupled Memory (TCM) and 8 kB of data TCM. The

ARM926EJ-S core provides a JTAG interface for firmware

debugging.

2

I C Interface

2

CX3’s I C interface is compatible with the I C Bus Specification

Revision 3. This I C interface is capable of operating only as I C

master; therefore, it may be used to communicate with other I C

2

slave devices. For example, CX3 may boot from an EEPROM

connected to the I C interface, as a selectable boot option.

CX3 offers the following advantages:

2

■ Integrates 512 KB of embedded SRAM for code and data and

8 kB of instruction cache and data cache.

2

CX3’s I C Master Controller also supports multi-master mode

functionality.

■ ImplementsefficientandflexibleDMAconnectivitybetweenthe

various peripherals (such as, USB, CSI-2 Rx, I S, SPI, and

UART), requiring firmware only to configure data accesses

between peripherals, which are then managed by the DMA

fabric.

2

The power supply for the I C interface is V

, which is a

DDIO1

separate power domain from the other serial peripherals. This

2

gives the I C interface the flexibility to operate at a different

voltage than the other serial interfaces.

■ Allows easy application development on industry-standard

development tools for ARM926EJ-S.

Document Number: 001-87516 Rev. *L

Page 7 of 37

CYUSB306X

2

The I C controller supports bus frequencies of 400 kHz, and

1 MHz. When V is 1.8 V, 2.5 V, or 3.3 V, the operating

Boot Options

DDIO1

2

frequencies supported are 400 kHz and 1 MHz. The I C

controller supports the clock-stretching feature to enable slower

devices to exercise flow control.

CX3 can load boot images from various sources, selected by the

configuration of the PMODE pins. Following are the CX3 boot

options:

2

The I C interface’s SCL and SDA signals require external pull-up

■ Boot from USB

resistors. The pull-up resistors must be connected to V

.

DDIO1

2

■ Boot from I C

2

Note: I C addresses with the pattern 0x0000111x are used inter-

nally and no slave devices with those addresses should be

connected to the bus.

■ Boot from SPI (SPI devices supported are M25P16 (16 Mbit),

M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents

2

I S Interface

Table 2. CX3 Booting Options

2

[1]

CX3 has an I S port to support external audio codec devices.

PMODE[2:0]

F11

Boot From

2

CX3 functions as I S Master as transmitter only. The I S

interface consists of four signals: clock line (I2S_CLK), serial

data line (I2S_SD), word select line (I2S_WS), and master

system clock (I2S_MCLK). CX3 can generate the system clock

as an output on I2S_MCLK or accept an external system clock

input on I2S_MCLK.

USB boot

2

F1F

I C, On failure, USB boot is enabled

2

1FF

I C only

0F1

SPI, On failure, USB boot is enabled

2

The sampling frequencies supported by the I S interface are

32 kHz, 44.1 kHz, and 48 kHz.

Reset

SPI Interface

Hard Reset

CX3 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

A hard reset is initiated by asserting the RESET# pin on CX3.

The specific reset sequence and timing requirements are

detailed in Figure 11 on page 26 and Table 14 on page 26. All

I/Os are tristated during a hard reset.

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 24 for details on the

modes) with the Start-Stop clock. This controller is a

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

An additional reset pin called MIPI_RESET is provided that

resets the MIPI CSI-2 core. It should be pulled down with a

resistor for normal operation.

Soft Reset

There are two types of Soft Reset:

■ CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset – This reset is identical to Hard Reset.

The firmware must be reloaded following a Whole Device

Reset.

Note

1. F indicates Floating.

Document Number: 001-87516 Rev. *L

Page 8 of 37

CYUSB306X

The input clock frequency is independent of the clock and data

rate of the CX3 core or any of the device interfaces (including the

CSI-2 Rx Port). The internal PLL applies the appropriate

clock-multiply option depending on the input frequency.

Clocking

CX3 requires two clocks for normal operation:

1. A 19.2-MHz clock to be connected at the CLKIN pin

2. A 6-MHz to 40-MHz clock to be connected at the REFCLK pin

Note: REFCLK and CLKIN must have either separate clock

inputs or if the same source is used, the clock must be passed

through a buffer with two outputs and then connected to the clock

pins.

Clock inputs to CX3 must meet the phase noise and jitter require-

ments specified in Table 3 on page 9.

Table 3. CX3 Input Clock Specifications

Specification

Units

Parameter

Description

100-Hz offset

Min

–

Max

–75

–104

–120

–128

–130

150

70

dB

ppm

%

1-kHz offset

10-kHz offset

100-kHz offset

1-MHz offset

–

Phase noise

–

Maximum frequency deviation

Duty cycle

–

30

–

Overshoot

3

%

Undershoot

–

–3

%

Rise time/fall time

–

3

ns

Table 4 provides the requirements for the optional 32-kHz clock

input

32-kHz Watchdog Timer Clock Input

CX3 includes a watchdog timer. The watchdog timer can be used

to interrupt the ARM926EJ-S core, automatically wake up the

CX3 in Standby mode, and reset the ARM926EJ-S core. The

watchdog timer runs a 32-kHz clock, which may be optionally

supplied from an external source on a dedicated CX3 pin.

Table 4. 32-kHz Clock Input Requirements

Parameter

Duty cycle

Min

40

–

Max

60

Units

%

The firmware can disable the watchdog timer.

Frequency deviation

Rise time/fall time

±200

200

ppm

ns

–

Document Number: 001-87516 Rev. *L

Page 9 of 37

CYUSB306X

Power Modes

Power

CX3 supports the following power modes:

CX3 has the following power supply domains:

■ Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

■ IO_VDDQ: This is a group of independent supply domains for

digital I/Os.

2

❐ V_DDIO1: GPIO, I C, JTAG, XRST, XSHUTDOWN and REF-

CLK

❐ Normal operating power consumption does not exceed the

sum of I Core max and I USB max (see DC

CC

2

❐ V_DDIO2: UART and I S (except MCLK)

Specifications on page 17 for current consumption

specifications).

2

❐ V_DDIO3: I S_MCLK and SPI

❐ C_VDDQ: CLKIN

❐ V_{DD_MIPI}: MIPI CSI-2 clock and data lanes

❐ The I/O power supplies V

and V

can be turned off

DDIO2

DDIO3

whenthecorrespondinginterfaceisnotinuse.V

never be turned off for normal operation.

should

DDIO1

■ V_DD: This is the supply voltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

❐ A_VDD: This is the 1.2 V supply for the PLL, crystal oscillator,

and other core analog circuits.

■ Low-power modes (see Table 5 on page 11):

❐ Suspend mode with USB 3.0 PHY enabled

❐ Standby mode

❐ Core power-down mode

❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2 V supply volt-

ages for the USB 3.0 interface.

■ VUSB: This is the 4 V to 6 V power supply for the USB I/O and

analog circuits. This supply powers the USB transceiver

through CX3’s internal voltage regulator. VUSB is internally

regulated to 3.3 V.

Note: The different power supplies have to be powered on or off

in a specific sequence as illustrated in Figure 4.

Figure 4. Power-up Sequence

VUSB

(VBUS)

VDD

(VDD, AVDD,

VDD_MIPI)

VDDIO1

<= 10 ms

CVDDQ, VDDIO2,

VDDIO3

CLK_IN, REFCLK

RESET#

MIPI_RESET

>= 1 ms

XRST

(Image Sensor RESET)

User programmable

in firmware

Document Number: 001-87516 Rev. *L

Page 10 of 37

CYUSB306X

Table 5. Entry and Exit Methods for Low-Power Modes

Low-Power Mode

Characteristics

Methods of Entry

Methods of Exit

■ Power consumption in this mode does not

exceed I

SB1

■ USB3.0PHYisenabledandisinU3mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block

alone is operational with its internal clock,

while all other clocks are shut down

■ D+ transitioning to low

or high

■ All I/Os maintain their previous state

■ D- transitioning to low

or high

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on or off

individually

■ Firmware executing on

■ Resume condition on

SSRX±

ARM926EJ-S core can put CX3 into

the suspend mode. For example, on

USBsuspendcondition,thefirmware

may decide to put CX3 into suspend

mode

Suspend Mode with

USB 3.0 PHY

Enabled

■ Detection of VBUS

■ The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■ Level detect on

UART_CTS

(programmable

polarity)

■ All transactions must be completed before

CX3 enters suspend mode (state of

outstanding transactions are not

preserved)

■ Assertion of RESET#

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

■ Thepowerconsumptioninthismodedoes

not exceed ISB3

■ All configuration register settings and

program/data RAM contents are

preserved. However, data in the buffers or

other parts of the data path, if any, is not

guaranteed. Therefore, the external

processor should take care that the data

needed is read before putting CX3 into the

standby mode

■ Detection of VBUS

■ The program counter is reset after waking

up from the standby mode

■ The firmware executing on

ARM926EJ-S core or external

■ Level detect on

UART_CTS

Standby Mode

processorconfigurestheappropriate (programmable

■ GPIO pins maintain their configuration

■ Internal PLL is turned off

register

polarity)

■ Assertion of RESET#

■ USB transceiver is turned off

■ ARM926EJ-S core is powered down.

Upon wakeup, the core re-starts and runs

the program stored in the program/data

RAM

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on or off

individually

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Page 11 of 37

CYUSB306X

Table 5. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode

Characteristics

Methods of Entry

Methods of Exit

■ Thepowerconsumptioninthismodedoes

not exceed ISB

4

■ Core power is turned off

■ Reapply V

■ All buffer memory, configuration registers,

and the program RAM do not maintain

state. After exiting this mode, reload the

firmware

DD

Core Power-down

Mode

■ Turn off V

DD

■ Assertion of RESET#

■ In this mode, all other power domains can

be turned on or off individually

Document Number: 001-87516 Rev. *L

Page 12 of 37

CYUSB306X

Configuration Options

EMI

Configuration options are available for specific usage models.

Contact Cypress Marketing (usb3@cypress.com) for details.

CX3 can meet EMI requirements outlined by FCC 15B (USA)

and EN55022 (Europe) for consumer electronics at system level.

CX3 can tolerate reasonable EMI, conducted by the aggressor,

outlined by these specifications and continue to function as

expected.

Digital I/Os

CX3 has internal firmware-controlled pull-up or pull-down

resistors on all digital I/O pins. An internal 50-k resistor pulls

the pins high, while an internal 10-k resistor pulls the pins low

to prevent them from floating. The I/O pins may have the

following states:

System-level ESD

CX3 has built-in ESD protection on the D+, D–, and GND pins

on the USB interface. The ESD protection levels provided on

these ports are:

■ Tristated (High-Z)

■ ±2.2-kV human body model (HBM) based on JESD22-A114

specification

■ Weak pull-up (via internal 50 k)

■ Pull-down (via internal 10 k)

■ ±6-kV contact discharge and ±8-kV air gap discharge based

on IEC61000-4-2 level 3A using external system-level

protection devices

■ Hold (I/O hold its value) when in low-power modes

■ The JTAG TDI, TMC, and TRST# signals have fixed 50-k

internal pull-ups, and the TCK signal has a fixed 10-k

pull-down resistor.

■ ± 8-kV contact discharge and ±15-kV air gap discharge based

on IEC61000-4-2 level 4C using external system-level

protection devices

All unused I/Os should be pulled high by using the internal

pull-up resistors. All unused outputs should be left floating. All

I/Os can be driven at full-strength, three-quarter strength,

half-strength, or quarter-strength. These drive strengths are

configured separately for each interface.

This protection ensures that the device continues to function

after ESD events up to the levels stated in this section.

The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to

±2.2-kV HBM internal ESD protection.

GPIOs

CX3 provides 12 pins for general purpose I/O (for example, can

be used for lighting, sync-in, sync-out and so on). See Pin

Configuration on page 14 for pinout details.

All GPIO pins support an external load of up to 16 pF for every

pin.

Document Number: 001-87516 Rev. *L

Page 13 of 37

CYUSB306X

Pin Configuration

Figure 5. CX3 Ball Map (Top View)

A1

A2

A3

A4

SSRXP

B4

A5

SSTXP

B5

A6

SSTXM

B6

A7

AVDD

B7

A8

VSS

B8

A9

DP

B9

A10

DM

A11

GPIO[24]

B11

U3VSSQ U3RXVDDQ SSRXM

B1

VDDIO3

C1

B2

VSS

C2

B3

GPIO[23]

C3

B10

VDD

C10

GPIO[21] U3TXVDDQ

CVDDQ

C6

AVSS

C7

VSS

C8

VSS

C9

TRST#

C11

C4

GPIO[26]

D4

C5

RESET#

D5

SPI_SSN / SPI_MISO /

GPIO[54]

I2S_MCLK

/ GPIO[57]

VDD

GPIO[18]

D6

GPIO[19]

D7

GPIO[22]

D8

GPIO[45]

D9

TDO

GPIO[55]

D1

D2

D3

D10

D11

I2S_CLK /

GPIO[50]

I2S_SD /

GPIO[51]

I2S_WS / SPI_SCK / SPI_MOSI /

CLKIN_32

E6

CLKIN

E7

VSS

E8

I2C_SCL

E9

I2C_SDA GPIO[17]

GPIO[52]

GPIO[53]

GPIO[56]

E1

E2

VSS

E3

E4

E5

E10

VUSB

F10

E11

VSS

UART_CTS /

GPIO[47]

UART_RX / UART_TX /

VDDIO2

F3

GPIO[20]

F6

TDI

TMS

F8

VDD

F9

GPIO[49]

GPIO[48]

F1

DNU

G1

F2

F4

F5

F7

F11

UART_RTS /

GPIO[46]

REFCLK

G2

GPIO[44]

G3

XRST

TCK

DNU

G7

DNU

G8

DNU

G9

DNU

G10

VDD

G11

G4

G5

G6

XSHUTDOW

N

PMODE[0] /

GPIO[30]

VSS

H1

MCLK

H3

GPIO[25] HSYNC_test

H5 H6

DNU

H7

DNU

H8

DNU

H9

DNU

H10

VSS

H2

H4

H11

PMODE[1] /

GPIO[31]

VDD

DNU

VSYNC_test MIPI RESET

DNU

PCLK_test

DNU

VDDIO1

J1

DNU

K1

J2

DNU

K2

J3

DNU

K3

J4

DNU

K4

J5

J6

J7

MIPI_CP

K7

J10

DNU

K10

DNU

L10

J11

VDD

K11

DNU

L11

J8

J9

MIPI_D1P¹

MIPI_D0P

MIPI_D2P^{1, 2}MIPI_D2N^{1, 2}

K5

MIPI_D0N

L5

K8

MIPI_D3N^{1, 2}

L8

K9

DNU

L9

K6

MIPI_D1N¹

L6

DNU

L1

DNU

L2

VSS

L3

VSS

L4

MIPI_CN

L7

PMODE[2] /

GPIO[32]

MIPI_D3P^{1, 2}

VSS

VDD_MIPI

VSS

VDD

VDDIO1

DNU

VSS

1. Unused MIPI input data lanes to be connected to GND.

2. The signals MIPI_D2N, MIPI_D2P, MIPI_D3N, and MIPI_D3P are not available in the CYUSB3064 part. These pins should be left "open" in the customer board.

Legend

Ground

USB PHY power supply; Clock power supply

Power supply

Document Number: 001-87516 Rev. *L

Page 14 of 37

CYUSB306X

Table 6. CYUSB306X Pin List (continued)

Pin Description

CX3

Table 6. CYUSB306X Pin List

Pin#

C4

F3

Pin name

I/O

I

CX3

GPIO[26]

Pin#

F10

F9

Pin name

DNU

I/O

GPIO[44]

C9

G4

H4

L4

GPIO[45]

DNU

PMODE[0] / GPIO[30]

PMODE[1] / GPIO[31]

PMODE[2] / GPIO[32]

DNU

F7

DNU

G10

G9

F8

DNU

F1

DNU

H6

C5

F4

MIPI RESET

H10

H9

J10

H7

K11

L10

K10

K9

DNU

RESET#

DNU

XRST

O

DNU

G2

G3

XSHUTDOWN

O

DNU

MCLK

O

DNU

VDDIO2 Power Domain

UART_RTS / GPIO[46]

UART_CTS / GPIO[47]

UART_TX / GPIO[48]

UART_RX / GPIO[49]

I2S_CLK / GPIO[50]

I2S_SD / GPIO[51]

I2S_WS / GPIO[52]

VDDIO3 Power Domain

SPI_SCK / GPIO[53]

SPI_SSN / GPIO[54]

SPI_MISO / GPIO[55]

SPI_MOSI / GPIO[56]

I2S_MCLK / GPIO[57]

DNU

F5

E1

E5

E4

D1

D2

D3

I/O

DNU

G7

G8

K2

DNU

J4

DNU

K1

DNU

J2

DNU

D4

C1

I/O

J3

DNU

J1

DNU

C2

H2

H3

G6

H5

H8

DNU

D5

DNU

C11

HSYNC_test

VSYNC_test

PCLK_test

VDDIO1 Power Domain

GPIO[17]

GPIO[18]

GPIO[19]

GPIO[20]

GPIO[21]

GPIO[22]

GPIO[23]

GPIO[24]

GPIO[25]

USB Port (U3TXVDDQ/U3RXVDDQ

Power Domain)

A3

A4

A6

A5

SSRXM

I

SSRXP

I

D11

C6

C7

E6

I/O

SSTXM

O

SSTXP

USB Port (VUSB Power Domain)

A9

DP

DM

I/O

B4

A10

C8

B3

VDDIO1 Power Domain

REFCLK

F2

J7

I

A11

G5

VDD_MIPI Power Domain

MIPI_CP

Document Number: 001-87516 Rev. *L

Page 15 of 37

CYUSB306X

Table 6. CYUSB306X Pin List (continued)

CX3

Pin name

VDD

VSS

Pin#

K7

J5

Pin name

MIPI_CN

MIPI_D0P

MIPI_D0N

I/O

Pin#

L7

I/O

I

PWR

D8

E2

E11

G1

A8

G11

L1

K5

J6

1

MIPI_D1P

MIPI_D1N

1

K6

J9

1, 2

MIPI_D2N

MIPI_D2P

MIPI_D3P

MIPI_D3N

J8

L8

K8

B8

L6

CVDDQ Power Domain

CLKIN

D7

D6

I

B2

L11

B9

K4

L3

CLKIN_32

VDDIO1 Power Domain

I2C_SCL

I2C_SDA

TDI

D9

D10

E7

I/O

I

O

I

K3

L2

C10

B11

E8

TDO

TRST#

1. Unused MIPI input data lanes to be connected to GND.

2. The signals MIPI_D2N, MIPI_D2P, MIPI_D3N, and MIPI_D3P are not available

in the CYUSB3064 part. These pins should be left "open" in the customer

board.

TMS

I

F6

TCK

I

Power Domains

VUSB

E10

A1

PWR

U3VSSQ

VDDIO1

VDDIO2

VDDIO3

CVDDQ

U3TXVDDQ

U3RXVDDQ

AVDD

H11

L9

E3

B1

B6

B5

A2

A7

B7

AVSS

L5

VDD_MIPI

VDD

B10

J11

C3

E9

VDD

F11

H1

VDD

Document Number: 001-87516 Rev. *L

Page 16 of 37

CYUSB306X

Absolute Maximum Ratings

Operating Conditions

Exceeding maximum ratings may shorten the useful life of the

device.

T (ambient temperature under bias)

A

Industrial ................................................... –40 °C to +85 °C

V , A , U3TX , U3RX

DD VDDQ

Storage temperature ......................... ...... –65 °C to +150 °C

Supply voltage to ground potential

VDDQ

Supply voltage .............................................1.15 V to 1.25 V

V

, A

................................................................. 1.25 V

V supply voltage ..............................................4 V to 6 V

USB

DD VDDQ

V

, V

................................................3.6 V

..............................................1.25 V

V

, V

, C

DDIO1

DDIO2

DDIO3

, U3RX

VDDQ

DDIO1

DDIO2

DDIO3 VDDQ

Supply voltage .................................................1.7 V to 3.6 V

U3TX

VDDQ

DC input voltage to any input pin ...........................V + 0.3

CC

DC voltage applied to

outputs in high Z state

(V is the corresponding I/O voltage) ..................V + 0.3

CC

Maximum latch-up current ........................................ 140 mA

Maximum output short-circuit current

for all I/O configurations. (V

= 0 V) .................. –100 mA

OUT

DC Specifications

Parameter

Description

Min

1.15

Max

1.25

Units

Notes

V

Core voltage supply

V

1.2-V typical

DD

A

Analog voltage supply

VDD

MIPI bridge D-PHY supply

voltage

V

1.15

1.7

1.25

3.6

V

1.2-V typical

DD_MIPI

2

I C, JTAG and GPIO power

V

1.8-, 2.5-, and 3.3-V typical

DDIO1

domain

2

V

UART/I S power supply domain

1.7

4

3.6

6

V

1.8-, 2.5-, and 3.3-V typical

5-V typical

DDIO2

DDIO3

USB

2

SPI/I S power supply domain

USB voltage supply

USB 3.0 1.2-V supply

1.2-V typical. A 22-µF bypass

capacitor is required on this power

supply.

U3TX

1.15

1.25

V

VDDQ

1.2-V typical. A 22-µF bypass

capacitor is required on this power

supply.

U3RX

USB 3.0 1.2-V supply

Clock voltage supply

Input HIGH voltage 1

1.15

1.7

1.25

3.6

V

C

1.8-, 3.3-V typical

VDDQ

For2.0 V V  3.6 V(exceptUSB

CC

V

0.625 × V

V

+ 0.3

and MIPI CSI-2 pins).V is the

IH1

CC

corresponding I/O voltage supply.

For 1.7 V  V 2.0 V

CC

(except USB USB and MIPI CSI-2

V

Input HIGH voltage 2

V

– 0.4

+ 0.3

V

IH2

CC

pins).V is the corresponding I/O

CC

voltage supply.

V

is the corresponding I/O

CC

V

Input LOW voltage

–0.3

0.25 × V

–

V

IL

CC

voltage supply.

I

(max) = –100 µA tested at

OH

Output HIGH voltage

0.9 × V

–

quarter drive strength. V is the

OH

CC

corresponding I/O voltage supply.

I

(min)=+100µAtestedatquarter

OL

V

Output LOW voltage

0.1 × V

V

drive strength. V is the

OL

CC

corresponding I/O voltage supply.

Document Number: 001-87516 Rev. *L

Page 17 of 37

CYUSB306X

DC Specifications (continued)

Parameter

Description

Min

Max

Units

Notes

All I/O signals held at V

(For I/Os with a pull-up or pull-down

µA resistor connected, the leakage

DDQ

Input leakage current for all pins

except

I

–1

1

IX

SSTXP/SSXM/SSRXP/SSRXM

current increases by V /R or

DDQ PU

V

/R

)

DDQ PD

OutputHigh-Zleakagecurrentfor

all pins except SSTXP/ SSXM/

SSRXP/SSRXM and MIPI CSI-2

signals

I

–1

1

µA All I/O signals held at V

DDQ

OZ

Core and analog voltage

operating current

I

Core

USB

–

192

60

mA Total current through A

, V

CC

VDD DD

USB voltage supply operating

current

mA

–

CC

Core: 558.35 µA

I/O: 4.58 µA

–

µA Core Current is measured through

Total suspend current during

suspend mode with USB 3.0 PHY

enabled

V

, A

and V

.

DD VDD

DD_MIPI

I

µA

SB1

SB3

USB: 4672 µA

Core: 148.31 µA

I/O: 3.16 µA

I/O Current is measured through

to V

V

.

DDIO3

DDIO1

Total standby current during core

power-down mode

I

USB Current is measured through

, U3TX and U3RX .

VDDQ

USB: 15.8 µA

V

USB

VDDQ

Voltage ramp rate on core and I/O

supplies

V

0.2

–

12

100

20

V/ms Voltage ramp must be monotonic

RAMP

Noise level permitted on V and

Max p-p noise level permitted on all

supplies except A

DD

mV

N

I/O supplies

VDD

Noise level permitted on A

supply

Max p-p noise level permitted on

VDD

–

N_AVDD

A

VDD

MIPI D-PHY Electrical Characteristics

Spec

Nom

Parameter

Description

Unit

Min

Max

MIPI D-PHY RX DC Characteristics

V

Pin signal voltage range

–50

880

–

1350

–

mV

Logic 1 input voltage

IH

Logic 0 input voltage

550

330

70

IL

Common-mode voltage HS receiver mode

Differential input high threshold

Differential input low threshold

Single-ended input high voltage

Single-ended input low voltage

70

CMRX (DC)

IDTH

IDTL

IHHS

ILHS

–70

–40

–

460

–

Document Number: 001-87516 Rev. *L

Page 18 of 37

CYUSB306X

AC Timing Parameters

MIPI Data to Clock Timing Reference

Figure 6. MIPI CSI Signal Data to Clock Timing Reference

Reference Time

T_SETUP

T_HOLD

0.5UI_INST

T_SKEW

+

CLKp

CLKn

1 UI_INST

T_CLKp

Table 7. MIPI Data to Clock Timing Reference

Parameter

Description

Min

Max

Units

T

Data to clock skew measured at the transmitter

Data to clock setup time at receiver

Clock to data hold time at receiver

One data bit time (instantaneous)

Period of dual data rate clock

–0.15

0.15

1

0.15

–

UI

SKEW

SETUP

HOLD

INST

–

UI

12.5

25

ns

INST

CLKp

T

2

Reference Clock Specifications

Table 8. Reference Clock Specifications

Parameter

RefClk

Description

Min

Max

Units

Notes

Reference clock frequency

6

40

MHz

–

RefclkDutyCyl Duty cycle

40%

-100

60%

100

RefClkPJ

Reference clock input period jitter

ps

Document Number: 001-87516 Rev. *L

Page 19 of 37

CYUSB306X

MIPI CSI Signal Low Power AC Characteristics

Figure 7. MIPI CSI bus Input Glitch Rejection

2*T_LPX

e_SPIKE

V_IH

V_IL

Input

e_SPIKE

T_MIN-RX

Output

Table 9. MIPI CSI Signal Low Power AC Characteristics

Parameter

Description

Min

Max

300

–

Units

Notes

Time-voltage integration of a spike above V

IL

when being in LP-0 or below V when being in

IH

e

Input noise rejection

–

V.ps LP-1 state.

SPIKE

An impulse less than this will not change the

receiver state.

An input pulse greater than this shall toggle the

output.

T

Minimum pulse width response

20

ns

MIN-RX

V

peak interference amplitude

Interference frequency

–

200

–

mV

–

INT

F

450

MHz

INT

Length of any low power state

period

T

50

–

ns

–

LPX

AC Specifications

Table 10. AC Specifications

Parameter

Description

Min

Max

Units

Details / Conditions

Common-mode interference

beyond 450 MHz

∆V

is the peak amp. Of a sine wave

CMRX(HF)

∆V_CMRX(HF)

–

100

mV

superimposed on the receiver inputs.

Excluding static ground shift of 50 mV.

mV Voltage difference compared to the DC average

common-mode potential

Common-mode interference

beyond 50 - 450 MHz

∆V

-50

50

CMRX(LF)

Document Number: 001-87516 Rev. *L

Page 20 of 37

CYUSB306X

Serial Peripherals Timing

I²C Timing

Figure 8. I²C Timing Definition

[2]

Table 11. I²C Timing Parameters

Parameter

Description

Min

Max

Units

I²C Standard Mode Parameters

f

t

SCL clock frequency

0

4

100

–

kHz

µs

ns

µs

SCL

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

HD:STA

LOW

4.7

4

–

HIGH

SU:STA

HD:DAT

SU:DAT

r

Setup time for a repeated START condition

Data hold time

4.7

0

–

Data setup time

250

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

1000

300

–

t

–

f

4

SU:STO

BUF

4.7

–

3.45

n/a

VD:DAT

VD:ACK

SP

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

n/a

Note

2. All parameters guaranteed by design and validated through characterization.

Document Number: 001-87516 Rev. *L

Page 21 of 37

CYUSB306X

[2]

Table 11. I²C Timing Parameters (continued)

Parameter

Description

Min

Max

Units

I²C Fast Mode Parameters

f

t

SCL clock frequency

0

0.6

1.3

0.6

0

400

–

kHz

µs

ns

µs

ns

SCL

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

HD:STA

LOW

–

HIGH

SU:STA

HD:DAT

SU:DAT

r

Setup time for a repeated START condition

Data hold time

–

Data setup time

100

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

300

–

t

–

f

0.6

1.3

–

SU:STO

BUF

–

0.9

50

VD:DAT

VD:ACK

SP

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

I²C Fast Mode Plus Parameters

SCL clock frequency

0

f

t

0

0.26

0.5

0.26

0

1000

–

kHz

µs

ns

µs

ns

SCL

Hold time START condition

HD:STA

LOW

LOW period of the SCL

–

HIGH period of the SCL

–

HIGH

SU:STA

HD:DAT

SU:DAT

r

Setup time for a repeated START condition

Data hold time

–

Data setup time

50

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus-free time between a STOP and START condition

Data valid time

120

–

t

–

f

0.26

0.5

–

SU:STO

BUF

–

0.45

0.55

50

VD:DAT

VD:ACK

SP

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

0

Document Number: 001-87516 Rev. *L

Page 22 of 37

CYUSB306X

I²S Timing Diagram

Figure 9. I²S Transmit Cycle

t_T

t_TRt_TF

t_TH

t_TL

SCK

t_Thd

SA,

WS (output)

t_Td

[3]

Table 12. I²S Timing Parameters

Parameter

Description

Min

Max

Units

ns

2

t

I S transmitter clock cycle

t

–

T

TR

2

I S transmitter cycle LOW period

0.35 t

ns

TL

TH

TR

TF

Thd

Td

TR

2

I S transmitter cycle HIGH period

0.35 t

ns

2

I S transmitter rise time

–

0

–

0.15 t

–

ns

TR

2

I S transmitter fall time

ns

2

I S transmitter data hold time

ns

2

I S transmitter delay time

0.8 t

ns

T

Note t is selectable through clock gears. Max t is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).

T

TR

Note

3. All parameters guaranteed by design and validated through characterization.

Document Number: 001-87516 Rev. *L

Page 23 of 37

CYUSB306X

SPI Timing Specification

Figure 10. SPI Timing

SSN

(output)

t_ssnh

t_sck

t_lag

t_lead

SCK

(CPOL=0,

Output)

t_rf

t_wsck

SCK

(CPOL=1,

Output)

t_sdi

t_hoi

LSB

MISO

(input)

MSB

t_d

t_dis

t_sdd

t_di

v

MOSI

(output)

LSB

SPI Master Timing for CPHA = 0

SSN

(output)

t_ssnh

t_sck

t_lag

t_lead

t_rf

SCK

(CPOL=0,

Output)

t_wsck

SCK

(CPOL=1,

Output)

t_hoi

LSB

t_sdi

MISO

(input)

MSB

t_dis

t_di

t_dv

MOSI

(output)

LSB

SPI Master Timing for CPHA = 1

Document Number: 001-87516 Rev. *L

Page 24 of 37

CYUSB306X

[4]

Table 13. SPI Timing Parameters

Parameter

Description

Min

0

Max

33

–

Units

MHz

ns

f

t

Operating frequency

Cycle time

op

30

sck

wsck

lead

lag

rf

Clock HIGH/LOW time

SSN-SCK lead time

Enable lag time

Rise/fall time

13.5

–

ns

[5]

1/2 t

– 5

1.5 t

+ 5

ns

sck

[5]

0.5

–

ns

sck

8

5

–

ns

Output SSN to valid data delay time

Output data valid time

–

ns

sdd

dv

–

ns

Output data invalid

0

ns

di

Minimum SSN HIGH time

Data setup time input

10

8

ns

ssnh

sdi

hoi

dis

ns

Data hold time input

0

ns

Disable data output on SSN HIGH

0

ns

Notes

4. All parameters guaranteed by design and validated through characterization.

5. Depends on LAG and LEAD setting in the SPI_CONFIG register.

Document Number: 001-87516 Rev. *L

Page 25 of 37

CYUSB306X

Reset Sequence

CX3’s hard reset sequence requirements are specified in this section.

Table 14. Reset and Standby Timing Parameters

Parameter

Definition

Minimum RESET# pulse width

Conditions

Clock Input

–

Min (ms) Max (ms)

t

1

5

–

RPW

Minimum HIGH on RESET#

RH

RR

Reset recovery time (after which the boot loader begins

firmware download)

t

Clock Input

1

–

Time to enter standby/suspend mode (from the time

MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)

t

–

1

5

1

–

SBY

WU

WH

Time to wakeup from standby

Clock Input

–

Minimum time before standby/suspend source may be

reasserted

Figure 11. Reset Sequence

VDD

( core )

xVDDQ

CLKIN

CLKIN must be stable before

exiting Standby/Suspend

t_Rh

t_RR

Mandatory

Reset Pulse

Hard Reset

RESET#

t_WH

t_WU

t_RPW

t_SBY

Standby/

Suspend

Source

Standby/Suspend

source Is deasserted

Standby/Suspend source Is asserted

(MAIN_POWER_EN/ MAIN_CLK_EN bit is set)

Document Number: 001-87516 Rev. *L

Page 26 of 37

CYUSB306X

Ordering Information

Table 15. Ordering Information

Ordering Code

CYUSB3065-BZXI

CYUSB3065-BZXC

CYUSB3064-BZXI

CYUSB3064-BZXC

MIPI CSI-2 Lanes

Package Type

121-ball BGA

Temperature Grade

4

2

Industrial

Commercial

Industrial

Commercial

Ordering Code Definitions

X

BZ

I

3

CY USB

06X -

Temperature Grade:

I = Industrial

C = Commercial

Pb-free

Package Type: BZ = 121-ball BGA

X = 4 for up to 2 MIPI CSI-2 lanes

X = 5 for up to 4 MIPI CSI-2 lanes

Density: Base part number for USB 3.0

Marketing Code: USB = USB Controller

Company ID: CY = Cypress

Document Number: 001-87516 Rev. *L

Page 27 of 37

CYUSB306X

Package Diagram

Figure 12. 121-ball BGA (10 × 10 × 1.7 mm) Package Outline, 001-87293

001-87293 **

Document Number: 001-87516 Rev. *L

Page 28 of 37

CYUSB306X

Acronyms

Document Conventions

Table 16. Acronyms Used in this Document

Units of Measure

Acronym

CSI - 2

Description

Camera Serial Interface - 2

Direct Memory Access

Do Not Use

Table 17. Units of Measure

Symbol

°C

Unit of Measure

DMA

DNU

HNP

MIPI

MMC

MTP

PLL

degree Celsius

Megabits per second

Megabytes per second

megahertz

Mbps

MBps

MHz

µA

Host Negotiation Protocol

Mobile Industry Processor Interface

Multimedia Card

microampere

microsecond

milliampere

millisecond

Media Transfer Protocol

Phase Locked Loop

µs

mA

ms

ns

PMIC

SD

Power Management IC

Secure Digital

nanosecond

ohm

SDIO

SLC

Secure Digital Input / Output

Single-Level Cell



pF

picofarad

SPI

Serial Peripheral Interface

Session Request Protocol

Universal Serial Bus

V

volt

SRP

USB

WLCSP

Wafer Level Chip Scale Package

Document Number: 001-87516 Rev. *L

Page 29 of 37

CYUSB306X

Errata

This section describes the errata for CX3. Details include errata trigger conditions, scope of impact, available workaround, and silicon

revision applicability. Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

Device Characteristics

CYUSB306x-xxxx

All Variants

Qualification Status

Product Status: Production

Errata Summary

The following table defines the errata applicability to available EZ-USB CX3 SuperSpeed USB Controller family devices.

Items

[Part Number]

Silicon Revision

Fix Status

1. Turning off VDDIO1 during Normal, Suspend, and

Standby modes causes the CX3 to stop working.

CYUSB306x-xxxx

All

Workaround provided

2. USB enumeration failure in USB boot mode when CX3

is self-powered.

CYUSB306x-xxxx

All

Workaround provided

3. Extra ZLP is generated by the COMMIT action in the

GPIF II state.

4. Invalid PID Sequence in USB 2.0 ISOC data transfer.

CYUSB306x-xxxx

All

Workaround provided

5. USB data transfer errors are seen when ZLP is followed

by data packet within same microframe.

6. Bus collision is seen when the I2C block is used as a

master in the I2C Multi-master configuration.

CYUSB306x-xxxx

All

Use CX3 in single-master

configuration

1. Turning off VDDIO1 during Normal, Suspend, and Standby modes causes the CX3 to stop working.

■ Problem Definition

Turning off the VDDIO1 during Normal, Suspend, and Standby modes will cause the CX3 to stop working.

■ Parameters Affected

N/A

■ Trigger Conditions

This condition is triggered when the VDDIO1 is turned off during Normal, Suspend, and Standby modes.

■ Scope Of Impact

CX3 stops working.

■ Workaround

VDDIO1 must stay on during Normal, Suspend, and Standby modes.

■ Fix Status

No fix. Workaround is required.

Document Number: 001-87516 Rev. *L

Page 30 of 37

CYUSB306X

2. USB enumeration failure in USB boot mode when CX3 is self-powered.

■ Problem Definition

CX3 device may not enumerate in USB boot mode when it is self-powered. The bootloader is designed for bus power mode. It

does not make use of the VUSB pin on the USB connector to detect the USB connection and expect that USB bus is connected

to host if it is powered. If CX3 is not already connected to the USB host when it is powered, then it enters into low-power mode

and does not wake up when connected to USB host.

■ Parameters Affected

N/A

■ Trigger Conditions

This condition is triggered when CX3 is self-powered in USB boot mode.

■ Scope of Impact

Device does not enumerate

■ Workaround

Reset the device after connecting to USB host.

■ Fix Status

No fix. Workaround is required.

3. Extra ZLP is generated by the COMMIT action in the GPIF II state.

■ Problem Definition

When COMMIT action is used in a GPIF-II state without IN_DATA action then an extra Zero Length Packet (ZLP) is committed

along with the data packets.

■ Parameters Affected

N/A

■ Trigger Conditions

This condition is triggered when COMMIT action is used in a state without IN_DATA action.

■ Scope of Impact

Extra ZLP is generated.

■ Workaround

Use IN_DATA action along with COMMIT action in the same state.

■ Fix Status

No fix. Workaround is required.

Document Number: 001-87516 Rev. *L

Page 31 of 37

CYUSB306X

4. Invalid PID Sequence in USB 2.0 ISOC data transfer.

■ Problem Definition

When the CX3 device is functioning as a high speed USB device with high bandwidth isochronous endpoints, the PID sequence

of the ISO data packets is governed solely by the isomult setting. The length of the data packet is not considered while generating

the PID sequence during each microframe. For example, even if a short packet is being sent on an endpoint with MULT set to 2;

the PID used will be DATA2.

■ Parameters Affected

N/A

■ Trigger Conditions

This condition is triggered when high bandwidth ISOC transfer endpoints are used.

■ Scope of Impact

ISOC data transfers failure.

■ Workaround

This problem can be worked around by reconfiguring the endpoint with a lower isomult setting prior to sending short packets, and

then switching back to the original value.

■ Fix Status

No fix. Workaround is required.

5. USB data transfer errors are seen when ZLP is followed by data packet within same microframe.

■ Problem Definition

Some data transfer errors may be seen if a Zero Length Packet is followed very quickly (within one microframe or 125 µs) by

another data packet on a burst enabled USB IN endpoint operating at super speed.

■ Parameters Affected

N/A

■ Trigger Conditions

This condition is triggered in SuperSpeed transfer with ZLPs.

■ Scope of Impact

Data failure and lower data speed.

■ Workaround

The solution is to ensure that some time is allowed to elapse between a ZLP and the next data packet on burst enabled USB IN

endpoints. If this cannot be ensured at the data source, the CyU3PDmaChannelSetSuspend() API can be used to suspend the

corresponding USB DMA socket on seeing the EOP condition. The channel operation can then be resumed as soon as the suspend

callback is received.

■ Fix Status

No fix. Workaround is required.

Document Number: 001-87516 Rev. *L

Page 32 of 37

CYUSB306X

6. Bus collision is seen when the I²C block is used as a master in the I²C Multi-master configuration.

■ Problem Definition

2

When CX3 is used as a master in the I C multi-master configuration, there can be occasional bus collisions.

■ Parameters Affected

NA

■ Trigger Conditions

2

This condition is triggered only when the CX3 I C block operates in Multi-master configuration.

■ Scope of Impact

2

The CX3 I C block can transmit data when the I C bus is not idle leading to bus collision.

■ Workaround

Use CX3 as a single master.

■ Fix Status

No fix.

Document Number: 001-87516 Rev. *L

Page 33 of 37

CYUSB306X

Document History Page

Document Title: CYUSB306X, EZ-USB^®CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller

Document Number: 001-87516

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

3994736

4065766

KUMR

05/09/2013 New datasheet

*A

07/17/2013 Updated Logic Block Diagram.

Updated Pin Description.

Updated DC Specifications.

Replaced “VBUS” and “VBATT” by “VUSB” in all instances across the

document.

Updated in new template.

*B

*C

*D

4080302

4088328

4113754

KUMR

07/29/2013 Updated status as “Preliminary”.

08/06/2013 Updated Pin Configuration (Updated Figure ).

09/04/2013 Updated Clocking: Added a Note at the bottom of section.

Updated Pin Description.

Updated Table 6.

Updated DC Specifications:

Updated description of V

parameter.

DDIO2

DDIO3

Changed maximum value of I Core parameter from 200 mA to 380 mA.

CC

*E

4188453

KUMR

11/14/2013 Changed status from Preliminary to Final.

Updated Features: Updated description.

Updated Applications: Updated description.

Updated Logic Block Diagram.

Updated Functional Overview.

Updated MIPI CSI-2 RX Interface.

Updated Additional Outputs: Updated description.

Updated Reset.

Updated Soft Reset: Updated description.

Updated Power.

Updated Power Modes.

Updated Table 5.

Updated “Methods of Entry” corresponding to “Suspend Mode with USB 3.0

PHY Enabled”.

Updated “Characteristics” corresponding to “Standby Mode”.

Updated EMI: Updated description.

Updated System-level ESD: Updated description.

Updated Pin Configuration:

Updated details of G4, H4, L4, F1, F5, E1, E5, E4, D1, D2, D3, D4, C1, C2,

D5, C11 pins in Figure .

Updated Pin Description.

Updated details in “Pin name” column for G4, H4, L4, F1, F5, E1, E5, E4, D1,

D2, D3, D4, C1, C2, D5, C11 pins.

Updated Absolute Maximum Ratings:

Removed “Ambient temperature with power applied”.

Removed “Static discharge voltage ESD protection levels”.

Renamed “Latch-up current” as “Maximum latch-up current” and updated the

values.

Updated DC Specifications:

Updated details in “Notes” column corresponding to V and V parameters.

IH1

IH2

Updated description of I parameter.

OZ

Updated minimum value of I

and I

parameters.

SB1

SB3

Updated details in “Notes” column corresponding to I

Added MIPI D-PHY Electrical Characteristics.

Updated AC Timing Parameters.

and I

parameters.

SB3

SB1

Updated MIPI Data to Clock Timing Reference.

Document Number: 001-87516 Rev. *L

Page 34 of 37

CYUSB306X

Document History Page (continued)

Document Title: CYUSB306X, EZ-USB^®CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller

Document Number: 001-87516

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*E (cont.)

4188453

KUMR

11/14/2013 Updated Figure 6.

Updated Table 7.

Updated minimum value of UI

parameter.

INST

Updated maximum value of T

CLKp

Updated MIPI CSI Signal Low Power AC Characteristics:

Updated Figure 7.

Updated Serial Peripherals Timing.

Updated I2C Timing.

Updated Table 11:

2

Removed “(Not supported at I2C_VDDQ = 1.2 V)” in “I C Fast Mode Plus

Parameters” sub-heading.

Updated Reset Sequence.

Updated Table 14.

Removed “Crystal Input” condition for t

Updated Figure 11.

, t , t

parameters.

RPW RR WU

Updated Ordering Information: Updated part numbers.

*F

4214952

RAJA

03/12/2014 Updated Features.

Updated Functional Overview.

Updated Application Examples.

Updated Figure 1.

Updated Configuration Options: Added email.

Updated Pin Description.

Updated caption of Table 6.

Updated DC Specifications:

Updated maximum value of V parameter.

IL

Updated maximum value of V

parameter.

RAMP

Updated AC Timing Parameters.

Updated MIPI CSI Signal Low Power AC Characteristics.

Updated Table 9.

Updated details in “Notes” column.

Updated to new template.

*G

*H

4417040

4467092

KUMR

RAJA

06/23/2014 Updated Power: Updated details of IO_VDDQ power supply domain.

Updated DC Specifications: Updated maximum value of I Core parameter.

CC

08/06/2014 Added new part numbers: 2 and 4 MIPI CSI-2 lane parts with Industrial and

Commercial temperature grades.

HSYNC, VSYNC, PCLK test points mentioned in the pin configuration table

MCLK - Signal description updated.

Updated information for CYUSB3064 part number: MIPI_D2P, MIPI_D2N,

MIPI_D3P, MIPI_D3N signals not available.

*I

4862446

RAGO

08/13/2015 Added footnote 1, and updated Pin Configuration (Figure 5) and Pin

Description (Table 6) to indicate grounding of unused MIPI lanes.

*J

4974015

5283275

RAGO

10/19/2015 Added More Information.

*K

05/24/2016 Updated to new template.

Completing Sunset Review.

Document Number: 001-87516 Rev. *L

Page 35 of 37

CYUSB306X

Document History Page (continued)

Document Title: CYUSB306X, EZ-USB^®CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller

Document Number: 001-87516

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*L

5464498

RAJA

06/22/2017 Updated Power:

Updated description.

Updated Operating Conditions:

Replaced “3.2 V” with “4 V” in Operating Conditions corresponding to “V

supply voltage”.

USB

Updated DC Specifications:

Changed minimum value of V

Added Errata.

parameter from 3.2 V to 4 V.

USB

Updated to new template.

Document Number: 001-87516 Rev. *L

Page 36 of 37

CYUSB306X

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

®

ARM Cortex Microcontrollers

Automotive

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

Lighting & Power Control

Memory

cypress.com/support

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-87516 Rev. *L

Revised June 22, 2017

Page 37 of 37

®

EZ-USB is a registered trademark of Cypress Semiconductor Corporation.

型号:	CYUSB3065-BZXC
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	CYPRESS SEMICONDUCTOR CORP
包装说明：	BGA-121
Reach Compliance Code：	compliant
ECCN代码：	3A991.A.3
HTS代码：	8542.31.00.01
Factory Lead Time：	1 week
风险等级：	1.68
Samacsys Description：	Cypress Semiconductor CYUSB3065-BZXC, USB Controller, 5Gbit/s, USB 3.0, 1.2 V, 121-Pin BGA
总线兼容性：	I2C
最大时钟频率：	40 MHz
JESD-30 代码：	S-PBGA-B121
长度：	10 mm
端子数量：	121
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA
封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	1.7 mm
最大供电电压：	1.25 V
最小供电电压：	1.15 V
标称供电电压：	1.2 V
表面贴装：	YES
技术：	CMOS
端子形式：	BALL
端子节距：	0.8 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches：	1

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