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产品型号D43256BGU的Datasheet PDF文件预览

DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD43256B  
256K-BIT CMOS STATIC RAM  
32K-WORD BY 8-BIT  
Description  
The µPD43256B is a high speed, low power, and 262, 144 bits (32,768 words by 8 bits) CMOS static RAM.  
Battery backup is available (L, LL, A, and B versions). And A and B versions are wide voltage operations.  
The µPD43256B is packed in 28-pin plastic DIP, 28-pin plastic SOP and 28-pin plastic TSOP (I).  
Features  
32,768 words by 8 bits organization  
Fast access time: 70, 85, 100, 120, 150 ns (MAX.)  
Wide voltage range (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)  
2 V data retention  
OE input for easy application  
Operating  
supply voltage  
V
Operating  
temperature  
°C  
Standby  
supply current  
µA (MAX.)  
Data retention  
supply currentNote 1  
µA (MAX.)  
Access time  
ns (MAX.)  
Part number  
µPD43256B-L  
µPD43256B-LL  
µPD43256B-A  
70, 85  
70, 85  
4.5 to 5.5  
0 to 70  
50  
15  
3
2
Note 2  
Note 2  
85, 100  
, 120  
3.0 to 5.5  
2.7 to 5.5  
Note 2  
µPD43256B-B  
100, 120, 150  
Notes 1. TA 40 ˚C, VCC = 3 V  
2. Access time : 85 ns (MAX.) (VCC = 4.5 to 5.5 V)  
Version X and P  
This data sheet can be applied to the version X and P. Each version is identified with its lot number. Letter X in  
the fifth character position in a lot number signifies version X, letter P, version P.  
JAPAN  
D43256B  
Lot number  
The information in this document is subject to change without notice.  
Document No. M10770EJ9V0DS00 (9th edition)  
Date Published May 1997 N  
The mark  
shows major revised points.  
Printed in Japan  
1990, 1993, 1994  
©
µPD43256B  
Ordering Information  
Operating  
supply voltage  
V
Operating  
temperature  
˚C  
Access time  
ns (MAX.)  
Part number  
Package  
Remark  
µPD43256BCZ-70L  
28-pin plastic  
DIP (600 mil)  
70  
85  
4.5 to 5.5  
0 to 70  
L Version  
µPD43256BCZ-85L  
µPD43256BCZ-70LL  
µPD43256BCZ-85LL  
µPD43256BGU-70L  
70  
LL Version  
L Version  
LL Version  
A Version  
85  
28-pin plastic  
SOP (450 mil)  
70  
µPD43256BGU-85L  
85  
µPD43256BGU-70LL  
µPD43256BGU-85LL  
µPD43256BGU-A85  
µPD43256BGU-A10  
µPD43256BGU-A12  
µPD43256BGU-B10  
µPD43256BGU-B12  
µPD43256BGU-B15  
µPD43256BGW-70LL-9JL  
µPD43256BGW-85LL-9JL  
µPD43256BGW-A85-9JL  
µPD43256BGW-A10-9JL  
µPD43256BGW-A12-9JL  
µPD43256BGW-B10-9JL  
µPD43256BGW-B12-9JL  
µPD43256BGW-B15-9JL  
70  
85  
85  
3.0 to 5.5  
2.7 to 5.5  
100  
120  
100  
120  
150  
70  
B Version  
28-pin plastic  
TSOP (I)  
4.5 to 5.5  
3.0 to 5.5  
LL Version  
A Version  
85  
(8 × 13.4 mm)  
(Normal bent)  
85  
100  
120  
100  
120  
150  
70  
2.7 to 5.5  
B Version  
µPD43256BGW-70LL-9KL 28-pin plastic  
4.5 to 5.5  
3.0 to 5.5  
LL Version  
A Version  
TSOP (I)  
µPD43256BGW-85LL-9KL  
(8 × 13.4 mm)  
µPD43256BGW-A85-9KL  
85  
85  
(Reverse bent)  
µPD43256BGW-A10-9KL  
µPD43256BGW-A12-9KL  
µPD43256BGW-B10-9KL  
µPD43256BGW-B12-9KL  
µPD43256BGW-B15-9KL  
100  
120  
100  
120  
150  
2.7 to 5.5  
B Version  
2
µPD43256B  
Pin Configuration (Marking Side)  
28-pin plastic DIP (600 mil)  
µPD43256BCZ  
28-pin plastic SOP (450 mil)  
µPD43256BGU  
A14  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
A12  
A7  
2
WE  
A13  
A8  
3
A6  
4
A5  
5
A9  
A4  
6
A11  
OE  
A3  
7
A2  
8
A10  
CS  
A1  
9
A0  
10  
11  
12  
13  
14  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
I/O1  
I/O2  
I/O3  
GND  
A0 - A14 : Address inputs  
I/O1 - I/O8 : Data inputs/outputs  
CS  
: Chip Select  
: Write Enable  
: Output Enable  
: Power supply  
: Ground  
WE  
OE  
VCC  
GND  
3
µPD43256B  
28-pin plastic TSOP (I) (8 × 13.4 mm)  
(Normal bent)  
µPD43256BGW-9JL  
OE  
A11  
A9  
A8  
A13  
WE  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A10  
CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
GND  
I/O3  
I/O2  
I/O1  
A0  
V
CC  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
9
10  
11  
12  
13  
14  
A1  
A2  
28-pin plastic TSOP (I) (8 × 13.4 mm)  
(Reverse bent)  
µPD43256BGW-9KL  
A10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
OE  
A11  
A9  
A8  
A13  
WE  
CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
GND  
I/O3  
I/O2  
I/O1  
A0  
V
CC  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A1  
A2  
4
µPD43256B  
Block Diagram  
A0  
|
A14  
Memory cell array  
262,144 bits  
I/O1  
|
I/O8  
Input data  
controller  
Output data  
controller  
Sense/Switch  
Column decoder  
Address buffer  
CS  
OE  
WE  
VCC  
GND  
Truth Table  
CS  
OE  
×
WE  
×
Mode  
I/O  
Supply current  
H
L
L
L
Not selected  
Output disable  
Write  
High impedance  
ISB  
H
×
H
ICCA  
L
DIN  
L
H
Read  
DOUT  
Remark ×: Don’t care  
5
µPD43256B  
Electrical Characteristics  
Absolute Maximum Ratings  
Parameter  
Supply voltage  
Symbol  
VCC  
VT  
Rating  
Unit  
V
Note  
–0.5  
to +7.0  
Note  
Input/Output voltage  
–0.5  
to VCC + 0.5  
0 to 70  
–55 to +125  
V
Operating ambient temperature  
Storage temperature  
TA  
˚C  
˚C  
Tstg  
Note –3.0 V (MIN.) (Pulse width 50 ns)  
Caution Exposing the device to stress above those listed in absolute maximum ratings could cause  
permanent damage. The device is not meant to be operated under conditions outside the  
limits described in the operational sections of this characteristics. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
Recommended Operating Conditions  
µPD43256B-L  
µPD43256B-A  
µPD43256B-B  
µPD43256B-LL  
Parameter  
Symbol  
Unit  
MIN.  
4.5  
MAX.  
5.5  
MIN.  
3.0  
MAX.  
5.5  
MIN.  
2.7  
MAX.  
5.5  
Supply voltage  
VCC  
VIH  
VIL  
TA  
V
V
High level input voltage  
2.2  
VCC + 0.5  
2.2  
VCC + 0.5  
2.2  
VCC + 0.5  
+0.5  
70  
Note  
Note  
Note  
Low level input voltage  
–0.3  
+0.8 –0.3  
70  
+0.5 –0.3  
70  
V
Operating ambient temperature  
0
0
0
˚C  
Note –3.0 V (MIN.) (Pulse width 50 ns)  
6
µPD43256B  
DC Characteristics (Recommended operating conditions unless otherwise noted) (1/2)  
µPD43256B-L  
µPD43256B-LL  
Parameter  
Symbol  
Test conditions  
Unit  
MIN. TYP. MAX. MIN. TYP. MAX.  
Input leakage current  
I/O leakage current  
ILI  
VIN = 0 V to VCC  
–1.0  
–1.0  
+1.0 –1.0  
+1.0 –1.0  
+1.0 µA  
+1.0 µA  
ILO  
VI/O = 0 V to VCC  
OE = VIH or CS = VIH or WE = VIL  
Operating supply current  
ICCA1  
CS = VIL, Minimum cycle time,  
II/O = 0 mA  
45  
45  
mA  
ICCA2  
ICCA3  
CS = VIL, II/O = 0 mA  
10  
10  
10  
10  
CS 0.2 V, Cycle = 1 MHz,  
II/O = 0 mA  
VIL 0.2 V, VIH VCC – 0.2 V  
Standby supply current  
High level output voltage  
Low level output voltage  
ISB  
ISB1  
CS = VIH  
3
3
mA  
µA  
V
CS VCC – 0.2 V  
IOH = –1.0 mA  
IOH = –0.1 mA  
IOL = 2.1 mA  
1.0  
50  
0.5  
15  
VOH1  
VOH2  
VOL  
2.4  
2.4  
VCC–0.5  
0.4  
VCC–0.5  
0.4  
V
Remarks 1. VIN: Input voltage  
2. These DC Characteristics are in common regardless of package types.  
7
µPD43256B  
DC Characteristics (Recommended operating conditions unless otherwise noted) (2/2)  
µPD43256B-A  
µPD43256B-B  
Parameter  
Symbol  
Test conditions  
Unit  
MIN. TYP. MAX. MIN. TYP. MAX.  
Input leakage current  
I/O leakage current  
ILI  
VIN = 0 V to VCC  
–1.0  
–1.0  
+1.0 –1.0  
+1.0 –1.0  
+1.0 µA  
+1.0 µA  
ILO  
VI/O = 0 V to VCC  
CS = VIH or WE = VIL or OE = VIH  
Operating supply current  
ICCA1  
CS = VIL,  
µPD43256B-A85  
45  
mA  
Minimum cycle time, µPD43256B-A10  
II/O = 0 mA  
µPD43256B-A12  
µPD43256B-B10  
µPD43256B-B12  
µPD43256B-B15  
45  
VCC 3.3 V  
10  
10  
20  
10  
5
ICCA2  
ICCA3  
CS = VIL, II/O = 0 mA  
VCC 3.3 V  
CS 0.2 V, Cycle = 1 MHz,  
II/O = 0 mA, VIL 0.2 V,  
10  
VIH VCC – 0.2 V  
VCC 3.3 V  
3
5
3
Standby supply current  
High level output voltage  
Low level output voltage  
ISB  
CS = VIH  
mA  
µA  
V
VCC 3.3 V  
2
ISB1  
CS VCC – 0.2 V  
0.5  
15  
0.5  
0.5  
15  
10  
VCC 3.3 V  
VOH1  
VOH2  
VOL  
IOH = –1.0 mA, VCC 4.5 V  
IOH = –0.5 mA, VCC < 4.5 V  
IOH = –0.1 mA  
2.4  
2.4  
2.4  
2.4  
IOH = –0.02 mA  
VCC–0.1  
VCC–0.1  
0.4  
0.4  
0.1  
IOL = 2.1 mA, VCC 4.5 V  
IOL = 1.0 mA, VCC < 4.5 V  
IOL = 0.02 mA  
0.4  
0.4  
0.1  
V
VOL1  
Remarks 1. VIN: Input voltage  
2. These DC characteristics are in common regardless of package types.  
Capacitance (TA = 25 ˚C, f = 1 MHz)  
Parameter  
Input capacitance  
Symbol  
CIN  
Test conditions  
MIN.  
TYP.  
MAX.  
Unit  
VIN = 0 V  
VI/O = 0 V  
5
8
pF  
pF  
Input/Output capacitance  
CI/O  
Remarks 1. VIN: Input voltage  
2. These parameters are periodically sampled and not 100 % tested.  
8
µPD43256B  
AC Characteristics (Recommended operating conditions unless otherwise noted)  
AC Test Conditions  
Input waveform (Rise/fall time 5 ns)  
Input pulse levels  
0.8 V to 2.2 V: µPD43256B-L, 43256B-LL  
0.5 V to 2.2 V: µPD43256B-A, 43256B-B  
Test points  
1.5 V  
1.5 V  
Output waveform  
Test points  
1.5 V  
1.5 V  
Output load  
µPD43256B-A, 43256B-B : 1TTL + 100 pF  
µPD43256B-L, 43256B-LL:  
AC characteristics with notes should be measured with the output load shown in  
Figure 1 and Figure 2.  
Figure 1  
Figure 2  
(For tAA, tACS, tOE, tOH)  
(For tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)  
+5 V  
+5 V  
1.8 kΩ  
1.8 kΩ  
I/O (Output)  
I/O (Output)  
990 Ω  
990 Ω  
100 pF  
5 pF  
CL  
C
L
Remark CL includes capacitances of the probe and jig, and stray capacitances.  
9
µPD43256B  
Read Cycle (1/2)  
VCC 4.5 V  
µPD43256B-85  
Parameter  
Symbol  
µPD43256B-70  
µPD43256B-A85/A10/A12  
µPD43256B-B10/B12/B15  
Unit Condition  
MIN.  
MAX.  
MIN.  
85  
MAX.  
Read cycle time  
tRC  
tAA  
70  
ns  
Address access time  
70  
70  
35  
85  
85  
40  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Note 1  
Note 2  
CS access time  
tACS  
tOE  
OE access time  
Output hold from address change  
CS to output in low impedance  
OE to output in low impedance  
CS to output in high impedance  
OE to output in high impedance  
tOH  
10  
10  
5
10  
10  
5
tCLZ  
tOLZ  
tCHZ  
tOHZ  
30  
30  
30  
30  
Notes 1. See the output load shown in Figure 1 except for µPD43256B-A, 43256B-B.  
2. See the output load shown in Figure 2 except for µPD43256B-A, 43256B-B.  
Remark These AC characteristics are in common regardless of package types and L, LL versions.  
Read Cycle (2/2)  
VCC 3.0 V  
VCC 2.7 V  
Con-  
Parameter  
Symbol µPD43256B-A85 µPD43256B-A10 µPD43256B-A12 µPD43256B-B10 µPD43256B-B12 µPD43256B-B15 Unit  
dition  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
Read cycle time  
tRC  
tAA  
85  
100  
120  
100  
120  
150  
ns  
Address access time  
85  
85  
50  
100  
100  
60  
120  
120  
60  
100  
100  
60  
120  
120  
60  
150 ns Note  
150 ns  
70 ns  
ns  
CS access time  
tACS  
tOE  
OE access time  
Output hold from address change  
CS to output in low impedance  
OE to output in low impedance  
CS to output in high impedance  
OE to output in high impedance  
tOH  
10  
10  
5
10  
10  
5
10  
10  
5
10  
10  
5
10  
10  
5
10  
10  
5
tCLZ  
tOLZ  
tCHZ  
tOHZ  
ns  
ns  
35  
35  
35  
35  
40  
40  
35  
35  
40  
40  
50 ns  
50 ns  
Note Loading condition is 1TTL + 100 pF.  
Remark These AC characteristics are in common regardless of package types and L, LL versions.  
10  
µPD43256B  
Read Cycle Timing Chart  
t
RC  
Address (Input)  
t
OH  
t
AA  
ACS  
t
CS (Input)  
OE (Input)  
I/O (Output)  
t
CLZ  
t
CHZ  
t
OE  
t
OHZ  
t
OLZ  
High impedance  
High impedance  
Data out  
Remark In read cycle, WE should be fixed to high level.  
11  
µPD43256B  
Write Cycle (1/2)  
VCC 4.5 V  
µPD43256B-85  
Parameter  
Symbol  
µPD43256B-70  
µPD43256B-A85/A10/A12  
µPD43256B-B10/B12/B15  
Unit Condition  
MIN.  
MAX.  
MIN.  
85  
70  
70  
60  
35  
0
MAX.  
Write cycle time  
tWC  
tCW  
tAW  
tWP  
tDW  
tDH  
70  
50  
50  
55  
30  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS to end of write  
Address valid to end of write  
Write pulse width  
Data valid to end of write  
Data hold time  
Address setup time  
tAS  
0
0
Write recovery time  
tWR  
tWHZ  
tOW  
0
0
WE to output in high impedance  
Output active from end of write  
30  
30  
ns  
ns  
Note  
10  
10  
Note See the output load shown in Figure 2 except for µPD43256B-A, 43256B-B.  
Remark These AC characteristics are in common regardless of package types and L, LL versions.  
Write Cycle (2/2)  
VCC 3.0 V  
VCC 2.7 V  
Con-  
Parameter  
Symbol µPD43256B-A85 µPD43256B-A10 µPD43256B-A12 µPD43256B-B10 µPD43256B-B12 µPD43256B-B15 Unit  
dition  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
Write cycle time  
tWC  
tCW  
tAW  
tWP  
tDW  
tDH  
85  
70  
70  
60  
60  
0
100  
70  
70  
60  
60  
0
120  
90  
90  
80  
70  
0
100  
70  
70  
60  
60  
0
120  
90  
90  
80  
70  
0
150  
100  
100  
90  
80  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS to end of write  
Address valid to end of write  
Write pulse width  
Data valid to end of write  
Data hold time  
Address setup time  
tAS  
0
0
0
0
0
0
Write recovery time  
tWR  
tWHZ  
tOW  
0
0
0
0
0
0
WE to output in high impedance  
Output active from end of write  
30  
35  
40  
35  
40  
50 ns Note  
10  
10  
10  
10  
10  
10  
ns  
Note Loading condition is 1TTL + 100 pF.  
Remark These AC characteristics are in common regardless of package types and L, LL versions.  
12  
µPD43256B  
Write Cycle Timing Chart 1 (WE Controlled)  
t
WC  
Address (Input)  
CS (Input)  
t
CW  
t
AW  
t
AS  
t
WP  
t
WR  
WE (Input)  
t
OW  
t
WHZ  
t
DW  
t
DH  
High  
High  
I/O (Input/Output)  
Indefinite data out  
Data in  
Indefinite data out  
impe-  
dance  
impe-  
dance  
Cautions 1. CS or WE should be fixed to high level during address transition.  
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite  
in phase with output signals.  
Remarks 1. Write operation is done during the overlap time of a low level CS and a low level WE.  
2. When WE is at low level, the I/O pins are always high impedance. When WE is at high level,  
read operation is executed. Therefore OE should be at high level to make the I/O pins high  
impedance.  
3. If CS changes to low level at the same time or after the change of WE to low level, the I/O pins  
will remain high impedance state.  
13  
µPD43256B  
Write Cycle Timing Chart 2 (CS Controlled)  
t
WC  
Address (Input)  
t
AS  
t
CW  
CS (Input)  
WE (Input)  
t
t
AW  
WP  
t
WR  
t
DW  
t
DH  
High impedance  
High  
impedance  
Data In  
I/O (Input)  
Cautions 1. CS or WE should be fixed to high level during address transition.  
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite  
in phase with output signals.  
Remark Write operation is done during the overlap time of a low level CS and a low level WE.  
14  
µPD43256B  
Low VCC Data Retention Characteristics  
L Version (µPD43256B-L: TA = 0 to 70 ˚C)  
Parameter  
Symbol  
Test conditions  
CS VCC – 0.2 V  
VCC = 3.0 V, CS VCC – 0.2 V  
MIN.  
2.0  
TYP.  
0.5  
MAX.  
5.5  
Unit  
V
Data retention supply voltage VCCDR  
Data retention supply current ICCDR  
Note  
20  
µA  
ns  
Chip deselection to data  
retention mode  
tCDR  
0
5
Operation recovery time  
tR  
ms  
Note 3 µA (TA 40 ˚C)  
LL Version (µPD43256B-LL: TA = 0 to 70 ˚C)  
A Version (µPD43256B-A: TA = 0 to 70 ˚C)  
B Version (µPD43256B-B: TA = 0 to 70 ˚C)  
Parameter  
Symbol  
Test conditions  
CS VCC – 0.2 V  
VCC = 3.0 V, CS VCC – 0.2 V  
MIN.  
2.0  
TYP.  
0.5  
MAX.  
5.5  
Unit  
V
Data retention supply voltage VCCDR  
Note  
Data retention supply current  
ICCDR  
tCDR  
7
µA  
ns  
Chip deselection to data  
retention mode  
0
5
Operation recovery time  
tR  
ms  
Note 2 µA (TA 40 ˚C), 1 µA (TA 25 ˚C)  
15  
µPD43256B  
Data Retention Timing Chart  
t
CDR  
Data retention mode  
tR  
5.0 V  
4.5 VNote  
VCC  
CS  
VIH (MIN.)  
VCCDR  
CS VCC – 0.2 V  
VIL (MAX.)  
GND  
Note A Version: 3.0 V, B Version: 2.7 V  
Remark The other pins (address, OE, WE, I/Os) can be in high impedance state.  
16  
µPD43256B  
Package Drawings  
28 PIN PLASTIC DIP (600 mil)  
28  
15  
1
14  
A
K
L
F
M
R
C
B
M
D
N
NOTES  
1) Each lead centerline is located within 0.25 mm (0.01 inch)  
of its true position (T.P.) at maximum material condition.  
ITEM MILLIMETERS  
INCHES  
1.500 MAX.  
0.100 MAX.  
0.100 (T.P.)  
+0.004  
A
B
C
38.10 MAX.  
2.54 MAX.  
2.54 (T.P.)  
2) Item "K" to center of leads when formed parallel.  
D
0.50±0.10  
0.020  
–0.005  
F
G
H
I
1.2 MIN.  
3.6±0.3  
0.047 MIN.  
0.142±0.012  
0.020 MIN.  
0.170 MAX.  
0.226 MAX.  
0.600 (T.P.)  
0.520  
0.51 MIN.  
4.31 MAX.  
5.72 MAX.  
15.24 (T.P.)  
13.2  
J
K
L
+0.10  
0.25  
+0.004  
0.010  
M
–0.05  
–0.003  
N
R
0.25  
0.01  
0 ~ 15°  
0 ~ 15°  
P28C-100-600A1-1  
17  
µPD43256B  
28 PIN PLASTIC SOP (450 mil)  
28  
15  
detail of lead end  
1
14  
A
H
I
J
N
C
B
L
M
D
M
NOTE  
ITEM MILLIMETERS  
INCHES  
Each lead centerline is located within 0.12 mm (0.005 inch) of  
its true position (T.P.) at maximum material condition.  
A
B
C
19.05 MAX.  
1.27 MAX.  
1.27 (T.P.)  
0.750 MAX.  
0.050 MAX.  
0.050 (T.P.)  
+0.004  
0.016  
D
0.40±0.10  
–0.005  
E
F
0.2±0.1  
0.008±0.004  
0.119 MAX.  
3.0 MAX.  
+0.005  
0.100  
G
H
2.55±0.1  
11.8±0.3  
–0.004  
+0.012  
0.465  
–0.013  
+0.004  
0.331  
I
8.4±0.1  
1.7±0.2  
–0.005  
J
K
0.067±0.008  
+0.07  
0.20  
+0.003  
0.008  
–0.03  
–0.002  
+0.008  
0.028  
L
0.7±0.2  
–0.009  
M
N
0.12  
0.10  
0.005  
0.004  
P
5°±5°  
5°±5°  
P28GU-50-450A-1  
18  
µPD43256B  
28PIN PLASTIC TSOP ( I ) (8×13.4)  
1
28  
detail of lead end  
S
R
Q
14  
15  
P
I
J
A
G
B
H
C
M
L
D
M
N
K
NOTE  
ITEM MILLIMETERS  
INCHES  
(1) Each lead centerline is located within 0.08 mm (0.003 inch) of  
its true position (T.P.) at maximum material condition.  
A
B
C
8.0±0.1  
0.315±0.004  
0.024 MAX.  
0.022 (T.P.)  
0.6 MAX.  
0.55 (T.P.)  
(2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.  
<0.331 inch MAX.>)  
+0.08  
0.22  
D
0.009±0.003  
–0.07  
1.0  
G
H
0.039  
12.4±0.2  
0.488±0.008  
+0.004  
0.465  
I
11.8±0.1  
0.8±0.2  
–0.005  
+0.009  
0.031  
J
K
L
–0.008  
+0.025  
0.145  
0.006±0.001  
–0.015  
+0.004  
0.020  
0.5±0.1  
–0.005  
M
N
0.08  
0.10  
0.003  
0.004  
+0.008  
0.528  
P
13.4±0.2  
–0.009  
Q
R
0.1±0.05  
0.004±0.002  
+7°  
3°  
+7°  
3°  
–3°  
–3°  
S
1.2 MAX.  
0.048 MAX.  
P28GW-55-9JL-1  
19  
µPD43256B  
28PIN PLASTIC TSOP ( I ) (8×13.4)  
1
28  
detail of lead end  
Q
R
S
14  
15  
K
M
M
D
N
L
J
C
H
B
G
A
I
P
NOTE  
ITEM MILLIMETERS  
INCHES  
(1) Each lead centerline is located within 0.08 mm (0.003 inch) of  
its true position (T.P.) at maximum material condition.  
A
B
C
8.0±0.1  
0.315±0.004  
0.024 MAX.  
0.022 (T.P.)  
0.6 MAX.  
0.55 (T.P.)  
(2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.  
<0.331 inch MAX.>)  
+0.08  
0.22  
D
0.009±0.003  
–0.07  
1.0  
G
H
0.039  
12.4±0.2  
0.488±0.008  
+0.004  
0.465  
I
11.8±0.1  
0.8±0.2  
–0.005  
+0.009  
0.031  
J
K
L
–0.008  
+0.025  
0.145  
0.006±0.001  
–0.015  
+0.004  
0.020  
0.5±0.1  
–0.005  
M
N
0.08  
0.10  
0.003  
0.004  
+0.008  
0.528  
P
13.4±0.2  
–0.009  
Q
R
0.1±0.05  
0.004±0.002  
+7°  
3°  
+7°  
3°  
–3°  
–3°  
S
1.2 MAX.  
0.048 MAX.  
P28GW-55-9KL-1  
20  
µPD43256B  
Recommended Soldering Conditions  
The following conditions (See table below) must be met when soldering µPD43256B. For more details, refer  
to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E).  
Please consult with our sales offices in case other soldering process is used, or in case soldering is done  
under different conditions.  
Types of Surface Mount Device  
µPD43256BGU: 28-pin plastic SOP (450 mil)  
µPD43256BGW-9JL: 28-pin plastic TSOP (I) (8 × 13.4 mm) (Normal bent)  
µPD43256BGW-9KL: 28-pin plastic TSOP (I) (8 × 13.4 mm) (Reverse bent)  
Please consult with our sales offices.  
Type of Through Hole Mount Device  
µPD43256BCZ: 28-pin plastic DIP (600 mil)  
Soldering process  
Soldering conditions  
Wave soldering  
(only to leads)  
Solder temperature: 260 ˚C or below,  
Flow time: 10 seconds or below  
Partial heating method  
Terminal temperature: 300 ˚C or below,  
Time: 3 seconds or below (Per one lead)  
Caution Do not jet molten solder on the surface of package.  
21  
µPD43256B  
[MEMO]  
22  
µPD43256B  
NOTES FOR CMOS DEVICES  
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS  
Note: Strong electric field, when exposed to a MOS device, can cause destruction  
of the gate oxide and ultimately degrade the device operation. Steps must  
be taken to stop generation of static electricity as much as possible, and  
quickly dissipate it once, when it has occurred. Environmental control must  
be adequate. When it is dry, humidifier should be used. It is recommended  
to avoid using insulators that easily build static electricity. Semiconductor  
devices must be stored and transported in an anti-static container, static  
shielding bag or conductive material. All test and measurement tools  
including work bench and floor should be grounded. The operator should  
be grounded using wrist strap. Semiconductor devices must not be touched  
with bare hands. Similar precautions need to be taken for PW boards with  
semiconductor devices on it.  
2 HANDLING OF UNUSED INPUT PINS FOR CMOS  
Note: No connection for CMOS device inputs can be cause of malfunction. If no  
connection is provided to the input pins, it is possible that an internal input  
level may be generated due to noise, etc., hence causing malfunction. CMOS  
device behave differently than Bipolar or NMOS devices. Input levels of  
CMOS devices must be fixed high or low by using a pull-up or pull-down  
circuitry. Each unused pin should be connected to VDD or GND with a  
resistor, if it is considered to have a possibility of being an output pin. All  
handling related to the unused pins must be judged device by device and  
related specifications governing the devices.  
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES  
Note: Power-on does not necessarily define initial status of MOS device. Produc-  
tion process of MOS does not define the initial operation status of the device.  
Immediately after the power source is turned ON, the devices with reset  
function have not yet been initialized. Hence, power-on does not guarantee  
out-pin levels, I/O settings or contents of registers. Device is not initialized  
until the reset signal is received. Reset operation must be executed imme-  
diately after power-on for devices having reset function.  
23  
µPD43256B  
[MEMO]  
No part of this document may be copied or reproduced in any form or by any means without the prior written  
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in  
this document.  
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property  
rights of third parties by or arising from use of a device described herein or any other liability arising from use  
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other  
intellectual property rights of NEC Corporation or others.  
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,  
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or  
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety  
measures in its design, such as redundancy, fire-containment, and anti-failure features.  
NEC devices are classified into the following three quality grades:  
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a  
customer designated "quality assurance program" for a specific application. The recommended applications of  
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device  
before using it in a particular application.  
Standard: Computers, office equipment, communications equipment, test and measurement equipment,  
audio and visual equipment, home electronic appliances, machine tools, personal electronic  
equipment and industrial robots  
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster  
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed  
for life support)  
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life  
support systems or medical equipment for life support, etc.  
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.  
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,  
they should contact an NEC sales representative in advance.  
Anti-radioactive design is not implemented in this product.  
M4 96.5  
配单直通车
D432F1001F产品参数
型号:D432F1001F
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:AMPHENOL FCI ASIA PTE LTD
Reach Compliance Code:compliant
风险等级:5.92
连接器类型:INTERCONNECTION DEVICE
Base Number Matches:1
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