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产品型号DA82562ET的概述

DA82562ET芯片概述 DA82562ET是一款高性能的以太网控制器，属于集成电路芯片家族，由达尔贝特（Daiwa）半导体公司设计和生产。该芯片广泛应用于多种网络应用领域，提供了可靠的网络连接解决方案，尤其适合嵌入式系统和工业自动化设备。DA82562ET具有高度集成的特点，其设计满足市场对低功耗、高速度和高稳定性的需求。 DA82562ET具备灵活的接口，能够支持多种数据传输协议，构成了其在网络通信应用中的核心竞争力。该芯片支持10/100 Mbps的以太网速度，能够适应大多数网络架构的需求。此外，DA82562ET还内置了多个功能模块，以简化设计并降低系统成本，包括快速发送和接收数据的缓冲区、DMA控制器、以及多种指示灯和节能功能。 DA82562ET的详细参数 DA82562ET的技术参数包括： - 供电电压：3.3V ± 10% - 工作温度范围：-40℃ 到 +85℃ -...

产品型号DA82562ET的Datasheet PDF文件预览

82562ET 10/100 Mbps Platform LAN

Connect (PLC)

Networking Silicon

Datasheet

Product Features

■ IEEE 802.3 10BASE-T/100BASE-TX

■ Diagnostic loopback mode

■ 1:1 transmit transformer ratio support

compliant physical layer interface

■ IEEE 802.3u Auto-Negotiation support

■ Digital Adaptive Equalization control

■ Link status interrupt capability

■ XOR tree mode support

■ Low power (less than 300 mW in active

transmit mode)

■ Reduced power in “unplugged mode” (less

than 50 mW)

■ Automatic detection of “unplugged mode”

■ 3.3 V device

■ 3-port LED support (speed, link and

activity)

■ 10BASE-T auto-polarity correction

■ LAN Connect Interface

■ 48-pin Shrink Small Outline Package

Revision 1.3

March 2003

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating

to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82562ET PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

* Other brands and names are the property of their respective owners.

Datasheet

Networking Silicon — 82562ET

Revision History

Revision

Revision Date

Description

1.3

1.2

March 2003

Added product ordering code in Section 1.0.

Removed confidential status.

October 2001

•

Removed sections: “Physical Layer Interface Functionality” and “Platform

LAN Connect”.

•

Changed “Electrical and Timing Specifications” section to “Voltage and Tem-

perature Specifications” and removed timing specifications.

1.1

1.0

June 2000

Advance Information Datasheet release (Intel Confidential).

•

On cover page, replaced Boundary Scan Support with XOR tree mode sup-

port. Added bullet for LAN Connect I/F.

•

Pg. 3, added a Solution Block Diagram as included in OR-2338 Pg. 4 but

replaced EM with ET in diagram.

•

Pg. 11, removed Figure 4, “NRZ to MLT-3 Encoding Diagram”.

Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0.

May 2000

Advance Information Datasheet release (Intel Secret).

•

Modified Table 1 “82562ET Hardware Configuration” to add one row for XOR

Tree and include column for comments.

•

Updated the descrition of the Activity LED signal in Section 3.6, “LED Pins”.

Revised Section 3.7, “Miscellaneous Control Pins” to reflect references to

Table 1 “82562ET Hardware Configuration”.

•

Updated Section 4.0, “Voltage and Temperature Specifications”.

Replaced diagrams in Section 5.1, “Package Information”.

0.6

Nov. 1999

Sept. 1999

•

Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect

correct signal transitions.

Removed “10BASE-T Error Detection and Reporting” section since the

82562 does not do 10BASE-T error reporting.

0.55

Initial release.

Datasheet

iii

82562ET — Networking Silicon

Datasheet

Networking Silicon — 82562ET

Contents

1.0

Introduction.........................................................................................................................1

1.1

1.2

1.3

Overview ...............................................................................................................1

Features ................................................................................................................1

References............................................................................................................1

2.0

3.0

82562ET Architectural Overview........................................................................................3

82562ET Signal Descriptions.............................................................................................5

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

Signal Type Definitions .........................................................................................5

Twisted Pair Ethernet (TPE) Pins .........................................................................5

External Bias Pins ................................................................................................5

Clock Pins ............................................................................................................6

Platform LAN Connect Interface Pins....................................................................6

LED Pins ..............................................................................................................7

Miscellaneous Control Pins ..................................................................................7

Power and Ground Connections ..........................................................................8

4.0

Voltage and Temperature Specifications ...........................................................................9

4.1

4.2

Absolute Maximum Ratings...................................................................................9

DC Characteristics ...............................................................................................9

4.2.1 X1 Clock DC Specifications .....................................................................9

4.2.2 LAN Connect Interface DC Specifications .............................................10

4.2.3 LED DC Specifications ..........................................................................10

4.2.4 10BASE-T Voltage and Current DC Specifications ...............................10

4.2.5 100BASE-TX Voltage and Current DC Specifications ..........................11

5.0

Package and Pinout Information ......................................................................................13

5.1

5.2

Package Information ...........................................................................................13

Pinout Information ...............................................................................................14

5.2.1 82562ET Pin Assignments ....................................................................14

5.2.2 82562ET Shrink Small Outlying Package Diagram ...............................15

Datasheet

82562ET — Networking Silicon

Datasheet

Networking Silicon — 82562ET

1.0

Introduction

1.1

Overview

The Intel^®82562ET is a highly-integrated Platform LAN Connect device designed for 10 or 100

Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE

802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded

twisted pair cable or Type 1 shielded twisted pair cable.

The 82562ET complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full

Duplex Flow Control standard. The 82563ET also includes a PHY interface compliant to the

current platform LAN connect interface.

1.2

Features

• IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface

• IEEE 802.3u Auto-Negotiation support

• Digital Adaptive Equalization control

• Link status interrupt capability

• XOR Tree mode support for board testing

• 3-port LED support (speed, link and activity)

• 10BASE-T auto-polarity correction

• Diagnostic loopback mode

• 1:1 transmit transformer ratio support

• Low power (less than 300 mW in active transmit mode)

• Reduced power in “unplugged mode” (less than 50 mW)

• Automatic detection of “unplugged mode”

• 3.3 V device

• 48-pin Shrink Small Outline Package

• Platform LAN connect interface support

1.3

References

• IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and

Electronics Engineers

• 82555 10/100 Mbps LAN Physical Layer Interface Datasheet, Intel Corporation

• LAN Connect Interface Specification, Intel Corporation

Datasheet

82562ET — Networking Silicon

1.4

Product Code

The product ordering code for the 82562ET is: DA82562ET.

Datasheet

Networking Silicon — 82562ET

2.0

82562ET Architectural Overview

The 82562ET is a highly integrated Platform LAN Connect device that combines a 10BASE-T and

100BASE-TX physical layer interfaces. The 82562ET supports a single interface fully compliant

with the IEEE 802.3 standard. Figure 1 provides a block diagram of the 82562ET architecture.

Figure 1. 82562ET Block Diagram

Digital

Equalizer

Adaptation

LILED

Port LED

Drivers

ACTLED

SPEEDLED

Equalizer &

BLW correction

Digital Clock

Recovery (100)

100Base-TX

PCS

RDN/RDP

LAN_RSTSYNC

LAN_TXD[2:0]

CRS/Link 10

Detection

Digital Clock

Recovery (10)

10Base-T

PCS

LAN

Connect

Interface

LAN_RXD[2:0]

LAN_CLK

Transmit DAC

10/100

TDN/ TDP

Auto-

Negotiation

Bias & Band-

Gap Voltage

Circuit

Clock

Generator

Control

Registers

Crystal

25 MHz

The 8252ET is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP). This document

describes the architecture of the device in all modes of operation.

Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test

Execute (ISOL_EX), define the general operation of the device. Table 1 shows the pin settings for

the different modes of operation.

Table 1. 82562ET Hardware Configuration

Mode of Operation

TESTEN

ISOL_TCK

ISOL_TI

ISOL_EX

Comments

Normal operating

mode

The ISOL_TCK, ISOL_TI,

and ISOL_EX pins can

remain floating.

Isolate mode

The device is in tri-state

and power-down mode.

(Tri-state and full

power-down mode)

The device is in tri-state

and the fully powered

down.

XOR Tree

The XOR Tree is used for

board testing and tri-state

mode.

NOTE: Combinations not shown in Table 1 are reserved and should not be used.

Datasheet

82562ET — Networking Silicon

Figure 2. 82562ET Solution Overview

VRM

Procesor

Clock

Termination

2 RIMM

Modules

MCH

IDE Primary

UltraDMA/33

IDE

PCI Control Bus

Secondary

ICH2

USB Port 1

USB Port 2

PCI Address/Data Bus

USB

AMC97

Audio/

Modem

AC97 Link

Control

Address/Data

82550 LAN

Controller

LPC Bus

SIO

82562ET

PLC

Keyboard

Mouse

Floppy

Parallel

Game Conn

Serial 1

Datasheet

Networking Silicon — 82562ET

3.0

82562ET Signal Descriptions

3.1

Signal Type Definitions

Type

Name

Description

Input

Output

Input pin to the 82562ET.

Output pin from the 82562ET.

I/O

Input/Output Multiplexed input and output pin to and from the 82562ET.

Multi-level

MLT

Multi-level analog pin used for input and output.

analog I/O

Bias pin used for ground connection through a resistor or an external voltage

reference.

Bias

Digital Power

DPS

APS

Digital power or ground pin for the 82562ET.

Supply

Analog Power

Analog power or ground pin for the 82562ET.

Supply

3.2

Twisted Pair Ethernet (TPE) Pins

Number

Pin Name

TDP

Type

MLT

Description

Transmit Differential Pair. The transmit differential pair sends serial bit

streams to the unshielded twisted pair (UTP) cable. The differential pair is

a two-level signal in 10BASE-T (Manchester) mode and a three-level

signal in 100BASE-TX mode (MLT-3). These signals directly interface with

the isolation transformer.

TDN

RDP

RDN

MLT

Receive Differential Pair. The receive differential pair receive the serial

bit stream from an unshielded twisted pair (UTP) cable. The differential

pair is a two-level signal in 10BASE-T mode (Manchester) or a three-level

signal in 100BASE-TX mode (MLT-3). These signals directly interface with

an isolation transformer.

3.3

External Bias Pins

Number

Pin Name

Type

Description

RBIAS10

Bias Reference Resistor 10. This pin should be connected to a 549 Ω

pull-down resistor.^a

RBIAS100

Bias reference Resistor 100. This pin should be connected to a 619 Ω

pull-down resistor.^b

a. 549 Ω for RBIAS10 is only a recommended value and should be fine tuned for various designs.

b. 619 Ω for RBIAS100 is only a recommended value and should be fine tuned for various designs.

Datasheet

82562ET — Networking Silicon

3.4

Clock Pins

Number

Pin Name

Type

Description

Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz

crystal of 50 PPM or better. Otherwise, X1 is driven by an external metal-

oxide semiconductor (MOS) level 25 MHz oscillator when X2 is left

floating.

Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz

crystal of 50 PPM or better.

3.5

Platform LAN Connect Interface Pins

Number

Pin Name

Type

Description

LAN_CLK

LAN Connect Clock. The LAN Connect Clock is driven by the 82562ET

on two frequencies depending on operation speed. When the 82562ET is

in 100BASE-TX mode, LAN_CLK drives a 50 MHz clock. Otherwise,

LAN_CLK drives a 5 MHz clock for 10BASE-T. The LAN_CLK does not

stop during normal operation.

LAN_

Reset/Synchronize. This is a multiplexed pin and is driven by the Media

Access Control (MAC) layer device. Its functions are:

RSTSYNC

•

Reset. When this pin is asserted beyond one LAN Connect clock

period, the 82562ET uses this signal Reset. To ensure reset of the

82562ET, the Reset signal should remain active for at least 500

µseconds.

•

Synchronize. When this pin is activated synchronously, for only one

LAN Connect clock period, it is used to synchronize the MAC and PHY

on LAN Connect word boundaries.

LAN_

45, 44,

LAN Connect Transmit Data. The LAN Connect transmit pins are used

to transfer data from the MAC device to the 82562ET. These pins are

used to move transmitted data and real time control and management

data. They also transmit out of band control data from the MAC to the

PHY. The pins should be fully synchronous to LAN_CLK.

TXD[2:0]

LAN_

37, 35,

LAN Connect Receive Data. The LAN Connect receive pins are used to

transfer data from the 82562ET to the MAC device. These pins are used

to move received data and real time control and management data. They

also move out of band control data from the PHY to the MAC. These pins

are synchronous to LAN_CLK.

RXD[2:0]

Datasheet

Networking Silicon — 82562ET

3.6

LED Pins

Number

Pin Name

Type

Description

LILED#

Link Integrity LED. The LED is active low and the Link Integrity LED pin

indicates link status in either 10BASE-T or 100BASE-TX mode. If a link is

present in either mode, the LILED is asserted.

ACTLED#

Activity LED. The LED is active low and the Activity LED signal indicates

either receive or transmit activity. When no activity is present, the LED is

off. The Activity LED will flicker when activity is present. The flicker rate

depends on the activity load.

The individual address LED control bit (Word A hexadecimal, bit 4) in the

ICH2 EEPROM can select the ACTLED# behavior. It controls the Activity

LED (ACTLED) functionality in Wake on LAN (WOL) mode.

0 = In WOL mode, the ACTLED is activated by the transmission and

reception of broadcast and individual address match packets.

1 = In WOL mode, the ACTLED is activated by the transmission and

reception of individual address match packets only.

This bit is configured by the OEM and is activated by a transmission and

reception of individual address match packets.

SPDLED#

Speed LED. The LED is active low and the Speed LED signal indicates

the speed of operation, either 10 Mbps or 100 Mbps. The Speed LED is

on during 100BASE-TX operation and off in 10BASE-T mode.

3.7

Miscellaneous Control Pins

Number

Pin Name

ADV10

Type

Description

Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted

high, and the 82562ET advertises only 10BASE-T technology during

Auto-Negotiation processes in this state. Otherwise, the 82562ET

advertises all of its technologies.

Note: ADV10 has an internal pull-down resistor.

ISOL_TCK

ISOL_TI

Test Clock. The Test Clock signal sets the device into asynchronous test

mode in conjunction with the Test Input, Test Execute and Test Enable

pins (refer to Table 1).

In the manufacturing test mode, it acts as the test clock.

Note: ISOL_TCK has an internal pull-down resistor.

Test Input. The Test Input signal sets the device into asynchronous test

mode in conjunction with the Test Clock, Test Execute and Test Enable

pins (refer to Table 1).

In the manufacturing test mode, it acts as the test data input pin.

Note: ISOL_TI has an internal pull-down resistor.

Datasheet

82562ET — Networking Silicon

Number

Pin Name

Type

Description

ISOL_TEX

Test Execute. The Test Execute signal sets the device into asynchronous

test mode in conjunction with the Test Clock, Test Input, and Test Enable

pins (refer to Table 1).

In the manufacturing test mode, it places the command that was entered

through the TI pin in the instruction register.

Note: ISOL_TEX has an internal pull-down resistor.

TOUT

Test Output. The Test Output pin is used for Boundary XOR scan output.

In the manufacturing test mode, it acts as the test output port.

TESTEN

Test Enable. The Test Enable pin is used to enable test mode and should

be pulled down to V_SSto allow XOR Tree test mode.

3.8

Power and Ground Connections

Number

Pin Name

VCC

Type

DPS

Description

1, 25

36, 40

Digital 3.3 V Power. These pins should be connected to the main digital

power supply.

VCCP

VCCA

VCCA2

VCCT

9, 12,

14, 17

VSS

8, 13, 18 DPS

Digital Ground. These pins should be connected to the main digital

ground.

24, 48

VSSP

VSSA

VSSA2

33, 38

VCCR

VSSR

19, 23

20, 22

APS

Analog Power.

Analog Ground. These pins should not be isolated from the main digital.

Datasheet

Networking Silicon — 82562ET

4.0

Voltage and Temperature Specifications

4.1

Absolute Maximum Ratings

Maximum ratings are listed below:

Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 135 C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 150 C

Supply Voltage with respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.45 V

Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 3.45 V

Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to 3.45 V

Stresses above the listed absolute maximum ratings may cause permanent damage to the 82562ET

device. This is a stress rating only and functional operations of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

4.2

DC Characteristics

Table 2. General DC Specifications

Symbol

V_CC

Parameter

Supply Voltage

Condition

Min

Typical

Max

Units

Notes

3.0

3.3

3.45

Minimum/MaximumCase

Temperature

10/100Mbps (transmitter

on)

300

Power

Consumption

Reduced Power

Auto-Negotiation

200

4.2.1

X1 Clock DC Specifications

Table 3. X1 Clock DC Specifications

Symbol

V_IL

Parameter

Condition

Min

Typical

Max

Units

Notes

Input Low Voltage

0.8

Input High

Voltage

V_IH

I_ILIH

C_I

2.0

Input Leakage

Currents

0 < V_IN< V_CC

±10

µA

Input

Capacitance

NOTES:

1. This characteristic is only characterized, not tested. It is valid for digital pins only.

Datasheet

82562ET — Networking Silicon

4.2.2

LAN Connect Interface DC Specifications

Table 4. LAN Connect Interface DC Specifications

Symbol

V_CCJ

Parameter

Condition

Min

Typical

Max

Units

Notes

Input/Output

Supply Voltage

3.0

-0.5

3.45

V_IL

V_IH

Input Low Voltage

0.3V_CCJ

Input High

Voltage

V_CCJ

0.5

0.6V_CCJ

Input Leakage

Current

I_IL

0 < V_IN< V_CCJ

±10

µA

Output Low

Voltage

V_OL

V_OH

C_IN

_OUT= 1500 µA

_OUT= -500 µA

0.1V_CCJ

Output High

Voltage

0.9V_CCJ

Input Pin

Capacitance

NOTES:

1. This characteristic is only characterized, not tested. It is valid for digital pins only.

4.2.3

LED DC Specifications

Table 5. LED DC Specifications

Symbol

V_OLLED

V_OHLED

Parameter

Condition

_OUT= 10 mA

_OUT= -10 mA

Min

Typical

Max

Units

Notes

Output Low

Voltage

0.7

Output High

Voltage

2.4

4.2.4

10BASE-T Voltage and Current DC Specifications

Table 6. 10BASE-T Transmitter

Symbol

V_OD10

Parameter

Condition

R_L= 100 Ω

Min

Typical

Max

Units

Notes

OutputDifferential

Peak Voltage

2.2

2.8

NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V.

1. R_Lis the resistive load measured across the transmit differential pins, TDP and TDN.

Datasheet

Networking Silicon — 82562ET

Table 7. 10BASE-T Receiver

Symbol

R_ID10

Parameter

Condition

Min

Typical

Max

Units

Notes

Input Differential

Resistance

KΩ

Input Differential

Accept Peak

Voltage

V_IDA10

5 MHz ≤ f ≤ 10 MHz

585

3100

300

Input Differential

Reject Peak

Voltage

V_IDR10

Input Common

Mode Voltage

V_ICM10

V_CC/2

NOTES:

1. The input differential resistance is measured across the receive differential pins, RDP and RDN.

4.2.5

100BASE-TX Voltage and Current DC Specifications

Table 8. 100BASE-TX Transmitter

Symbol

V_OD100

Parameter

Condition

R_L= 100 Ω

Min

Typical

Max

Units

Notes

OutputDifferential

Peak Voltage

0.95

1.0

1.05

NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V.

1. R_Lis the resistive load measured across the transmit differential pins, TDP and TDN.

Table 9. 100BASE-TX Receiver

Symbol

Parameter

Condition

Min

Typical

Max

Units

Notes

Input Differential

Resistance

R_ID100

KΩ

Input Differential

Accept Peak

Voltage

V_IDA100

500

1200

100

Input Differential

Reject Peak

Voltage

V_IDR100

Input Common

Mode Voltage

V_ICM100

V_CC/2

NOTES:

1. The input differential resistance is measured across the receive differential pins, RDP and RDN.

Datasheet

82562ET — Networking Silicon

Datasheet

Networking Silicon — 82562ET

5.0

Package and Pinout Information

5.1

Package Information

The 82562ET is a 48-pin Shrink Small Outlying Package (SSOP). The Package dimensions are

shown in Figure 3. More information on Intel device packaging is available in the Intel Packaging

Handbook, which is available from the Intel Literature Center or your local sales office.

Figure 3. Dimension Diagram for the 82562ET 48-pin SSOP

Datasheet

82562ET — Networking Silicon

5.2

Pinout Information

5.2.1

82562ET Pin Assignments

Table 10. 82562ET Pin Assignments

Number

Pin Name

VCC

VCCA

VSSA

VSS

VCCT

RDP

VCC

TOUT

LAN_RXD2

VSSP

LILED

LAN_CLK

VCCP

RBIAS10

RBIAS100

VSSA2

VCCA2

VSS

RDN

ISOL_TI

ISOL_TEX

ISOL_TCK

SPDLED

ACTLED

VSSP

VCCT

VSS

ADV10

LAN_RSTSYNC

LAN_TXD0

LAN_TXD1

LAN_TXD2

VCCR

VSSR

TESTEN

VSSR

VCCR

VSS

VCCT

TDP

LAN_RXD0

LAN_RXD1

VCCP

TDN

VCCT

VSS

Datasheet

Networking Silicon — 82562ET

5.2.2

82562ET Shrink Small Outlying Package Diagram

Figure 4. 82562ET Pin Out Diagram

VCC (DPS)

VCCA (APS)

VSSA (APS)

RBIAS10 (B)

RBIAS100 (B)

VSSA2 (APS)

VCCA2 (APS)

VSS (DPS)

X2 (O)

X1(I)

LAN_TXD2 (I)

LAN_TXD1 (I)

LAN_TXD0 (I)

LAN_RSTSYNC

ADV10 (I)

VSS (DPS)

VCCT (APS)

VCCP (DPS)

LAN_CLK (O)

VSSP (DPS)

LAN_RXD2 (O)

VCCP (DPS)

LAN_RXD1 (O)

LAN_RXD0 (O)

VSSP (DPS)

ACTLED# (O)

SPDLED# (O)

ISOL_TCK (I)

ISOL_TEX (I)

ISOL_TI (I)

TDP (MLT)

TDN (MLT)

VCCT (APS)

VSS (DPS)

VCCT (APS)

RDP (MLT)

RDN (MLT)

VCCT (APS)

82562ET

PIN DIAGRAM

SSOP48

Rev 1.0

Top View

VSS (DPS)

VCCR (APS)

VSSR (APS)

TESTEN (I)

VSSR (APS)

VCCR (APS)

LILED# (O)

TOUT (O)

VSS (DPS)

VCC (DPS)

Datasheet

DA82562ET相关文章

配单直通车

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

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深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

电子百科

产品导航

产品型号DA82562ET的概述

产品型号DA82562ET的Datasheet PDF文件预览

DA82562ET相关产品

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