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产品型号DAC121S101WGRQV的概述

DAC121S101WGRQV 概述 DAC121S101WGRQV 是一款高精度、低功耗的数模转换器 (DAC),由德州仪器(Texas Instruments)公司生产,专为需要高分辨率和小信号输出的应用而设计。作为一款 12 位的DAC,DAC121S101WGRQV 提供完美的线性度和输出稳定性,适合在各种电子系统中实现精确的电压输出。 该 DAC 使用 SPI (Serial Peripheral Interface) 进行通信,使得它在数据传输中具备高速和灵活性,它能够在较短的时间内处理和转换来自数字信号的数据。DAC121S101WGRQV 的应用包括工业控制、医疗设备、音频设备以及通信系统等领域。 详细参数 DAC121S101WGRQV 的主要参数如下: - 分辨率:12-bit - 输出范围:0V 到 VREF(VREF 通常为 2.5V 或 5V,具体取决于电路的...

产品型号DAC121S101WGRQV的Datasheet PDF文件预览

May 6, 2010  
DAC121S101QML  
12-Bit Micro Power Digital-to-Analog Converter with Rail-  
to-Rail Output  
General Description  
Features  
The DAC121S101 is a full-featured, general purpose 12-bit  
voltage-output digital-to-analog converter (DAC) that can op-  
erate from a single +2.7 V to 5.5 V supply and consumes just  
177 µA of current at 3.6 V. The on-chip output amplifier allows  
rail-to-rail output swing and the three wire serial interface op-  
erates at clock rates up to 20 MHz over the specified supply  
voltage range and is compatible with standard SPI, QSPI,  
MICROWIRE and DSP interfaces.  
Total Ionizing Dose  
100 krad(Si)  
120 MeV-cm2/mg  
Single Event Latch-up  
Guaranteed Monotonicity  
Low Power Operation  
Rail-to-Rail Voltage Output  
Power-on Reset to Zero Volts Output  
SYNC Interrupt Facility  
The supply voltage for the DAC121S101 serves as its voltage  
reference, providing the widest possible output dynamic  
range. A power-on reset circuit ensures that the DAC output  
powers up to zero volts and remains there until there is a valid  
write to the device. A power-down feature reduces power  
consumption to less than a microWatt.  
Wide power supply range (+2.7 V to +5.5 V)  
Small Packages  
Power Down Feature  
Key Specifications  
The low power consumption and small packages of the  
DAC121S101 make it an excellent choice for use in battery  
operated equipment.  
Resolution  
DNL  
Output Settling Time  
Zero Code Error  
12 bits  
+0.21, -0.10 LSB (typ)  
12.5 µs (typ)  
The DAC121S101 operates over the extended temperature  
range of -55°C to +125°C.  
2.1 mV (typ)  
−0.04 %FS (typ)  
Full-Scale Error  
Power Dissipation  
Normal Mode 0.52 mW (3.6 V) / 1.19 mW (5.5 V) typ  
Pwr Down  
Mode  
0.014 µW (3.6 V) / 0.033 µW (5.5 V) typ  
Applications  
Battery-Powered Instruments  
Digital Gain and Offset Adjustment  
Programmable Voltage & Current Sources  
Programmable Attenuators  
Ordering Information  
NS Part Number  
SMD Part Number  
NS Package Number  
Package Discription  
DAC121S101WGRQV  
Flight Part  
5962R0722601VZA  
100 krad(Si)  
WG10A  
10LD Ceramic SOIC  
10LD Ceramic SOIC  
DAC121S101WGMPR  
Pre-flight Prototype  
WG10A  
DAC121S101CVAL  
Ceramic Evaluation Board  
10LD Ceramic SOIC  
on Evaluation Board  
SPIis a trademark of Motorola, Inc.  
© 2010 National Semiconductor Corporation  
300180  
www.national.com  
Connection Diagrams  
10LD Ceramic SOIC  
30018001  
Top View  
See NS Package Number WG10A  
Block Diagram  
30018003  
www.national.com  
2
Absolute Maximum Ratings  
(Note 1, Note 2)  
Operating Ratings (Note 1, Note 2)  
Operating Temperature Range  
−55°C to +125°C  
Supply Voltage, VA  
+2.7 V to 5.5 V  
−0.1 V to (VA + 0.1 V)  
0 to 1500 pF  
Supply Voltage, VA  
6.5 V  
Any Input Voltage (Note 6)  
Output Load  
SCLK Frequency  
Voltage on any Input Pin  
−0.3 V to (VA + 0.3 V)  
10 mA  
Input Current at Any Pin (Note 3)  
Maximum Output Current (Note 10)  
VOUT Pin in Powerdown Mode  
Package Input Current (Note 3)  
Power Dissipation at TA = 25°C  
Maximum Junction Temperature  
Lead Temperature  
Up to 20 MHz  
10 mA  
1.0 mA  
20 mA  
Package Thermal Resistance  
θJA  
Package  
θJC  
See (Note 4)  
175°C  
(Still Air)  
10-lead Ceramic SOIC  
Package on 2 layer, 1oz.  
PCB  
214°C/W  
25.7°C/W  
Ceramic SOIC  
(Soldering 10 Seconds)  
260°C  
Storage Temperature  
Package Weight (Typical)  
Ceramic SOIC  
−65°C to +150°C  
220 mg  
ESD Tolerance (Note 5)  
Class 3A (5000 V)  
Quality Conformance Inspection  
MIL-STD-883, Method 5005 - Group A  
Subgroup  
Description  
Temp (° C)  
1
2
Static tests at  
Static tests at  
+25  
+125  
-55  
3
Static tests at  
4
Dynamic tests at  
Dynamic tests at  
Dynamic tests at  
Functional tests at  
Functional tests at  
Functional tests at  
Switching tests at  
Switching tests at  
Switching tests at  
Setting time at  
+25  
+125  
-55  
5
6
7
+25  
+125  
-55  
8A  
8B  
9
+25  
+125  
-55  
10  
11  
12  
13  
14  
+25  
+125  
-55  
Setting time at  
Setting time at  
3
www.national.com  
DAC121S101 Electrical Characteristics  
DC Parameters  
The following specifications apply for VA = +2.7 V to +5.5 V, RL = , CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to  
4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25°C, unless otherwise specified.  
Typical  
(Note 8)  
Sub-  
groups  
Symbol  
Parameter  
Conditions  
Notes  
Min  
Max  
Units  
STATIC PERFORMANCE  
Resolution  
(Note 9)  
(Note 9)  
12  
12  
Bits  
Bits  
LSB  
LSB  
LSB  
mV  
Monotonicity  
INL  
Integral Non-Linearity  
Over Decimal codes 48 to 4047  
VA = 2.7 V to 5.5 V  
±2.75  
+0.21  
−0.10  
+2.12  
−0.04  
−0.11  
−20  
−8.0  
8.0  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
+1.0  
DNL  
Differential Non-Linearity  
−0.7  
IOUT = 0  
ZE  
FSE  
GE  
Zero Code Error  
Full-Scale Error  
Gain Error  
+15  
IOUT = 0  
−1.0 %FSR  
±1.0 %FSR  
µV/°C  
All ones Loaded to DAC register  
ZCED  
Zero Code Error Drift  
(Note 9)  
(Note 9)  
VA = 3 V  
VA = 5 V  
−0.7  
ppm/°C  
TC GE Gain Error Tempco  
−1.0  
ppm/°C  
OUTPUT CHARACTERISTICS  
Vout Pin in Powerdown  
IPD SINK  
Mode  
All PD Modes  
(Note 9)  
(Note 9)  
1.0  
mA  
VA  
6
Output Voltage Range  
0
V
mV  
mV  
mV  
mV  
V
VA = 3 V, IOUT = 10 µA  
VA = 3 V, IOUT = 100 µA  
VA = 5 V, IOUT = 10 µA  
VA = 5 V, IOUT = 100 µA  
VA = 3 V, IOUT = 10 µA  
VA = 3 V, IOUT = 100 µA  
VA = 5 V, IOUT = 10 µA  
VA = 5 V, IOUT = 100 µA  
2.0  
4
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
10  
8
ZCO  
FSO  
Zero Code Output  
Full Scale Output  
2
4
9
2.997  
2.991  
4.994  
4.992  
1500  
2.990  
2.985  
4.985  
4.985  
V
V
V
pF  
RL = ∞  
RL = 2 kΩ  
Maximum Load Capacitance  
DC Output Impedance  
(Note 9)  
1500  
8
pF  
16  
1, 2, 3  
www.national.com  
4
DC Parameters (Continued)  
The following specifications apply for VA = +2.7 V to +5.5 V, RL = , CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to  
4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25°C, unless otherwise specified.  
Typical  
(Note 8)  
Sub-  
groups  
Symbol  
Parameter  
Conditions  
Notes  
Min Max  
Units  
LOGIC INPUT  
IIN  
Input Current  
6
−200 +200  
nA  
V
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
VA = 5 V  
VA = 3 V  
VA = 5 V  
VA = 3 V  
0.8  
0.5  
VIL  
Input Low Voltage  
V
2.4  
V
VIH  
CIN  
Input High Voltage  
Input Capacitance  
2.1  
V
(Note 9)  
5
pF  
POWER REQUIREMENTS  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
216  
145  
185  
132  
150  
115  
22  
270  
200  
230  
175  
190  
160  
60  
µA  
µA  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
Normal Mode  
fSCLK = 20 MHz  
µA  
Normal Mode  
fSCLK = 10 MHz  
µA  
µA  
Normal Mode  
fSCLK = 0  
µA  
Supply Current (output  
unloaded)  
IA  
µA  
All PD Modes,  
fSCLK = 20 MHz  
12  
30  
µA  
12  
40  
µA  
All PD Modes,  
fSCLK = 10 MHz  
6
20  
µA  
.006  
.004  
1.19  
0.52  
1.02  
0.47  
0.82  
0.41  
0.12  
0.07  
0.04  
0.02  
0.033  
0.014  
91  
1.0  
1.0  
1.49  
.72  
1.27  
.63  
1.05  
.58  
.33  
.11  
.22  
.08  
5.5  
3.6  
µA  
All PD Modes,  
fSCLK = 0  
µA  
mW  
mW  
mW  
mW  
mW  
mW  
mW  
mW  
mW  
mW  
µW  
µW  
%
Normal Mode  
fSCLK = 20 MHz  
(Note 9)  
(Note 9)  
(Note 9)  
(Note 9)  
(Note 9)  
(Note 9)  
(Note 9)  
Normal Mode  
fSCLK = 10 MHz  
Normal Mode  
fSCLK = 0  
Power Consumption (output  
unloaded)  
PC  
All PD Modes,  
fSCLK = 20 MHz  
All PD Modes,  
fSCLK = 10 MHz  
All PD Modes,  
fSCLK = 0  
IOUT / IA  
ILOAD = 2 mA  
Power Efficiency  
94  
%
5
www.national.com  
AC and Timing Characteristics  
The following specifications apply for VA = +2.7 V to +5.5 V, RL = , CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to  
4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25°C, unless otherwise specified.  
Typical  
(Note 8)  
Sub-  
groups  
Symbol  
Parameter  
Conductions  
Notes  
Min Max Units  
(Note  
9)  
fSCLK  
SCLK Frequency  
(See Figure 2)  
20  
MHz 9, 10, 11  
FF0 to 00F code  
12.5  
12.5  
12.5  
12.5  
15  
15  
15  
15  
µs  
µs  
µs  
µs  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
CL 200 pF  
CL = 500 pF  
change, RL = ∞  
ts  
Output Voltage Settling Time  
00Fh to FF0h code  
CL 200 pF  
CL = 500 pF  
change, RL = ∞  
(Note  
9)  
SR  
Output Slew Rate  
Glitch Impulse  
1
V/µs  
(Note  
9)  
Code change from 800h to 7FFh  
12  
0.5  
nV-sec  
nV-sec  
(Note  
9)  
Digital Feedthrough  
VA = 5 V  
.65  
1.1  
µs  
µs  
ns  
ns  
ns  
(Note  
9)  
tWU  
Wake-Up Time  
VA = 3 V  
1/fSCLK  
SCLK Cycle Time  
SCLK High time  
SCLK Low Time  
(See Figure 2)  
(See Figure 2)  
(See Figure 2)  
50  
20  
20  
9, 10, 11  
9, 10, 11  
9, 10, 11  
tH  
tL  
Set-up Time SYNC to SCLK  
Rising Edge  
tSUCL  
(See Figure 2)  
0
ns  
9, 10, 11  
tSUD  
tDHD  
Data Set-Up Time  
Data Hold Time  
(See Figure 2)  
6
ns  
ns  
ns  
ns  
ns  
ns  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
(See Figure 2)  
4.5  
10  
18  
37  
36  
VA = 5.5 V (See Figure 2)  
VA = 2.7 V (See Figure 2)  
VA = 5.5 V (See Figure 2)  
VA = 2.7 V (See Figure 2)  
tCS  
SCLK fall to rise of SYNC  
SYNC High Time  
tSYNC  
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6
Radiation Electrical Characteristics  
(Note 12)  
The following specifications apply for VA = +2.7 V to +5.5 V, RL = , CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to  
4047.  
Sub-  
groups  
Symbol  
Parameter  
Conditions  
Min  
Max  
Units  
POWER REQUIREMENTS  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
5.5 V  
3.6 V  
325  
250  
300  
225  
275  
200  
125  
100  
115  
95  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
1
1
1
1
1
1
1
1
1
1
1
1
Normal Mode  
fSCLK = 20 MHz  
Normal Mode  
fSCLK = 10 MHz  
Normal Mode  
fSCLK = 0  
IA  
Supply Current (output unloaded)  
All PD Modes,  
fSCLK = 20 MHz  
All PD Modes,  
fSCLK = 10 MHz  
100  
100  
All PD Modes,  
fSCLK = 0  
Operating Life Test Delta Parameters TA @ 25°C  
(Note 11)  
Symbol  
INL  
Parameter  
Integral non-linearity  
Conditions  
Min  
Max  
±2  
Units  
LBS  
µA  
ts  
Output voltage settling time  
±5  
Normal Mode, VA = 5.5V fSCLK = 20 MHz  
Normal Mode, VA = 3.6V fSCLK = 20 MHz  
Normal Mode, VA = 5.5V fSCLK = 10 MHz  
Normal Mode, VA = 3.6V fSCLK = 10 MHz  
Normal Mode, VA = 5.5V fSCLK = 0  
±10  
±6  
µA  
µA  
±10  
±6  
µA  
µA  
±8  
µA  
Normal Mode, VA = 3.6V fSCLK = 0  
±6  
µA  
IA  
Supply Current (output unloaded)  
All PD Modes, VA = 5.5V fSCLK = 20 MHz  
All PD Modes, VA = 3.6V fSCLK = 20 MHz  
All PD Modes, VA = 5.5V fSCLK = 10 MHz  
All PD Modes, VA = 3.6V fSCLK = 10 MHz  
All PD Modes, VA = 5.5V fSCLK = 0  
±2  
µA  
±1  
µA  
±1  
µA  
±1  
µA  
±0.1  
±0.1  
µA  
All PD Modes, VA = 3.6V fSCLK = 0  
µA  
7
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed  
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test  
conditions.  
Note 2: All voltages are measured with respect to GND = 0 V, unless otherwise specified  
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should be limited to 10  
mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.  
Note 4: The absolute maximum junction temperature (TJmax) for this device is 175°C. The maximum allowable power dissipation is dictated by TJmax, the  
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values  
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond  
the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.  
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kresistor. Machine model is 220 pF discharged through ZERO Ohms.  
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.  
However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VA is 2.7 VDC, ensure that  
−100 mV input voltages 2.8 VDC to ensure accurate conversions.  
30018004  
Note 7: To guarantee accuracy, it is required that VA be well bypassed.  
Note 8: Typical figures are at TJ = 25°C, and represent most likely parametric norms.  
Note 9: This parameter is guaranteed by design and/or characterization and is not tested in production.  
Note 10: Maximum Output Current may not exceed 10 mA. At VDD = 5.5 V the minimum external resistive load can be no less than 550 Ω, (360 Ω at VDD = 3.6  
V).  
Note 11: These parameters are worse case drift. Deltas are performed at room temperature Post OP Life. All other parameters no Deltas are required.  
Note 12: Pre and post irradiation limits are identical to those listed in the “DC Parameters” and “AC and Timing Characteristics” tables, except as listed in the  
“Radiation Electrical Characteristics” table. When performing post irradiation electrical measurements for any RHA level, TA = +25°C. See section 3.0 for dose  
rate and test conditions.  
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8
MAXIMUM LOAD CAPACITANCE is the maximum capaci-  
tance that can be driven by the DAC with output stability  
maintained.  
Specification Definitions  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of  
the maximum deviation from the ideal step size of 1 LSB,  
which is VREF / 4096 = VA / 4096.  
MONOTONICITY is the condition of being monotonic, where  
the DAC has an output that never decreases when the input  
code increases.  
DIGITAL FEEDTHROUGH is a measure of the energy inject-  
ed into the analog output of the DAC from the digital inputs  
when the DAC outputs are not updated. It is measured with a  
full-scale code change on the data bus.  
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest  
value or weight of all bits in a word. Its value is 1/2 of VA.  
POWER EFFICIENCY is the ratio of the output current to the  
total supply current. The output current comes from the power  
supply. The difference between the supply and output cur-  
rents is the power consumed by the device without a load.  
FULL-SCALE ERROR is the difference between the actual  
output voltage with a full scale code (FFFh) loaded into the  
DAC and the value of VA x 4095 / 4096.  
GAIN ERROR is the deviation from the ideal slope of the  
transfer function. It can be calculated from Zero and Full-  
Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE  
is Full-Scale Error and ZE is Zero Error.  
SETTLING TIME is the time for the output to settle to within  
1/2 LSB of the final value after the input code is updated.  
WAKE-UP TIME is the time for the output to exit power-down  
mode. This is the time measured from the falling edge of 16th  
SCLK pulse to when the output voltage deviates from the  
power-down voltage of 0 V.  
GLITCH IMPULSE is the energy injected into the analog out-  
put when the input code to the DAC register changes. It is  
specified as the area of the glitch in nanovolt-seconds.  
ZERO CODE ERROR is the output error, or voltage, present  
at the DAC output after a code of 000h has been entered.  
INTEGRAL NON-LINEARITY (INL) is a measure of the de-  
viation of each individual code from a straight line through the  
input to output transfer function. The deviation of any given  
code from this straight line is measured from the center of that  
code value. The end point method is used. INL for this product  
is specified over a limited range, per the Electrical Tables.  
LEAST SIGNIFICANT BIT (LSB) is the bit that has the small-  
est value or weight of all bits in a word. This value is  
LSB = VREF / 2n  
where VREF is the supply voltage for this product, and "n" is  
the DAC resolution in bits, which is 12 for the DAC121S101.  
9
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Transfer Characteristic  
30018005  
FIGURE 1. Input / Output Transfer Characteristic  
Timing Diagram  
30018006  
FIGURE 2. DAC121S101 Timing  
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10  
Typical Performance Characteristics fSCLK = 20 MHz, TA = 25C, Input Code Range 48 to 4047, unless  
otherwise stated  
DNL at VA = 2.7V  
INL at VA = 2.7V  
DNL vs. VA  
DNL at VA = 5.5V  
INL at VA = 5.5V  
INL vs. VA  
30018052  
30018054  
30018022  
30018053  
30018055  
30018023  
11  
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2.7V DNL vs. fSCLK  
5.5V DNL vs. fSCLK  
30018050  
30018056  
30018026  
30018051  
30018057  
30018027  
2.7V DNL vs. Clock Duty Cycle  
5.5V DNL vs. Clock Duty Cycle  
2.7V DNL vs. Temperature  
5.5V DNL vs. Temperature  
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12  
2.7V INL vs. fSCLK  
5.5V INL vs. fSCLK  
30018028  
30018030  
30018032  
30018029  
30018031  
30018033  
2.7V INL vs. Clock Duty Cycle  
5.5V INL vs. Clock Duty Cycle  
2.7V INL vs. Temperature  
5.5V INL vs. Temperature  
13  
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Zero Code Error vs. fSCLK  
Full-Scale Error vs. fSCLK  
Supply Current vs. VA  
Zero Code Error vs. Temperature  
Full-Scale Error vs. Temperature  
Supply Current vs. Temperature  
30018036  
30018039  
30018045  
30018034  
30018037  
30018044  
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14  
5V Glitch Response  
Power-On Reset  
30018046  
30018047  
3V Wake-Up Time  
5V Wake-Up Time  
30018048  
30018049  
15  
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1.3 OUTPUT AMPLIFIER  
1.0 Functional Description  
The output buffer amplifier is a rail-to-rail type, providing an  
output voltage range of 0V to VA. All amplifiers, even rail-to-  
rail types, exhibit a loss of linearity as the output approaches  
the supply rails (0V and VA, in this case). For this reason,  
linearity is specified over less than the full output range of the  
DAC. The output capabilities of the amplifier are described in  
the Electrical Tables.  
1.1 DAC SECTION  
The DAC121S101 is fabricated on a CMOS process with an  
architecture that consists of switches and a resistor string that  
are followed by an output buffer. The power supply serves as  
the reference voltage. The input coding is straight binary with  
an ideal output voltage of:  
1.4 SERIAL INTERFACE  
VOUT = VA x (D / 4096)  
The three-wire interface is compatible with SPI, QSPI and  
MICROWIRE, as well as most DSPs. See the Timing Diagram  
for information on a write sequence.  
where D is the decimal equivalent of the binary code that is  
loaded into the DAC register and can take on any value be-  
tween 0 and 4095.  
A write sequence begins by bringing the SYNC line low. Once  
SYNC is low, the data on the DIN line is clocked into the 16-  
bit serial input register on the falling edges of SCLK. On the  
16th falling clock edge, the last data bit is clocked in and the  
programmed function (a change in the mode of operation and/  
or a change in the DAC register contents) is executed. At this  
point the SYNC line may be kept low or brought high. In either  
case, it must be brought high for the minimum specified time  
before the next write sequence as a falling edge of SYNC can  
initiate the next write cycle.  
1.2 RESISTOR STRING  
The simplified resistor string is shown in Figure 3. Conceptu-  
ally, this string consists of 4096 equal valued resistors with a  
switch at each junction of two resistors, plus a switch to  
ground. The code loaded into the DAC register determines  
which switch is closed, connecting the proper node to the  
amplifier. This configuration guarantees that the DAC is  
monotonic.  
Since the SYNC and DIN buffers draw more current when they  
are high, they should be idled low between write sequences  
to minimize power consumption.  
1.5 INPUT SHIFT REGISTER  
The input shift register, Figure 4, has sixteen bits. The first  
two bits are "don't cares" and are followed by two bits that  
determine the mode of operation (normal mode or one of  
three power-down modes). The contents of the serial input  
register are transferred to the DAC register on the sixteenth  
falling edge of SCLK. See Timing Diagram, Figure 2.  
30018007  
FIGURE 3. DAC Resistor String  
30018008  
FIGURE 4. Input Register Contents  
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16  
Normally, the SYNC line is kept low for at least 16 falling  
edges of SCLK and the DAC is updated on the 16th SCLK  
falling edge. However, if SYNC is brought high before the 16th  
falling edge, the shift register is reset and the write sequence  
is invalid. The DAC register is not updated and there is no  
change in the mode of operation or in the output voltage.  
1.6 POWER-ON RESET  
30018009  
The power-on reset circuit controls the output voltage during  
power-up. Upon application of power the DAC register is filled  
with zeros and the output voltage is 0 Volts and remains there  
until a valid write sequence is made to the DAC.  
FIGURE 5. ADSP-2101/2103 Interface  
2.1.2 80C51/80L51 Interface  
A serial interface between the DAC121S101 and the  
80C51/80L51 microcontroller is shown in Figure 6. The  
SYNC signal comes from a bit-programmable pin on the mi-  
crocontroller. The example shown here uses port line P3.3.  
This line is taken low when data is to transmitted to the  
DAC121S101. Since the 80C51/80L51 transmits 8-bit bytes,  
only eight falling clock edges occur in the transmit cycle. To  
load data into the DAC, the P3.3 line must be left low after the  
first eight bits are transmitted. A second write cycle is initiated  
to transmit the second byte of data, after which port line P3.3  
is brought high. The 80C51/80L51 transmit routine must rec-  
ognize that the 80C51/80L51 transmits data with the LSB first  
while the DAC121S101 requires data with the MSB first.  
1.7 POWER-DOWN MODES  
The DAC121S101 has four modes of operation. These  
modes are set with two bits (DB13 and DB12) in the control  
register.  
TABLE 1. Modes of Operation  
DB13  
DB12  
Operating Mode  
0
0
1
1
0
1
0
1
Normal Operation  
Power-Down with 5kto GND  
Power-Down with 100kto GND  
Power-Down with Hi-Z  
When both DB13 and DB12 are 0, the device operates nor-  
mally. For the other three possible combinations of these bits  
the supply current drops to its power-down level and the out-  
put is pulled down with either a 5kor a 100kresistor, or is  
in a high impedance state, as described in Table 1.  
The bias generator, output amplifier, the resistor string and  
other linear circuitry are all shut down in any of the power-  
down modes. Minimum power consumption is achieved in the  
power-down mode with SCLK disabled and SYNC and DIN  
idled low.  
30018010  
FIGURE 6. 80C51/80L51 Interface  
2.1.3 68HC11 Interface  
A serial interface between the DAC121S101 and the 68HC11  
microcontroller is shown in Figure 7. The SYNC line of the  
DAC121S101 is driven from a port line (PC7 in the figure),  
similar to the 80C51/80L51.  
2.0 Applications Information  
The simplicity of the DAC121S101 implies ease of use. How-  
ever, it is important to recognize that any data converter that  
utilizes its supply voltage as its reference voltage will have  
essentially zero PSRR (Power Supply Rejection Ratio).  
Therefore, it is necessary to provide a noise-free supply volt-  
age to the device.  
The 68HC11 should be configured with its CPOL bit as a zero  
and its CPHA bit as a one. This configuration causes data on  
the MOSI output to be valid on the falling edge of SCLK. PC7  
is taken low to transmit data to the DAC. The 68HC11 trans-  
mits data in 8-bit bytes with eight falling clock edges. Data is  
transmitted with the MSB first. PC7 must remain low after the  
first eight bits are transferred. A second write cycle is initiated  
to transmit the second byte of data to the DAC, after which  
PC7 should be raised to end the write sequence.  
2.1 DSP/MICROPROCESSOR INTERFACING  
Interfacing the DAC121S101 to microprocessors and DSPs  
is quite simple. The following guidelines are offered to hasten  
the design process.  
2.1.1 ADSP-2101/ADSP2103 Interfacing  
Figure 5 shows a serial interface between the DAC121S101  
and the ADSP-2101/ADSP2103. The DSP should be set to  
operate in the SPORT Transmit Alternate Framing Mode. It is  
programmed through the SPORT control register and should  
be configured for Internal Clock Operation, Active Low Fram-  
ing and 16-bit Word Length. Transmission is started by writing  
a word to the Tx register after the SPORT mode has been  
enabled.  
30018011  
FIGURE 7. 68HC11 Interface  
2.1.4 Microwire Interface  
Figure 8 shows an interface between a Microwire compatible  
device and the DAC121S101. Data is clocked out on the rising  
edges of the SCLK signal.  
17  
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30018012  
FIGURE 8. Microwire Interface  
2.2 USING REFERENCES AS POWER SUPPLIES  
Recall the need for a quiet supply source for devices that use  
their power supply voltage as a reference voltage.  
Since the DAC121S101 consumes very little power, a refer-  
ence source may be used as the supply voltage. The advan-  
tages of using a reference source over a voltage regulator are  
accuracy and stability. Some low noise regulators can also be  
used for the power supply of the DAC121S101. Listed below  
are a few power supply options for the DAC121S101.  
30018014  
FIGURE 10. The LM4050 as a power supply  
The minimum resistor value in the circuit of Figure 10 should  
be chosen such that the maximum current through the  
LM4050 does not exceed its 15 mA rating. The conditions for  
maximum current include the input voltage at its maximum,  
the LM4050 voltage at its minimum, the resistor value at its  
minimum due to tolerance, and the DAC121S101 draws zero  
current. The maximum resistor value must allow the LM4050  
to draw more than its minimum current for regulation plus the  
maximum DAC121S101 current in full operation. The condi-  
tions for minimum current include the input voltage at its  
minimum, the LM4050 voltage at its maximum, the resistor  
value at its maximum due to tolerance, and the DAC121S101  
draws its maximum current. These conditions can be sum-  
marized as  
2.2.1 LM4130  
The LM4130 reference, with its 0.05% accuracy over tem-  
perature, is a good choice as a power source for the  
DAC121S101. Its primary disadvantage is the lack of 3 V and  
5 V versions. However, the 4.096 V version is useful if a 0 to  
4.095 V output range is desirable or acceptable. Bypassing  
the LM4130 VIN pin with a 0.1 µF capacitor and the VOUT  
pin with a 2.2 µF capacitor will improve stability and reduce  
output noise. The LM4130 comes in a space-saving 5-pin  
SOT23.  
R(min) = ( VIN(max) − VZ(min) / (IA(min) + IZ(max))  
and  
R(max) = ( VIN(min) − VZ(max) / (IA(max) + IZ(min) )  
where VZ(min) and VZ(max) are the nominal LM4050 output  
voltages ± the LM4050 output tolerance over temperature, IZ  
(max) is the maximum allowable current through the LM4050,  
IZ(min) is the minimum current required by the LM4050 for  
proper regulation, IA(max) is the maximum DAC121S101 sup-  
ply current, and IA(min) is the minimum DAC121S101 supply  
current.  
30018013  
FIGURE 9. The LM4130 as a power supply  
2.2.3 LP3985  
2.2.2 LM4050  
The LP3985 is a low noise, ultra low dropout voltage regulator  
with a 3% accuracy over temperature. It is a good choice for  
applications that do not require a precision reference for the  
DAC121S101. It comes in 3.0V, 3.3V and 5V versions, among  
others, and sports a low 30 µV noise specification at low fre-  
quencies. Since low frequency noise is relatively difficult to  
filter, this specification could be important for some applica-  
tions. The LP3985 comes in a space-saving 5-pin SOT23 and  
5-bump micro SMD packages.  
Available with accuracy of 0.44%, the LM4050 shunt refer-  
ence is also a good choice as a power regulator for the  
DAC121S101. It does not come in a 3 Volt version, but 4.096  
V and 5 V versions are available. It comes in a space-saving  
3-pin SOT23.  
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18  
30018015  
30018017  
FIGURE 11. Using the LP3985 regulator  
FIGURE 13. Bipolar Operation  
An input capacitance of 1.0µF without any ESR requirement  
is required at the LP3985 input, while a 1.0µF ceramic ca-  
pacitor with an ESR requirement of 5mto 500mis required  
at the output. Careful interpretation and understanding of the  
capacitor specification is required to ensure correct device  
operation.  
The output voltage of this circuit for any code is found to be  
VO = (VA x (D / 4096) x ((R1 + R2) / R1) - VA x R2 / R1)  
where D is the input code in decimal form. With VA = 5V and  
R1 = R2,  
2.2.4 LP2980  
VO = (10 x D / 4096) - 5V  
The LP2980 is an ultra low dropout regulator with a 0.5% or  
1.0% accuracy over temperature, depending upon grade. It is  
available in 3.0V, 3.3V and 5V versions, among others.  
A list of rail-to-rail amplifiers suitable for this application are  
indicated in Table 2.  
TABLE 2. Some Rail-to-Rail Amplifiers  
Typ ISUPPLY  
AMP  
PKGS  
Typ VOS  
DIP-8  
SOT23-5  
LMC7111  
0.9 mV  
25 µA  
SO-8  
SOT23-5  
LM7301  
LM8261  
0.03 mV  
0.7 mV  
620 µA  
1 mA  
SOT23-5  
2.4 LAYOUT, GROUNDING, AND BYPASSING  
For best accuracy and minimum noise, the printed circuit  
board containing the DAC121S101 should have separate  
analog and digital areas. The areas are defined by the loca-  
tions of the analog and digital power planes. Both of these  
planes should be located in the same board layer. There  
should be a single ground plane. A single ground plane is  
preferred if digital return current does not flow through the  
analog ground area. Frequently a single ground plane design  
will utilize a "fencing" technique to prevent the mixing of ana-  
log and digital ground current. Separate ground planes should  
only be utilized when the fencing technique is inadequate.  
The separate ground planes must be connected in one place,  
preferably near the DAC121S101. Special care is required to  
guarantee that digital signals with fast edge rates do not pass  
over split ground planes. They must always have a continu-  
ous return path below their traces.  
30018016  
FIGURE 12. Using the LP2980 regulator  
Like any low dropout regulator, the LP2980 requires an output  
capacitor for loop stability. This output capacitor must be at  
least 1.0µF over temperature, but values of 2.2µF or more will  
provide even better performance. The ESR of this capacitor  
should be within the range specified in the LP2980 data sheet.  
Surface-mount solid tantalum capacitors offer a good combi-  
nation of small size and ESR. Ceramic capacitors are attrac-  
tive due to their small size but generally have ESR values that  
are too low for use with the LP2980. Aluminum electrolytic  
capacitors are typically not a good choice due to their large  
size and have ESR values that may be too high at low tem-  
peratures.  
The DAC121S101 power supply should be bypassed with a  
10µF and a 0.1µF capacitor as close as possible to the device  
with the 0.1µF right at the device supply pin. The 10µF ca-  
pacitor should be a tantalum type and the 0.1µF capacitor  
should be a low ESL, low ESR type. The power supply for the  
DAC121S101 should only be used for analog circuits.  
2.3 BIPOLAR OPERATION  
The DAC121S101 is designed for single supply operation and  
thus has a unipolar output. However, a bipolar output may be  
obtained with the circuit in Figure 13. This circuit will provide  
an output voltage range of ±5 Volts. A rail-to-rail amplifier  
should be used if the amplifier supplies are limited to ±5V.  
Avoid crossover of analog and digital signals and keep the  
clock and data lines on the component side of the board. The  
clock and data lines should have controlled impedances.  
19  
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3.0 Radiation Environments  
Careful consideration should be given to environmental con-  
ditions when using a product in a radiation environment.  
3.2 Single Event Latch-Up and  
Functional Interrupt  
One time single event latch-up (SEL) and single event func-  
tional interrupt (SEFI) testing was preformed according to  
EIA/JEDEC Standard, EIA/JEDEC57. The linear energy  
transfer threshold (LETth) shown in the Key Specifications  
table on the front page is the maximum LET tested. A test  
report is available upon request.  
3.1 Total Ionizing Dose  
Radiation hardness assured (RHA) products are those part  
numbers with a total ionizing dose (TID) level specified in the  
Ordering Information table on the front page. Testing and  
qualification of these products is done on a wafer level ac-  
cording to MIL-STD-883G, Test Method 1019.7, Condition A  
and the “Extended room temperature anneal test” described  
in section 3.11 for application environment dose rates less  
than 0.027 rad(Si)/s. Wafer level TID data is available with lot  
shipments.  
3.3 Single Event Upset  
A report on single event upset (SEU) is available upon re-  
quest.  
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20  
Revision History  
Date Relased  
Revision  
Section  
Changes  
05/05/08  
A
B
Initial Release  
New Product Data Sheet Release  
Removed SMD reference. Added  
DAC121S101WGMLS NSPN . Revision A will be  
Archived.  
08/14/08  
07/15/09  
Ordering Information Table  
Added SMD reference, removed MLS device.  
Changed following parameter limits from Max to  
Min tH, tL, tSUCL tSUD, tDHD, tCS, tSYNC, tSUCL limit  
from −21 to 0, Added Delta Parameters. Added  
subgroups to fSCLK, Removed the typical limits.  
Changed paragraph's 1.7 and 3.0 section.  
Revision B will be Archived  
Ordering Information Table, AC and  
Timing Electrical Characteristics  
C
D
Added reference to MPR and CVAL NSPN,  
Ordering Information Table, Note Section, verbiage to Note 12, Per DSCC recommendation  
Operating Life Test Delta Table and  
Section 3.0 Radiation Environments  
05/06/2010  
delta limits for Supply Current. Change to para 3.1,  
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21  
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