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产品型号DAC5672IPFB的概述

DAC5672IPFB概述 DAC5672IPFB是一个高性能的数模转换器(DAC),由德州仪器(Texas Instruments)公司制造。该芯片旨在满足高保真度和低失真的声音应用,同时能够处理各种信号。DAC5672IPFB具有高转换速率、高分辨率和优越的传输性能,是现代数字信号处理(DSP)、通信系统和音频设备等领域的理想选择。 DAC5672采用了双通道架构,能够同时处理两个差分信号,支持高达16位的分辨率和高速DAC转换,适合需要高吞吐量和良好动态范围的应用。它的输出可以直接驱动放大器,有效地减少了外部电路的复杂性。 DAC5672IPFB详细参数 DAC5672IPFB的主要技术参数如下: - 分辨率: 16位 - 输入接口: 串行输入 - DATARATE: 支持高达1 GSPS的转换速率 - 动态范围: 89 dB (typical) - THD+N: -83 dB ...

产品型号DAC5672IPFB的Datasheet PDF文件预览

DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
DUAL, 14-BIT 200 MSPS DIGITAL-TO-ANALOG CONVERTER  
FEATURES  
Package: 48-Pin Thin-Quad Flat Pack (TQFP)  
14-Bit Dual Transmit Digital-to-Analog  
Converter (DAC)  
APPLICATIONS  
Cellular Base Transceiver Station Transmit  
Channel  
200 MSPS Update Rate  
Single Supply: 3.0 V to 3.6 V  
– CDMA: W-CDMA, CDMA2000, IS-95  
– TDMA: GSM, IS-136, EDGE/UWC-136  
Medical/Test Instrumentation  
Arbitrary Waveform Generators (ARB)  
Direct Digital Synthesis (DDS)  
High Spurious-Free Dynamic Range (SFDR):  
84 dBc at 5 MHz  
High Third-Order Two-Tone Intermodulation  
(IMD3): 79 dBc at 15.1 MHz and 16.1 MHz  
WCDMA Adjacent Channel Leakage Ratio  
(ACLR): 78 dB at Baseband  
Cable Modem Termination System (CMTS)  
WCDMA ACLR: 73 dB at 30.72 MHz  
Independent or Single Resistor Gain Control  
Dual or Interleaved Data  
On-Chip 1.2-V Reference  
Low Power: 330 mW  
Power-Down Mode: 9 mW  
DESCRIPTION  
The DAC5672 is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.  
Operating with update rates of up to 200 MSPS, the DAC5672 offers exceptional dynamic performance,  
tight-gain, and offset matching characteristics that make it suitable in either I/Q baseband or direct IF  
communication applications.  
Each DAC has a high-impedance, differential-current output, suitable for single-ended or differential  
analog-output configurations. External resistors allow scaling the full-scale output current for each DAC  
separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is  
temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may  
be used.  
The DAC5672 has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the  
DAC5672 also supports multiplexed data for each DAC on one port when operating in the interleaved mode.  
The DAC5672 has been specifically designed for a differential transformer-coupled output with a 50-  
doubly-terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output  
power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.  
The DAC5672 is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit  
(DAC5662) and 14-bit (DAC5672) resolution. Furthermore, the DAC5672 is pin compatible to the DAC2904 and  
AD9767 dual DACs. The device is characterized for operation over the industrial temperature range of -40°C to  
85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
FUNCTIONAL BLOCK DIAGRAM  
WRTB  
WRTA  
CLKB CLKA  
DE-  
MUX  
IOUTA1  
IOUTA2  
Latch A  
14−b DAC  
DA[13:0]  
DB[13:0]  
BIASJ_A  
IOUTB1  
IOUTB2  
Latch B  
14−b DAC  
MODE  
GSET  
BIASJ_B  
EXTIO  
1.2 V Reference  
SLEEP  
DVDD  
DGND  
AVDD  
AGND  
AVAILABLE OPTIONS  
TA  
PACKAGED DEVICES  
48-Pin TQFP  
-40°C to 85°C  
DAC5672IPFB  
DAC5672IPFBR  
2
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
DEVICE INFORMATION  
48 47 46 45 44 43 42 41 40 39 38 37  
DA13 (MSB)  
DA12  
DA11  
DA10  
DA9  
DB0 (LSB)  
DB1  
36  
1
2
3
4
5
6
7
8
9
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
DB2  
DB3  
DB4  
Top View  
48−Pin TQFP  
PFB Package  
DA8  
DB5  
DA7  
DB6  
DA6  
DB7  
DA5  
DB8  
DA4 10  
DA3 11  
DB9  
DB10  
DB11  
12  
DA2  
13 14 15 16 17 18 19 20 21 22 23 24  
TERMINAL FUNCTIONS  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
38  
AGND  
I
I
Analog ground  
AVDD  
47  
Analog supply voltage  
BIASJ_A  
BIASJ_B  
44  
O
O
I
Full-scale output current bias for DACA  
Full-scale output current bias for DACB  
Clock input for DACA, CLKIQ in interleaved mode  
Clock input for DACB, RESETIQ in interleaved mode  
Data port A. DA13 is MSB and DA0 is LSB.  
Data port B. DB13 is MSB and DB0 is LSB.  
Digital ground  
41  
CLKA/CLKIQ  
CLKB/RESETIQ  
DA[13:0]  
DB[13:0]  
DGND  
18  
19  
I
1-14  
23-36  
15, 21  
16, 22  
43  
I
I
I
DVDD  
I
Digital supply voltage  
EXTIO  
I/O  
I
Internal reference output (bypass with 0.1 µF to AGND) or external reference input  
Gain-setting mode: H – 1 resistor, L – 2 resistors. Internal pullup.  
DACA current output. Full-scale with all bits of DA high.  
GSET  
42  
IOUTA1  
IOUTA2  
IOUTB1  
IOUTB2  
MODE  
46  
O
O
O
O
I
45  
DACA complementary current output. Full-scale with all bits of DA low.  
DACB current output. Full-scale with all bits of DB high.  
39  
40  
DACB complementary current output. Full-scale with all bits of DB low.  
Mode Select: H – Dual Bus, L – Interleaved. Internal pullup.  
48  
Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode.  
Internal pulldown.  
SLEEP  
37  
I
WRTA/WRTIQ  
17  
20  
I
I
Input write signal for PORT A (WRTIQ in interleaving mode)  
Input write signal for PORT B (SELECTIQ in interleaving mode)  
WRTB/SELECTIQ  
3
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
ABSOLUTE MAXIMUM RATINGS  
over TA (unless otherwise noted)(1)  
UNIT  
Supply voltage range  
AVDD(2)  
DVDD(3)  
-0.5 V to 4 V  
-0.5 V to 4 V  
Voltage between AGND and DGND  
Voltage between AVDD and DVDD  
Supply voltage range  
-0.5 V to 0.5 V  
-0.5 V to 0.5 V  
-0.5 V to DVDD + 0.5 V  
-0.5 V to DVDD + 0.5 V  
-1.0 V to AVDD + 0.5 V  
-0.5 V to AVDD + 0.5 V  
+20 mA  
DA[13:0] and DB[13:0](3)  
MODE, CLKA, CLKB, WRTA, WRTB(3)  
IOUTA1, IOUTA2, IOUTB1, IOUTB2(2)  
EXTIO, BIASJ_A, BIASJ_B, SLEEP(2)  
Peak input current (any input)  
Peak total input current (all inputs)  
-30 mA  
Operating free-air temperature range  
Storage temperature range  
-40 °C to 85 °C  
-65 °C to 150 °C  
260 °C  
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds  
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings  
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) Measured with respect to AGND.  
(3) Measured with respect to DGND.  
ELECTRICAL CHARACTERISTICS  
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless otherwise noted)  
PARAMETER  
DC Specifications  
Resolution  
DC Accuracy(1)  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
14  
Bits  
INL  
Integral nonlinearity  
Differential nonlinearity  
1 LSB = IOUTFS/214, TMIN to TMAX  
-4  
-3  
±1.1  
4
3
LSB  
LSB  
DNL  
±0.75  
Analog Output  
Offset error  
Midscale value  
±0.03  
±0.03  
±0.25  
±0.25  
2
%FSR  
%FSR  
%FSR  
%FSR  
mA  
Offset mismatch  
Gain error  
Midscale value  
With external reference  
With internal reference  
Minimum full-scale output current(2)  
Maximum full-scale output current(2)  
Gain mismatch  
20  
mA  
With external reference  
With internal reference  
-2  
-2  
-1  
0.2  
2
2
%FSR  
%FSR  
V
0.2  
Output voltage compliance range(3)  
Output resistance  
1.25  
RO  
CO  
300  
5
kΩ  
Output capacitance  
pF  
Reference Output  
Reference voltage  
1.14  
1.2  
1.26  
V
(1) Measured differentially through 50 to AGND.  
(2) Nominal full-scale current, IOUTFS, equals 32x the IBIAS current.  
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,  
resulting in reduced reliability of the DAC5672 device. The upper limit of the output compliance is determined by the load resistors and  
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.  
4
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
ELECTRICAL CHARACTERISTICS (continued)  
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Reference output current(4)  
100  
nA  
Reference Input  
VEXTIO  
RI  
Input voltage  
0.1  
1.25  
V
Input resistance  
Small signal bandwidth  
Input capacitance  
1
300  
100  
MΩ  
kHz  
pF  
CI  
Temperature Coefficients  
Offset drift  
2
±20  
±40  
±20  
ppm of  
FSR/°C  
Gain drift  
With external reference  
With internal reference  
ppm of  
FSR/°C  
ppm of  
FSR/°C  
Reference voltage drift  
ppm/°C  
(4) Use an external buffer amplifier with high-impedance input to drive any external load.  
ELECTRICAL CHARACTERISTICS  
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz, independent gain set mode (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Power Supply  
AVDD  
DVDD  
IAVDD  
Analog supply voltage  
Digital supply voltage  
Supply current, analog  
3
3
3.3  
3.3  
75  
3.6  
3.6  
90  
V
V
Including output current through load  
resistor  
mA  
Sleep mode with clock  
2.5  
2.5  
25  
6
mA  
mA  
mA  
mA  
mA  
mW  
mW  
mW  
Sleep mode without clock  
IDVDD  
Supply current, digital  
Power dissipation  
38  
18  
Sleep mode with clock  
13.4  
0.6  
330  
53  
Sleep mode without clock  
390  
Sleep mode with clock  
Sleep mode without clock  
9.2  
-0.01  
0
APSRR  
DPSRR  
TA  
Analog power supply rejection ratio  
Digital power supply rejection ratio  
Operating free-air temperature  
-0.2  
-0.2  
-40  
0.2 %FSR/V  
0.2 %FSR/V  
85  
°C  
5
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
ELECTRICAL CHARACTERISTICS  
AC specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, differential 1:1 impedance  
ratio transformer coupled output, 50-doubly terminated load (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Analog Output  
fclk  
ts  
tr  
Maximum output update rate  
Output settling time to 0.1% (DAC)  
Output rise time 10% to 90% (OUT)  
Output fall time 90% to 10% (OUT)  
Output noise  
200  
MSPS  
ns  
Mid-scale transition  
20  
1.4  
1.5  
55  
ns  
tf  
ns  
IOUTFS = 20 mA  
IOUTFS = 2 mA  
pA/Hz  
pA/Hz  
30  
AC Linearity (estimates based on measurements of preliminary parts)  
SFDR  
Spurious-free dynamic range  
1st Nyquist zone, TA = 25°C,  
fDATA = 50 MSPS, fOUT = 1 MHz,  
IOUTFS = 0 dB  
83  
80  
79  
dBc  
dBc  
dBc  
1st Nyquist zone, TA = 25°C,  
fDATA = 50 MSPS, fOUT = 1 MHz,  
IOUTFS = -6 dB  
1st Nyquist zone, TA = 25°C,  
fDATA = 50 MSPS, fOUT = 1 MHz,  
IOUTFS = -12 dB  
1st Nyquist zone, TA = 25°C,  
fDATA = 100 MSPS, fOUT = 5 MHz  
84  
79  
75  
72  
77  
70  
75  
dBc  
dBc  
dBc  
dBc  
dB  
1st Nyquist zone, TA = 25°C,  
fDATA = 100 MSPS, fOUT = 20 MHz  
1st Nyquist zone, TMIN to TMAX  
fDATA = 200 MSPS, fOUT = 20 MHz  
,
68  
1st Nyquist zone, TA = 25°C,  
fDATA = 200 MSPS, fOUT = 41 MHz  
SNR  
Signal-to-noise ratio  
1st Nyquist zone, TA = 25°C,  
fDATA = 100 MSPS, fOUT = 5 MHz  
1st Nyquist zone, TA = 25°C,  
fDATA = 160 MSPS, fOUT = 20 MHz  
dB  
ACLR  
Adjacent channel leakage ratio  
W-CDMA signal with 3.84-MHz  
Bandwidth, fDATA = 61.44 MSPS,  
IF = 15.360 MHz  
dB  
W-CDMA signal with 3.84-MHz  
Bandwidth, fDATA = 122.88 MSPS,  
IF = 30.72 MHz  
73  
78  
78  
65  
79  
dB  
dB  
W-CDMA signal with 3.84-MHz  
Bandwidth, fDATA = 61.44 MSPS,  
Baseband  
W-CDMA signal with 3.84-MHz  
Bandwidth, fDATA = 122.88 MSPS,  
Baseband  
dB  
IMD3  
Third-order two-tone intermodulation Each tone at -6 dBFS, TA = 25°C,  
fDATA = 200 MSPS,  
dBc  
dBc  
fOUT = 45.4 MHz and 46.4 MHz  
Each tone at -6 dBFS, TA = 25°C,  
fDATA = 100 MSPS,  
fOUT = 15.1 MHz and 16.1 MHz  
6
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
ELECTRICAL CHARACTERISTICS (continued)  
AC specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, differential 1:1 impedance  
ratio transformer coupled output, 50-doubly terminated load (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
IMD  
Four-tone intermodulation  
Each tone at -12 dBFS, TA = 25°C  
fDATA = 100 MSPS  
79  
dBc  
fOUT = 15.6, 15.8, 16.2, and 16.4 MHz  
Each tone at -12 dBFS, TA = 25°C  
fDATA = 165 MSPS  
fOUT = 68.8, 69.6, 71.2, and 72.0 MHz  
61  
73  
95  
dBc  
dBc  
dBc  
Each tone at -12 dBFS, TA = 25°C  
fDATA = 165 MSPS  
fOUT = 19.0, 19.1, 19.3, and 19.4 MHz  
Channel isolation  
TA = 25°C, fDATA = 165 MSPS  
fOUT (CH1) = 20 MHz  
fOUT (CH2) = 21 MHz  
ELECTRICAL CHARACTERISTICS  
Digital specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Digital Input  
VIH  
High-level input voltage  
2
0
3.3  
0.8  
V
VIL  
Low-level input voltage  
V
IIH  
High-level input current  
±50  
±10  
7
µA  
µA  
µA  
µA  
µA  
µA  
pF  
IIL  
Low-level input current  
IIH(GSET)  
IIL(GSET)  
IIH(MODE)  
IIL(MODE)  
CI  
High-level input current, GSET pin  
Low-level input current, GSET pin  
High-level input current, MODE pin  
Low-level input current, MODE pin  
Input capacitance  
-80  
-30  
-80  
5
SWITCHING CHARACTERISTICS  
Digital specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA (unless otherwise noted)  
PARAMETER  
Timing - Dual Bus Mode  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
tsu  
Input setup time  
1
1
ns  
ns  
ns  
clk  
ns  
th  
Input hold time  
tLPH  
tLAT  
tPD  
Input clock pulse high time  
Clock latency (WRTA/B to outputs)  
Propagation delay time  
1
4
4
4
1.5  
Timing - Single Bus Interleaved Mode  
tsu  
Input setup time  
0.5  
0.5  
ns  
ns  
clk  
ns  
th  
Input hold time  
tLAT  
tPD  
Clock latency (WRTA/B to outputs)  
Propagation delay time  
4
1.5  
7
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
TYPICAL CHARACTERISTICS  
INTEGRAL NONLINEARITY  
vs  
INPUT CODE  
1.5  
1.0  
0.5  
0.0  
−0.5  
−1.0  
−1.5  
0
2000  
4000  
6000  
8000  
10000  
12000  
14000  
16000  
Input Code  
G001  
Figure 1.  
DIFFERENTIAL NONLINEARITY  
vs  
INPUT CODE  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
−0.2  
−0.4  
−0.6  
−0.8  
−1.0  
0
2000  
4000  
6000  
8000  
10000  
12000  
14000  
16000  
Input Code  
G002  
Figure 2.  
8
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
TYPICAL CHARACTERISTICS (continued)  
SPURIOUS-FREE DYNAMIC RANGE  
SPURIOUS-FREE DYNAMIC RANGE  
vs  
vs  
OUTPUT FREQUENCY  
OUTPUT FREQUENCY  
100  
95  
100  
95  
90  
85  
80  
75  
70  
65  
60  
0 dBf  
S
0 dBf  
S
90  
85  
80  
75  
70  
65  
60  
−6 dBf  
S
−6 dBf  
S
−12 dBf  
S
−12 dBf  
S
f
= 52 MSPS  
Dual Bus Mode  
f
= 78 MSPS  
data  
data  
Dual Bus Mode  
0
4
8
12  
16  
20  
0
5
10  
15  
20  
25  
30  
f
out  
− Output Frequency − MHz  
f
out  
− Output Frequency − MHz  
G003  
G004  
Figure 3.  
Figure 4.  
SPURIOUS-FREE DYNAMIC RANGE  
SPURIOUS-FREE DYNAMIC RANGE  
vs  
vs  
OUTPUT FREQUENCY  
OUTPUT FREQUENCY  
100  
95  
90  
85  
80  
75  
70  
65  
60  
100  
95  
90  
85  
80  
75  
70  
65  
60  
0 dBf  
S
0 dBf  
S
−6 dBf  
S
−6 dBf  
S
−12 dBf  
S
−12 dBf  
S
f
= 100 MSPS  
Dual Bus Mode  
f
= 165 MSPS  
Dual Bus Mode  
data  
data  
0
5
10  
15  
20  
25  
30  
35  
0
5
10 15 20 25 30 35 40 45 50 55 60  
f
out  
− Output Frequency − MHz  
f
out  
− Output Frequency − MHz  
G005  
G006  
Figure 5.  
Figure 6.  
9
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
TYPICAL CHARACTERISTICS (continued)  
SINGLE-TONE SPECTRUM  
SINGLE-TONE SPECTRUM  
0
0
−20  
f
f
= 78 MSPS  
= 15 MHz  
f
f
= 165 MSPS  
= 30.1 MHz  
data  
data  
OUT  
OUT  
Dual Bus Mode  
Dual Bus Mode  
−20  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−100  
0.0  
7.8  
15.6  
23.4  
31.2  
39.0  
0.0  
16.5  
33.0  
49.5  
66.0  
82.5  
f − Frequency − MHz  
f − Frequency − MHz  
G007  
G008  
Figure 7.  
Figure 8.  
TWO-TONE IMD3  
vs  
OUTPUT FREQUENCY  
TWO-TONE IMD3  
vs  
OUTPUT FREQUENCY  
95  
90  
85  
80  
75  
70  
65  
60  
100  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
f
= 78 MSPS  
f
= 165 MSPS  
data  
data  
Dual Bus Mode  
Dual Bus Mode  
f
= f  
out1  
+ 1 MHz  
f
= f  
out1  
+ 1 MHz  
out2  
out2  
0
5
10  
15  
20  
25  
30  
35  
0
10  
20  
30  
40  
50  
f
− Output Frequency − MHz  
f
− Output Frequency − MHz  
out1  
out1  
G009  
G010  
Figure 9.  
Figure 10.  
10  
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
TYPICAL CHARACTERISTICS (continued)  
TWO-TONE SPECTRUM  
TWO-TONE SPECTRUM  
= 165 MSPS  
= 30.1 MHz  
= 31.1 MHz  
f
f
f
f
f
f
= 78 MSPS  
= 20.1 MHz  
= 21.1 MHz  
data  
out1  
out2  
data  
out1  
out2  
−10  
−30  
−10  
−30  
Dual Bus Mode  
Dual Bus Mode  
−50  
−50  
−70  
−70  
−90  
−90  
−110  
−110  
19.0  
19.5  
20.0  
20.5  
21.0  
21.5  
22.0  
29.0  
29.5  
30.0  
30.5  
31.0  
31.5  
32.0  
f − Frequency − MHz  
f − Frequency − MHz  
G011  
G012  
Figure 11.  
Figure 12.  
POWER  
vs  
FREQUENCY  
POWER  
vs  
FREQUENCY  
−20  
−40  
−20  
−40  
f
= 122.88 MSPS  
f
= 61.44 MSPS  
data  
data  
Baseband Signal  
Dual Bus Mode  
IF = 15.36 MHz  
ACLR = 75.18 dB  
Dual Bus Mode  
−60  
−60  
−80  
−80  
−100  
−120  
−100  
−120  
0
1
2
3
4
5
6
7
8
9
10  
7.6  
10.1  
12.6  
15.1  
17.6  
20.1  
22.6  
f − Frequency − MHz  
f − Frequency − MHz  
G013  
G014  
Figure 13.  
Figure 14.  
11  
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
TYPICAL CHARACTERISTICS (continued)  
POWER  
vs  
FREQUENCY  
POWER  
vs  
FREQUENCY  
−20  
−20  
−40  
f
= 122.88 MSPS  
f
= 122.88 MSPS  
data  
data  
IF = 15.36 MHz  
ACLR = 77.16 dB  
Dual Bus Mode  
IF = 30.72 MHz  
ACLR = 72.7 dB  
Dual Bus Mode  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−100  
−120  
7.6  
10.1  
12.6  
15.1  
17.6  
20.1  
22.6  
23.0  
25.5  
28.0  
30.5  
33.0  
35.5  
38.0  
f − Frequency − MHz  
f − Frequency − MHz  
G015  
G016  
Figure 15.  
Figure 16.  
Digital Inputs and Timing  
Digital Inputs  
The data input ports of the DAC5672 accept a standard positive coding with data bits DA13 and DB13 being the  
most significant bits (MSB). The converter outputs support a clock rate of up to 200 MSPS. The best  
performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may  
vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their  
specified limits.  
All digital inputs of the DAC5672 are CMOS compatible. Figure 17 and Figure 18 show schematics of the  
equivalent CMOS digital inputs of the DAC5672. The 14-bit digital data input follows the offset positive binary  
coding scheme. The DAC5672 is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.  
DVDD  
DA[13:0]  
DB[13:0]  
Internal  
SLEEP  
Digital In  
CLKA/B  
WRTA/B  
DGND  
Figure 17. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor  
12  
 
DAC5672  
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SLAS440NOVEMBER 2004  
Digital Inputs and Timing (continued)  
DVDD  
Internal  
GSET  
Digital In  
MODE  
DGND  
Figure 18. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor  
Input Interfaces  
The DAC5672 features two operating modes selected by the MODE pin, as shown in the following table:  
For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own  
separate data input bus, clock input, and data write signal (data latch-in).  
In single-bus interleaved mode, the data must be presented interleaved at the A-channel input bus. The  
B-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.  
MODE Pin  
Bus input  
MODE pin connected to DGND  
MODE pin connected to DVDD  
Single-bus interleaved mode, clock and write input equal for both DACs  
Dual-bus mode, DACs operate independently  
Dual-Bus Data Interface and Timing  
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5672 consist  
of two independent, 14-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA,  
WRTB) and clock (CLKA, CLKB) lines. The WRTA/B lines control the channel input latches and the CLKA/B lines  
control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRTA/B line.  
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock  
domains having equal periods (but possibly different phases) are input to the DAC5672. This is defined by a  
minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.  
This essentially implies that the rising edge of CLKA/B must occur at the same time or before the rising edge of  
the WRTA/B signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the  
rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected  
externally. Note that all specifications were measured with the WRTA/B and CLKA/B lines connected together.  
13  
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
DA[13:0]/DB[13:0]  
Valid Data  
t
su  
t
h
t
1ph  
WRTA/WRTB  
CLKA/CLKB  
t
settle  
t
pd  
t
lat  
IOUT  
or  
IOUT  
Figure 19. Dual-Bus Mode Operation  
Single-Bus Interleaved Data Interface and Timing  
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 20 shows the timing diagram. In  
interleaved mode, the A- and B-channels share the write input (WRTIQ) and update clock (CLKIQ and internal  
CLKDACIQ). Multiplexing logic directs the input word at the A-channel input bus to either the A-channel input  
latch (SELECTIQ is high) or to the B-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data  
value in the B-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is  
low, the data value in the A-channel latch is retained by presenting the latch output data to its input.  
In interleaved mode, the A-channel input data rate is twice the update rate of the DAC core. As in dual-bus  
mode, it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch  
the A- and B-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the A-  
and B-DAC latches on the following falling edge of the write inputs. The DAC5672 clock input is divided by a  
factor of two before it is presented to the DAC latches.  
Correct pairing of the A- and B-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is  
divided by two, which would translate to a non-deterministic relation between the rising edges of the CLKIQ and  
CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ with respect  
to the data at the input of the DAC latch is determined. CLKDACIQ is disabled (low) when RESETIQ is high.  
14  
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
DA[13:0]  
Valid Data  
t
su  
t
h
SELECTIQ  
WRTIQ  
CLKIQ  
RESETIQ  
t
settle  
t
pd  
t
lat  
IOUT  
or  
IOUT  
Figure 20. Single-Bus Interleaved Mode Operation  
15  
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
APPLICATION INFORMATION  
Theory of Operation  
The architecture of the DAC5672 uses a current steering technique to enable fast switching and high update  
rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to  
deliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switches  
each time the DAC is updated and a corresponding output current is formed by steering all currents to either  
output summing node, IOUT1 or IOUT2. The complementary outputs deliver a differential output signal, which  
improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise),  
and double the peak-to-peak output signal swing by a factor of two, as compared to single-ended operation.  
The segmented architecture results in a significant reduction of the glitch energy and improves the dynamic  
performance (SFDR) and DNL. The current outputs maintain a very high output impedance of greater  
than 300 k.  
When pin 42 (GSET) is high (simultaneous gain set mode), the full-scale output current for both DACs is  
determined by the ratio of the internal reference voltage (1.2 V) and an external resistor (RSET) connected to  
BIASJ_A. When GSET is low (independent gain set mode), the full-scale output current for each DAC is  
determined by the ratio of the internal reference voltage (1.2 V) and separate external resistors (RSET) connected  
to BIASJ_A and BIASJ_B. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC  
output current that can range from 2 mA to 20 mA, depending on the value of RSET  
.
The DAC5672 is split into a digital and an analog portion, each of which is powered through its own supply pin.  
The digital section includes edge-triggered input latches and the decoder logic, while the analog section  
comprises both the current source array with its associated switches, and the reference circuitry.  
DAC Transfer Function  
Each of the DACs in the DAC5672 has a set of complementary current outputs, IOUT1 and IOUT2. The full-scale  
output current, IOUTFS, is the summation of the two complementary output currents:  
I
+ I  
) I  
OUTFS  
OUT1  
OUT2  
(1)  
The individual output currents depend on the DAC code and can be expressed as:  
Code  
16384  
ǒ Ǔ  
I
+ I  
 
OUT1  
OUTFS  
(2)  
(3)  
Code  
16384  
  ǒ16383 *  
Ǔ
I
+ I  
OUT2  
OUTFS  
where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the  
reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).  
V
REF  
I
+ 32   I  
+ 32   
OUTFS  
REF  
R
SET  
(4)  
In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage  
develops at each output according to:  
V
I
R
OUT1  
OUT1  
LOAD  
(5)  
(6)  
V
I
R
OUT2  
OUT2  
LOAD  
The value of the load resistance is limited by the output compliance specification of the DAC5672. To maintain  
specified linearity performance, the voltage for IOUT1 and IOUT2 must not exceed the maximum allowable  
compliance range.  
16  
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
The total differential output voltage is:  
V
V
V
OUTDIFF  
OUT1  
OUT2  
(7)  
(8)  
(
)
2
Code 16383  
16384  
V
+
  I  
  R  
OUTDIFF  
OUTFS  
LOAD  
Analog Outputs  
The DAC5672 provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of the  
analog output stage representing the differential topology is shown in Figure 21. The output impedance of IOUT1  
and IOUT2 results from the parallel combination of the differential switches, along with the current sources and  
associated parasitic capacitances.  
AVDD  
S(1)  
S(1)C  
S(2)  
S(2)C  
S(N)  
S(N)C  
Current Source Array  
IOUT1  
IOUT2  
R
LOAD  
R
LOAD  
Figure 21. Analog Outputs  
The signal voltage swing that may develop at the two outputs, IOUT1 and IOUT2, is limited by a negative and  
positive compliance. The negative limit of –1 V is given by the breakdown voltage of the CMOS process and  
exceeding it compromises the reliability of the DAC5672 (or even causes permanent damage). With the full-scale  
output set to 20 mA, the positive compliance equals 1.2 V. Note that the compliance range decreases to about 1  
V for a selected output current of IOUTFS = 2 mA. Care must be taken that the configuration of DAC5672 does not  
exceed the compliance range to avoid degradation of the distortion performance and integral linearity.  
Best distortion performance is typically achieved with the maximum full-scale output signal limited to  
approximately 0.5 VPP. This is the case for a 50-doubly-terminated load and a 20-mA full-scale output current.  
A variety of loads can be adapted to the output of the DAC5672 by selecting a suitable transformer while  
maintaining optimum voltage levels at IOUT1 and IOUT2. Furthermore, using the differential output configuration  
in combination with a transformer is instrumental for achieving excellent distortion performance. Common-mode  
errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly the case with  
high output frequencies.  
For those applications requiring the optimum distortion and noise performance, it is recommended to select a  
full-scale output of 20 mA. A lower full-scale range of 2 mA may be considered for applications that require low  
power consumption, but can tolerate a slight reduction in performance level.  
Output Configurations  
The current outputs of the DAC5672 allow for a variety of configurations. As mentioned previously, utilizing the  
converter’s differential outputs yield the best dynamic performance. Such a differential output circuit may consist  
of an RF transformer or a differential amplifier configuration. The transformer configuration is ideal for most  
applications with ac coupling, while op amps are suitable for a dc-coupled configuration.  
17  
 
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
The single-ended configuration may be considered for applications requiring a unipolar output voltage.  
Connecting a resistor from either one of the outputs to ground converts the output current into a  
ground-referenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V or  
op-amp configuration may be considered.  
Differential With Transformer  
Using an RF transformer provides a convenient way of converting the differential output signal into a  
single-ended signal while achieving excellent dynamic performance. The appropriate transformer must be  
carefully selected based on the output frequency spectrum and impedance requirements.  
The differential transformer configuration has the benefit of significantly reducing common-mode signals, thus  
improving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitable  
impedance ratio (winding ratio) the transformer can provide optimum impedance matching while controlling the  
compliance voltage for the converter outputs.  
Figure 22 and Figure 23 show 50-doubly-terminated transformer configurations with 1:1 and 4:1 impedance  
ratios, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable  
a dc-current flow. Applying a 20-mA full-scale output current would lead to a 0.5-VPP output for a 1:1 transformer  
and a 1-VPP output for a 4:1 transformer. In general, the 1:1 transformer configuration will have slightly better  
output distortion, but the 4:1 transformer will have 6 dB higher output power.  
50  
1:1  
IOUT1  
R
LOAD  
50 Ω  
AGND  
100 Ω  
IOUT2  
50 Ω  
Figure 22. Driving a Doubly-Terminated 50-Cable Using a 1:1 Impedance Ratio Transformer  
100  
4:1  
IOUT1  
R
LOAD  
50 Ω  
AGND  
IOUT2  
100 Ω  
Figure 23. Driving a Doubly-Terminated 50-Cable Using a 4:1 Impedance Ratio Transformer  
18  
 
 
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
Single-Ended Configuration  
Figure 24 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent  
load resistance of 25 . Node IOUT2 must be connected to AGND or terminated with a resistor of 25 to  
AGND. The nominal resistor load of 25 gives a differential output swing of 1 VPP when applying a 20-mA  
full-scale output current.  
IOUT1  
R
LOAD  
50  
IOUT2  
50 Ω  
25 Ω  
AGND  
Figure 24. Driving a Doubly-Terminated 50-Cable Using a Single-Ended Output  
Reference Operation  
Internal Reference  
The DAC5672 has an on-chip reference circuit which comprises a 1.2-V bandgap reference and two control  
amplifiers, one for each DAC. The full-scale output current, IOUTFS, of the DAC5672 is determined by the  
reference voltage, VREF, and the value of resistor RSET. IOUTFS can be calculated by:  
V
REF  
I
+ 32   I  
+ 32   
OUTFS  
REF  
R
SET  
(9)  
The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which is  
determined by the ratio of VREF and RSET (see Equation 9). The full-scale output current, IOUTFS, results from  
multiplying IREF by a fixed factor of 32.  
Using the internal reference, a 2-kresistor value results in a full-scale output of approximately 20 mA. Resistors  
with a tolerance of 1% or better should be considered. Selecting higher values, the output current can be  
adjusted from 20 mA down to 2 mA. Operating the DAC5672 at lower than 20-mA output currents may be  
desirable for reasons of reducing the total power consumption, improving the distortion performance, or  
observing the output compliance voltage limitations for a given load condition.  
It is recommended to bypass the EXTIO pin with a ceramic chip capacitor of 0.1 µF or more. The control  
amplifier is internally compensated and its small signal bandwidth is approximately 300 kHz.  
External Reference  
The internal reference can be disabled by simply applying an external reference voltage into the EXTIO pin,  
which in this case functions as an input. The use of an external reference may be considered for applications that  
require higher accuracy and drift performance or to add the ability of dynamic gain control.  
While a 0.1-µF capacitor is recommended to be used with the internal reference, it is optional for the external  
reference operation. The reference input, EXTIO, has a high input impedance (1 M) and can easily be driven  
by various sources. Note that the voltage range of the external reference must stay within the compliance range  
of the reference input.  
19  
 
DAC5672  
www.ti.com  
SLAS440NOVEMBER 2004  
Gain Setting Option  
The full-scale output current on the DAC5672 can be set two ways: either for each of the two DAC channels  
independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42)  
must be low (that is, connected to AGND). In this mode, two external resistors are required — one RSET  
connected to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user  
has the flexibility to set and adjust the full-scale output current for each DAC independently, allowing for the  
compensation of possible gain mismatches elsewhere within the transmit signal path.  
Alternatively, bringing the GSET pin high (that is, connected to AVDD), the DAC5672 switches into the  
simultaneous gain set mode. Now the full-scale output current of both DAC channels is determined by only one  
external RSET resistor connected to the BIASJ_A pin. The resistor at the BIASJ_B pin may be removed; however,  
this is not required since this pin is not functional in this mode and the resistor has no effect on the gain equation.  
Sleep Mode  
The DAC5672 features a power-down function which can reduce the total supply current to approximately 3.1  
mA over the specified supply range if no clock is present. Applying a logic high to the SLEEP pin initiates the  
power-down mode, while a logic low enables normal operation. When left unconnected, an internal active  
pulldown circuit enables the normal operation of the converter.  
20  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
DAC5672IPFB  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TQFP  
PFB  
48  
48  
48  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
DAC5672IPFBR  
DAC5672IPFBRG4  
TQFP  
TQFP  
PFB  
PFB  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
1000  
None  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998  
PFB (S-PQFP-G48)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
0,50  
M
0,08  
36  
25  
37  
24  
48  
13  
0,13 NOM  
1
12  
5,50 TYP  
7,20  
SQ  
Gage Plane  
6,80  
9,20  
SQ  
8,80  
0,25  
0,05 MIN  
0°7°  
1,05  
0,95  
0,75  
0,45  
Seating Plane  
0,08  
1,20 MAX  
4073176/B 10/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
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