DAC7614E各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

DAC7614

®

DAC7614

Quad, Serial Input, 12-Bit, Voltage Output

DIGITAL-TO-ANALOG CONVERTER

APPLICATIONS

● ATE PIN ELECTRONICS

FEATURES

● LOW POWER: 20mW

● PROCESS CONTROL

● UNIPOLAR OR BIPOLAR OPERATION

● SETTLING TIME: 10µs to 0.012%

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● 12-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● DATA ACQUISITION SYSTEMS

● USER SELECTABLE RESET TO MID-

SCALE OR ZERO-SCALE

● SECOND-SOURCE for DAC8420

● SMALL 20-LEAD SSOP PACKAGE

DESCRIPTION

The DAC7614 is a quad, serial input, 12-bit, voltage

output digital-to-analog converter (DAC) with guar-

anteed 12-bit monotonic performance over the –40°C

to +85°C temperature range. An asynchronous reset

clears all registers to either mid-scale (800_H) or zero-

scale (000_H), selectable via the RESETSEL pin. The

device can be powered from a single +5V supply or

from dual +5V and –5V supplies.

Low power and small size makes the DAC7614 ideal

for process control, data acquisition systems, and

closed-loop servo-control. The device is available in

16-pin plastic DIP, 16-lead SOIC, or 20-lead SSOP

packages, and is guaranteed over the –40°C to +85°C

temperature range.

V_DD

V_REFH

GND

DAC

Register A

DAC A

V_OUTA

SDI

DAC

Register B

DAC B

DAC C

Serial-to-

Parallel

Shift

V_OUTB

V_OUTC

V_OUTD

12

Register

DAC

Register C

CLK

CS

DAC

Select

DAC

Register D

DAC D

V_REFLV_SS

LOADDACS

RESET

RESETSEL

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

• Tel: (520) 746-1111

Twx: 910-952-1111

•

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP Telex: 066-6491

•

FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

•

PDS-1445C

Printed in U.S.A. December, 1998

SPECIFICATIONS

At T_A= –40°C to +85°C, V_DD= +5V, V_SS= –5V, V_REFH= +2.5V, and V_REFL= –2.5V, unless otherwise noted.

DAC7614E, P, U

DAC7614EB, PB, UB

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ACCURACY

Linearity Error⁽¹⁾

V_SS= 0V or –5V

±2

±1

LSB⁽²⁾

LSB

Linearity Matching⁽³⁾

Differential Linearity Error

Monotonicity

LSB

12

✻

Bits

Zero-Scale Error

Code = 000_H

Code = FFF_H

±4

5

✻

LSB

Zero-Scale Drift

Zero-Scale Matching⁽³⁾

2

✻

ppm/°C

LSB

±2

±4

±2

±8

10

±4

±8

±4

±1

✻

Full-Scale Error

LSB

Full-Scale Matching⁽³⁾

Zero-Scale Error

±1

✻

LSB

Code = 00A_H, V_SS= 0V

V_SS= 0V

LSB

Zero-Scale Drift

Zero-Scale Matching⁽³⁾

5

✻

ppm/°C

LSB

V_SS= 0V

±2

✻

Full-Scale Error

Code = FFF_H, V_SS= 0V

V_SS= 0V

LSB

Full-Scale Matching⁽³⁾

Power Supply Rejection

±2

LSB

30

ppm/V

ANALOG OUTPUT

Voltage Output⁽⁴⁾

Output Current

V_SS= 0V or –5V

No Oscillation

V_REFL

–1.25

V_REFH

+1.25

✻

V

mA

pF

Load Capacitance

Short-Circuit Current

Short-Circuit Duration

100

✻

+5, –15

Indefinite

mA

REFERENCE INPUT

V_REFHInput Range

V_REFLInput Range

V_SS= 0V or –5V

V_SS= 0V

V_REFL+1.25

+2.5

✻

V

0

V_REFH–1.25

V_SS= –5V

–2.5

DYNAMIC PERFORMANCE

Settling Time⁽⁵⁾

To ±0.012%

Full-Scale Step

5

10

✻

µs

Channel-to-Channel Crosstalk

0.1

LSB

On Any Other DAC, R_L= 2kΩ

Bandwidth: 0Hz to 1MHz

Output Noise Voltage

40

✻

nV/√Hz

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels

V_IH

TTL-Compatible CMOS

✻

| I_IH| ≤ 10µA

| I_IL| ≤ 10µA

2.4

V_DD+0.3

✻

V

V_IL

–0.3

0.8

Data Format

Straight Binary

✻

POWER SUPPLY REQUIREMENTS

V_DD

4.75

5.25

–4.75

1.9

✻

V

V_SS

If V_SS≠ 0V

–5.25

V

I_DD

1.5

–1.6

15

✻

mA

mW

I_SS

–2.1

–40

✻

Power Dissipation

V_SS= –5V

V_SS= 0V

20

10

✻

7.5

TEMPERATURE RANGE

Specified Performance

+85

✻

°C

✻ Specification same as grade to the left.

NOTES: (1) If V_SS= 0V, specification applies at code 00A_Hand above. (2) LSB means Least Significant Bit, with V_REFHequal to +2.5V and V_REFLequal to –2.5V,

one LSB is 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error.

(5) If V_SS= –5V, full-scale step from code 000_Hto FFF_Hor vice-versa. If V_SS= 0V, full-scale positive step from code 000_Hto FFF_Hand negative step from code

FFF_Hto 00A_H.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

®

2

DAC7614

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

V_DDto V_SS........................................................................... –0.3V to +11V

V_DDto GND ........................................................................ –0.3V to +5.5V

V

_REFLto V_SS...............................................................–0.3V to (V_DD– V_SS

V_DDto V_REFH..............................................................–0.3V to (V_DD– V_SS

V_REFHto V_REFL............................................................ –0.3V to (V_DD– V_SS

)

Digital Input Voltage to GND ...................................... –0.3V to V_DD+ 0.3V

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ......................................... –40°C to +85°C

Storage Temperature Range .......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION

MAXIMUM

LINEARITY

ERROR

MAXIMUM

DIFFERENTIAL

LINEARITY

(LSB)

PACKAGE

DRAWING

NUMBER⁽¹⁾

SPECIFICATION

TEMPERATURE

RANGE

ORDERING

NUMBER⁽²⁾

TRANSPORT

MEDIA

PRODUCT

(LSB)

PACKAGE

DAC7614P

DAC7614PB

±2

±1

"

16-Pin DIP

180

"

–40°C to +85°C

DAC7614P

DAC7614PB

Rails

"

DAC7614U

±2

"

±1

"

±1

"

±1

"

16-Lead SOIC

211

"

211

"

–40°C to +85°C

DAC7614U

DAC7614U/1K

DAC7614UB

Rails

Tape and Reel

Rails

"

DAC7614UB

16-Lead SOIC

–40°C to +85°C

"

DAC7614UB/1K

Tape and Reel

DAC7614E

±2

"

±1

"

±1

"

±1

"

20-Lead SSOP

334

"

334

"

–40°C to +85°C

DAC7614E

DAC7614E/1K

DAC7614EB

Rails

Tape and Reel

Rails

"

DAC7614EB

20-Lead SSOP

–40°C to +85°C

"

DAC7614EB/1K

Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are

available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7614EB/1K” will get a single

1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

®

3

DAC7614

PIN CONFIGURATION—P, U Packages

PIN CONFIGURATION—E Package

Top View

SSOP

Top View

PDIP, SOIC

V_DD

V_OUTD

V_OUTC

V_REFL

V_REFH

V_OUTB

V_OUTA

V_SS

1

2

3

4

5

6

7

8

16 RESETSEL

V_DD

V_OUTD

V_OUTC

V_REFL

NIC

1

2

3

4

5

6

7

8

9

20 RESETSEL

19 RESET

18 LOADDACS

17 NIC

15 RESET

14 LOADDACS

13 NIC

DAC7614P, U

12 CS

16 NIC

DAC7614E

11 CLK

NIC

15 NIC

10 SDI

V_REFH

V_OUTB

V_OUTA

14 CS

9

GND

13 CLK

12 SDI

V_SS10

11 GND

PIN DESCRIPTIONS—P, U Packages

PIN DESCRIPTIONS—E Package

LABEL

DESCRIPTION

LABEL

DESCRIPTION

1

2

3

4

V_DD

Positive Analog Supply Voltage, +5V nominal.

DAC D Voltage Output

1

2

3

4

V_DD

Positive Analog Supply Voltage, +5V nominal.

DAC D Voltage Output

V_OUTD

V_OUTC

V_REFL

V_OUTD

V_OUTC

V_REFL

DAC C Voltage Output

Reference Input Voltage Low. Sets minimum out-

put voltage for all DACs.

Reference Input Voltage Low. Sets minimum out-

put voltage for all DACs.

5

V_REFH

Reference Input Voltage High. Sets maximum out-

put voltage for all DACs.

5

6

7

NIC

Not Internally Connected.

6

7

8

V_OUTB

V_OUTA

V_SS

DAC B Voltage Output

DAC A Voltage Output

V_REFH

Reference Input Voltage High. Sets maximum out-

put voltage for all DACs.

Negative Analog Supply Voltage, 0V or –5V nomi-

nal.

8

V_OUTB

V_OUTA

V_SS

DAC B Voltage Output.

DAC A Voltage Output.

9

GND

SDI

Ground

10

Negative Analog Supply Voltage, 0V or –5V nomi-

nal.

10

11

12

13

14

Serial Data Input

Serial Data Clock

Chip Select Input

Not Internally Connected.

CLK

11

12

13

14

15

16

17

18

GND

SDI

Ground

CS

Serial Data Input

NIC

CLK

Serial Data Clock

LOADDACS

The selected DAC register becomes transparent

when LOADDACS is LOW. It is in the latched state

when LOADDACS is HIGH.

CS

Chip Select Input

NIC

Not Internally Connected.

NIC

15

16

RESET

Asynchronous Reset Input. Sets all DAC registers

to either zero-scale (000_H) or mid-scale (800_H)

when LOW. RESETSEL determines which code is

active.

NIC

LOADDACS

The selected DAC register becomes transparent

when LOADDACS is LOW. It is in the latched state

when LOADDACS is HIGH.

RESETSEL

When LOW, a LOW on RESET will cause all DAC

registers to be set to code 000_H. When RESETSEL

is HIGH, a LOW on RESET will set the registers to

code 800_H.

19

20

RESET

Asynchronous Reset Input. Sets all DAC registers

to either zero-scale (000_H) or mid-scale (800_H)

when LOW. RESETSEL determines which code is

active.

RESETSEL

When LOW, a LOW on RESET will cause all DAC

registers to be set to code 000_H. When RESETSEL

is HIGH, a LOW on RESET will set the registers to

code 800_H.

®

4

DAC7614

TYPICAL PERFORMANCE CURVES: V_SS= 0V

At T_A= +25°C, V_DD= +5V, V_SS= 0V, V_REFH= +2.5V, and V_REFL= 0V, representative unit, unless otherwise specified.

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B)

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A)

0.50

0.25

0.50

0.25

0.00

–0.25

–0.50

0.50

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

–0.25

–0.50

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Digital Input Code

LINEARITY ERROR and DIFFERENTIAL

LINEARITY ERROR vs CODE

(DAC D)

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C)

0.50

0.25

0.50

0.25

0.00

–0.25

–0.50

0.50

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

–0.25

–0.50

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Digital Input Code

LINEARITY ERROR vs CODE

(DAC A, –40°C and +85°C)

LINEARITY ERROR vs CODE

(DAC B, –40°C and +85°C)

0.50

0.25

0.50

+85°C

–40°C

+85°C

–40°C

0.25

0.00

–0.25

–0.50

0.50

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

–0.25

–0.50

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Digital Input Code

®

5

DAC7614

TYPICAL PERFORMANCE CURVES: V_SS= 0V (CONT)

At T_A= +25°C, V_DD= +5V, V_SS= 0V, V_REFH= +2.5V, and V_REFL= 0V, representative unit, unless otherwise specified.

LINEARITY ERROR vs CODE

(DAC D, –40°C and +85°C)

LINEARITY ERROR vs CODE

(DAC C, –40°C and +85°C)

0.50

0.25

0.50

0.25

+85°C

–40°C

+85°C

–40°C

0.00

–0.25

–0.50

0.50

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

–0.25

–0.50

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Digital Input Code

POSITIVE SLEW RATE and SETTLING TIME

NEGATIVE SLEW RATE and SETTLING TIME

2.75

9

2.75

9

5V

2.25

1.75

1.25

0.75

0.25

–0.25

6

2.25

1.75

1.25

0.75

0.25

–0.25

6

LOADDACS

0V

3

B

A

0

B

5V

–3

–6

–9

–3

–6

–9

LOADDACS

0V

–2

–1

0

1

2

3

4

5

6

7

8

–2

–1

0

1

2

3

4

5

6

7

8

Time (µs)

®

6

DAC7614

TYPICAL PERFORMANCE CURVES: V_SS= –5V

At T_A= +25°C, V_DD= +5V, V_SS= –5V, V_REFH= +2.5V, and V_REFL= –2.5V, representative unit, unless otherwise specified.

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B)

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A)

0.50

0.25

0.50

0.25

0.00

–0.25

–0.50

0.50

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

–0.25

–0.50

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Digital Input Code

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D)

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C)

0.50

0.25

0.00

–0.25

–0.50

0.50

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

–0.25

–0.50

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Digital Input Code

LINEARITY ERROR vs CODE

(DAC B, –40°C and +85°C)

LINEARITY ERROR vs CODE

(DAC A, –40°C and +85°C)

0.50

0.25

0.50

+85°C

–40°C

+85°C

–40°C

0.25

0.00

–0.25

–0.50

0.50

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

–0.25

–0.50

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Digital Input Code

®

7

DAC7614

TYPICAL PERFORMANCE CURVES: V_SS= –5V (CONT)

At T_A= +25°C, V_DD= +5V, V_SS= –5V, V_REFH= +2.5V, and V_REFL= –2.5V, representative unit, unless otherwise specified.

LINEARITY ERROR vs CODE

(DAC C, –40°C and +85°C)

LINEARITY ERROR vs CODE

(DAC D, –40˚C and +85˚C)

0.50

0.25

0.50

0.25

+85°C

–40°C

+85˚C

0.00

–0.25

–0.50

0.50

–0.25

–0.50

0.50

–40˚C

0.25

0.00

–0.25

–0.50

–0.25

–0.50

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Digital Input Code

POSITIVE SLEW RATE and SETTLING TIME

NEGATIVE SLEW RATE and SETTLING TIME

3

6

3

6

5V

2

1

4

2

1

4

LOADDACS

0V

2

A

B

A

0

B

5V

–1

–2

–3

–2

–4

–6

–1

–2

–3

–2

–4

–6

LOADDACS

0V

–2

–1

0

1

2

3

4

5

6

7

8

–2

–1

0

1

2

3

4

5

6

7

8

Time (µs)

V_REFHCURRENT vs CODE

V_REFLCURRENT vs CODE

(All DACs Set to Indicated Code)

600

500

400

300

200

100

0

–100

–200

–300

–400

–500

–600

000_H

400_H

800_H

C00_H

FFF_H

000_H

400_H

800_H

C00_H

FFF_H

Digital Input Code

®

8

DAC7614

ANALOG OUTPUTS

THEORY OF OPERATION

When V_SS= –5V (dual supply operation), the output

amplifier can swing to within 2.25V of the supply rails,

over the –40°C to +85°C temperature range. With V_SS= 0V

(single-supply operation), the output can swing to ground.

Note that the settling time of the output op amp will be

longer with voltages very near ground. Also, care must be

taken when measuring the zero-scale error when V_SS= 0V.

If the output amplifier has a negative offset, the output

voltage may not change for the first few digital input codes

(000_H, 001_H, 002_H, etc.) since the output voltage cannot

swing below ground.

The DAC7614 is a quad, serial input, 12-bit, voltage output

DAC. The architecture is a classic R-2R ladder configuration

followed by an operational amplifier that serves as a buffer.

Each DAC has its own R-2R ladder network and output op

amp, but all share the reference voltage inputs. The minimum

voltage output (“zero-scale”) and maximum voltage output

(“full-scale”) are set by external voltage references (V_REFL

and V_REFH, respectively). The digital input is a 16-bit serial

word that contains the 12-bit DAC code and a 2-bit address

code that selects one of the four DACs (the two remaining

bits are unused). The converter can be powered from a single

+5V supply or a dual ±5V supply. Each device offers a reset

function which immediately sets all DAC output voltages and

internal registers to either zero-scale (code 000_H) or mid-scale

(code 800_H). The reset code is selected by the state of the

RESETSEL pin (LOW = 000_H, HIGH = 800_H). See Figures

1 and 2 for the basic operation of the DAC7614.

The behavior of the output amplifier can be critical in some

applications. Under short-circuit conditions (DAC output

shorted to ground), the output amplifier can sink a great deal

more current than it can source. See the Specifications table

for more details concerning short-circuit current.

+5V

DAC7614⁽¹⁾

+

1µF to 10µF

0.1µF

1

2

3

4

5

6

7

8

V_DD

RESETSEL 16

Reset DACs⁽²⁾

V_OUTD

V_OUTC

V_REFL

V_REFH

V_OUTB

V_OUTA

V_SS

RESET 15

LOADDACS 14

NIC 13

0V to +2.5V

Update Selected Register

+2.500V

Chip Select

Clock

CS 12

CLK 11

0V to +2.5V

Serial Data In

SDI 10

GND

9

NOTES: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers

to code 000_H(0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800_H(1.25V).

FIGURE 1. Basic Single-Supply Operation of the DAC7614.

DAC7614⁽¹⁾

+5V

+

1µF to 10µF

0.1µF

+5V

1

2

3

4

5

6

7

8

V_DD

RESETSEL 16

Reset DACs⁽²⁾

V_OUTD

V_OUTC

V_REFL

V_REFH

V_OUTB

V_OUTA

V_SS

RESET 15

LOADDACS 14

NIC 13

–2.5V to +2.5V

Update Selected Register

–2.500V

0.1µF

Chip Select

Clock

CS 12

+2.500V

CLK 11

Serial Data In

SDI 10

–2.5V to +2.5V

GND

9

–5V

1µF to 10µF

0.1µF

+

NOTES: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal register

to code 800_H(0V). If RESETSEL is LOW, RESET LOW sets all internal registers to code 000_H(–2.5V).

FIGURE 2. Basic Dual-Supply Operation of the DAC7614.

®

9

DAC7614

REFERENCE INPUTS

SYMBOL

DESCRIPTION

MIN

TYP MAX UNITS

The reference inputs, V_REFLand V_REFH, can be any voltage

between V_SS+ 2.25V and V_DD– 2.25V provided that

V_REFHis at least 1.25V greater than V_REFL. The minimum

output of each DAC is equal to V_REFL– 1LSB plus a small

offset voltage (essentially, the offset of the output op amp).

The maximum output is equal to V_REFHplus a similar

offset voltage. Note that V_SS(the negative power supply)

must either be connected to ground or must be in the range

of –4.75V to –5.25V. The voltage on V_SSsets several bias

points within the converter. If V_SSis not in one of these two

configurations, the bias values may be in error and proper

operation of the device is not guaranteed.

t_DS

Data Valid to CLK Rising

Data Held Valid after CLK Rises

CLK HIGH

25

20

30

50

55

15

ns

µs

t_DH

t_CH

t_CL

CLK LOW

t_CSS

t_CSH

t_LD1

t_LD2

t_LDDW

t_RSSH

t_RSTW

t_S

CS LOW to CLK Rising

CLK HIGH to CS Rising

LOADDACS HIGH to CLK Rising 40

CLK Rising to LOADDACS LOW

LOADDACS LOW Time

RESETSEL Valid to RESET LOW

RESET LOW Time

15

45

25

70

10

Settling Time

The current into the reference inputs depends on the DAC

output voltages and can vary from a few microamps to

approximately 0.6 milliamp. Bypassing the reference volt-

age or voltages with a 0.1µF capacitor placed as close as

possible to the DAC7614 package is strongly recommended.

TABLE I. Timing Specifications (T_A= –40°C to +85°C).

asynchronous reset input (RESET) is provided to simplify

start-up conditions, periodic resets, or emergency resets to a

known state.

DIGITAL INTERFACE

The DAC code and address are provided via a 16-bit serial

interface as shown in Figure 3. The first two bits select the

DAC register that will be updated when LOADDACS goes

LOW (see Table II). The next two bits are not used. The last

12 bits is the DAC code which is provided, most significant

bit first.

Figure 3 and Table I provide the basic timing for the

DAC7614. The interface consists of a serial clock (CLK),

serial data (SDI), and a load DAC signal (LOADDACS). In

addition, a chip select (CS) input is available to enable serial

communication when there are multiple serial devices. An

(MSB)

(LSB)

SDI

A1

A0

X

D11

D10

D9

D3

D2

D1

D0

CLK

CS

t_CSH

t

css

t_LD2

t_LD1

LOADDAC

t_LDDW

t_DS

t_DH

SDI

t_CL

t_CH

CLK

t_LDDW

LOADDAC

V_OUT

t_S

1 LSB

ERROR BAND

1 LSB

ERROR BAND

t_RSTW

RESET

t_RSSH

RESETSEL

FIGURE 3. DAC7614 Timing.

®

10

DAC7614

Note that CS and CLK are combined with an OR gate and

the output controls the serial-to-parallel shift register inter-

nal to the DAC7614 (see the block diagram on the front of

this data sheet). These two inputs are completely inter-

changeable. In addition, care must be taken with the state of

CLK when CS rises at the end of a serial transfer. If CLK is

LOW when CS rises, the OR gate will provide a rising edge

to the shift register, shifting the internal data one additional

bit. The result will be incorrect data and possible selection of

the wrong DAC.

STATE OF

SELECTED

DAC

SELECTED

DAC

REGISTER

A1

A0

LOADDACS RESET

REGISTER

L⁽¹⁾

L

H

L

H

L

A

B

Transparent

(All Latched)

Reset⁽³⁾

H

L

C

H

X

L

D

X⁽²⁾

X

H

X

NONE

ALL

NOTES: (1) L = Logic LOW. (2) X = Don’t Care. (3) Resets to either 000H or

800_H, per the RESETSEL state (LOW = 000_H, HIGH = 800_H). When RESET

rises, all registers that are in their latched state retain the reset value.

If both CS and CLK are used, then CS should rise only when

CLK is HIGH. If not, then either CS or CLK can be used to

operate the shift register. See Table III for more information.

TABLE II. Control Logic Truth Table.

Digital Input Coding

CS⁽¹⁾

CLK⁽¹⁾LOADDACS

RESET

SERIAL SHIFT REGISTER

The DAC7614 input data is in Straight Binary format. The

output voltage is given by the following equation:

H⁽²⁾

L⁽⁴⁾

L

X⁽³⁾

L

H

No Change

(V_REFH– V_REFL) • N

(5)

↑

H

Advanced One Bit

No Change

V_OUT= V_REFL

+

4096

↑

L

X

H

H⁽⁶⁾

L⁽⁷⁾

H

where N is the digital input code (in decimal). This equation

does not include the effects of offset (zero-scale) or gain

(full-scale) errors.

L⁽⁸⁾

No Change

NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =

Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH

value is suggested in order to avoid a “false clock” from advancing the shift

register and changing the shift register. (7) If data is clocked into the serial

register while LOADDACS is LOW, the selected DAC register will change as

the shift register bits “flow” through A1 and A0. This will corrupt the data in

each DAC register that has been erroneously selected. (8) RESET LOW

causes no change in the contents of the serial shift register.

TABLE III. Serial Shift Register Truth Table.

®

11

DAC7614

The power applied to V_DD(as well as V_SS, if not grounded)

should be well regulated and low noise. Switching power

supplies and DC/DC converters will often have high-fre-

quency glitches or spikes riding on the output voltage. In

addition, digital components can create similar high-fre-

quency spikes as their internal logic switches states. This

noise can easily couple into the DAC output voltage through

various paths between the power connections and analog

output.

LAYOUT

A precision analog component requires careful layout, ad-

equate bypassing, and clean, well-regulated power supplies.

As the DAC7614 offers single-supply operation, it will often

be used in close proximity with digital logic, microcontrollers,

microprocessors, and digital signal processors. The more

digital logic present in the design and the higher the switch-

ing speed, the more difficult it will be to achieve good

performance from the converter.

As with the GND connection, V_DDshould be connected to

a +5V power supply plane or trace that is separate from the

connection for digital logic until they are connected at the

power entry point. In addition, the 1µF to 10µF and 0.1µF

capacitors shown in Figure 4 are strongly recommended. In

some situations, additional bypassing may be required, such

as a 100µF electrolytic capacitor or even a “Pi” filter made

up of inductors and capacitors—all designed to essentially

lowpass filter the +5V supply, removing the high frequency

noise (see Figure 4).

Because the DAC7614 has a single ground pin, all return

currents, including digital and analog return currents, must

flow through the GND pin. Ideally, GND would be con-

nected directly to an analog ground plane. This plane would

be separate from the ground connection for the digital

components until they were connected at the power entry

point of the system (see Figure 4).

Digital Circuits

+5V

Power Supply

Ground

+5V

DAC7614

Ground

V_DD

100µF

+

1µF to

10µF

0.1µF

GND

Optional

Other

Analog

Components

FIGURE 4. Suggested Power and Ground Connections for a DAC7614 Sharing a +5V Supply with a Digital System.

®

12

DAC7614

型号:	DAC7614E
是否Rohs认证：	不符合
生命周期：	Transferred
Reach Compliance Code：	unknown
风险等级：	5.67
Is Samacsys：	N
最大模拟输出电压：	2.5 V
最小模拟输出电压：	-2.5 V
转换器类型：	D/A CONVERTER
输入位码：	BINARY
输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0
最大线性误差 (EL)：	0.0488%
标称负供电电压：	-5 V
位数：	12
功能数量：	4
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP20,.3
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
电源：	+-5 V
认证状态：	Not Qualified
最大稳定时间：	10 µs
标称安定时间 (tstl)：	5 µs
子类别：	Other Converters
最大压摆率：	4 mA
标称供电电压：	5 V
表面贴装：	YES
技术：	BICMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
Base Number Matches：	1

电子百科

产品导航

产品型号DAC7614E的概述

产品型号DAC7614E的Datasheet PDF文件预览

DAC7614E相关产品

DAC7614E相关文章

IC37:专业IC行业平台