DAC7725NB应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

®

DAC7724

DAC7725

For most current data sheet and other product

information, visit www.burr-brown.com

12-Bit Quad Voltage Output

DIGITAL-TO-ANALOG CONVERTER

FEATURES

DESCRIPTION

The DAC7724 and DAC7725 are 12-bit quad voltage

output digital-to-analog converters with guaranteed

12-bit monotonic performance over the specified tem-

perature range. They accept 12-bit parallel input data,

have double-buffered DAC input logic (allowing simul-

taneous update of all DACs), and provide a readback

mode of the internal input registers. An asynchronous

reset clears all registers to a mid-scale code of 800_H

(DAC7724) or to a zero-scale of 000_H(DAC7725). The

DAC7724 and DAC7725 can operate from a single

+15V supply, or from +15V and –15V supplies.

● LOW POWER: 250mW max

● SINGLE SUPPLY OUTPUT RANGE: +10V

● DUAL SUPPLY OUTPUT RANGE: ±10V

● SETTLING TIME: 10µs to 0.012%

● 12-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● RESET TO MID-SCALE (DAC7724) OR

ZERO-SCALE (DAC7725)

● DATA READBACK

● DOUBLE-BUFFERED DATA INPUTS

Low power and small size per DAC make the DAC7724

and DAC7725 ideal for automatic test equipment,

DAC-per-pin programmers, data acquisition systems,

and closed-loop servo-control. The DAC7724 and

DAC7725 are available in a PLCC-28 or a SO-28

package, and offer guaranteed specifications over the

–40°C to +85°C temperature range.

APPLICATIONS

● PROCESS CONTROL

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

V_DD

V_CCV_REFH

GND

12

I/O

Buffer

Input

Register A

DAC

Register A

V_OUTA

DB0-DB11

DAC A

Input

Register B

DAC

Register B

DAC B

DAC C

DAC D

V_OUTB

V_OUTC

V_OUTD

A0

A1

Input

Register C

DAC

Register C

Control

Logic

R/W

CS

Input

Register D

DAC

Register D

V_REFL

V_SS

RESET LDAC

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

• Tel: (520) 746-1111

Twx: 910-952-1111

•

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP Telex: 066-6491

•

FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

•

PDS-1517B

Printed in U.S.A. April, 2000

SPECIFICATION (DUAL SUPPLY)

At T_A= –40°C to +85°C, V_CC= +15V, V_DD= +5V, V_SS= –15V, V_REFH= +10V, V_REFL= –10V, unless otherwise noted.

DAC7724N, U

DAC7725N, U

DAC7724NB, UB

DAC7725NB, UB

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ACCURACY

Linearity Error

±2

±1

LSB⁽¹⁾

LSB

Linearity Matching⁽²⁾

Differential Linearity Error

Monotonicity

LSB

T_MINto T_MAX

Code = 000_H

12

✻

Bits

Zero-Scale Error

±2

✻

LSB

Zero-Scale Drift

Zero-Scale Matching⁽²⁾

1

✻

ppm/°C

LSB

±2

±1

✻

Full-Scale Error

Code = FFF_H

At Full Scale

LSB

Full-Scale Matching⁽²⁾

Power Supply Sensitivity

±1

LSB

10

ppm/V

ANALOG OUTPUT

Voltage Output⁽³⁾

Output Current

V_REFL

V_REFH

✻

V

±5

mA

pF

Load Capacitance

Short-Circuit Current

Short-Circuit Duration

No Oscillation

500

±20

✻

mA

To V_SS, V_CC, or GND

Indefinite

REFERENCE INPUT

V_REFHInput Range

V_REFLInput Range

V_REFL+1.25

–10

+10

✻

V

V_REFH– 1.25

V

Ref High Input Current

Ref Low Input Current

–0.5

–3.5

3.0

0

mA

DYNAMIC PERFORMANCE

Settling Time

To ±0.012%, 20V Output Step

8

0.25

2

10

✻

µs

LSB

Channel-to-Channel Crosstalk

Digital Feedthrough

Full-Scale Step

nV-s

Output Noise Voltage

f = 10kHz

65

✻

nV/√Hz

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels

V_IH

TTL-Compatible CMOS

✻

I_IH≤ ±10µA

I_IL≤ ±10µA

I_OH= –0.8mA

I_OL= 1.6mA

2.4

V_DD+0.3

0.8

✻

V

V_IL

–0.3

3.6

V_OH

V_DD

V_OL

0.0

0.4

Data Format

Straight Binary

✻

POWER SUPPLY REQUIREMENTS

V_DD

+4.75

+14.25

–14.25

+5.25

+15.75

–15.75

✻

V

V_CC

V_SS

V

I_DD

50

6

✻

µA

mA

mW

I_CC

8.5

I_SS

–8

–6

180

✻

Power Dissipation

250

✻

TEMPERATURE RANGE

Specified Performance

–40

+85

✻

°C

NOTES: (1) LSB means Least Significant Bit, when V_REFHequals +10V and V_REFLequals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within

the specified error band. (3) Ideal output voltage, does not take into account zero or full-scale error.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

®

2

DAC7724, 7725

SPECIFICATION (SINGLE SUPPLY)

At T_A= –40°C to +85°C, V_CC= +15V, V_DD= +5V, V_SS= GND, V_REFH= +10V, V_REFL= 0V, unless otherwise noted.

DAC7724N, U

DAC7725N, U

DAC7724NB, UB

DAC7725NB, UB

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ACCURACY

Linearity Error⁽¹⁾

±2

±1

LSB⁽²⁾

LSB

Linearity Matching⁽³⁾

Differential Linearity Error

Monotonicity

LSB

T_MINto T_MAX

Code = 004_H

12

✻

Bits

Zero-Scale Error

±4

✻

LSB

Zero-Scale Drift

Zero-Scale Matching⁽³⁾

2

✻

ppm/°C

LSB

±4

±2

✻

Full-Scale Error

Code = FFF_H

At Full Scale

LSB

Full-Scale Matching⁽³⁾

Power Supply Sensitivity

±2

LSB

20

ppm/V

ANALOG OUTPUT

Voltage Output⁽⁴⁾

Output Current

V_REFL

V_REFH

✻

V

±5

mA

pF

Load Capacitance

Short-Circuit Current

Short-Circuit Duration

No Oscillation

500

±20

✻

mA

To V_CCor GND

Indefinite

REFERENCE INPUT

V_REFHInput Range

V_REFLInput Range

V_REFL+1.25

+10

✻

V

0

V_REFH– 1.25

V

Ref High Input Current

Ref Low Input Current

–0.3

–2.0

1.5

0

mA

DYNAMIC PERFORMANCE

Settling Time⁽⁵⁾

To ±0.012%, 10V Output Step

8

0.25

2

10

✻

µs

LSB

Channel-to-Channel Crosstalk

Digital Feedthrough

nV-s

Output Noise Voltage

f = 10kHz

65

✻

nV/√Hz

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels

V_IH

TTL-Compatible CMOS

✻

I_IH≤ ±10µA

I_IL≤ ±10µA

2.4

V_DD+0.3

0.8

✻

V

V_IL

–0.3

3.6

V_OH

I_OH= –0.8mA

I_OL= 1.6mA

V_DD

V_OL

0.0

0.4

Data Format

Straight Binary

✻

POWER SUPPLY REQUIREMENTS

V_DD

+4.75

14.25

+5.25

15.75

✻

V

V_CC

I_DD

50

3.0

45

✻

µA

mA

mW

I_CC

Power Dissipation

TEMPERATURE RANGE

Specified Performance

–40

+85

✻

°C

NOTES: (1) If V_SS= 0V, specification applies at code 004_Hand above. (2) LSB means Least Significant Bit, when V_REFHequals +10V and V_REFLequals 0V, then

one LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error.

(5) Full-scale positive 10V step and negative step from code FFF_Hto 004_H.

®

3

DAC7724, 7725

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

V_CCto V_SS........................................................................... –0.3V to +32V

V_CCto GND ......................................................................... –0.3V to +16V

V_SSto GND ......................................................................... +0.3V to –16V

V_DDto GND ............................................................................. –0.3V to 6V

V_REFH to GND ....................................................................... –9V to +11V

V_REFL to GND (V_SS= –15V) ................................................. –11V to +9V

V_REFL to GND (V_SS= 0V) .................................................... –0.3V to +9V

V_REFHto V_REFL....................................................................... –1V to +22V

Digital Input Voltage to GND ................................... –0.3V to V_DD+ 0.3V

Digital Output Voltage to GND ................................. –0.3V to V_DD+ 0.3V

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range ......................................... –65°C to +150°C

Lead Temperature (soldering, 10s)............................................... +300°C

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION

MAXIMUM

LINEARITY

ERROR

MAXIMUM

DIFFERENTIAL

NONLINEARITY ERROR

(LSB)

PACKAGE

DRAWING

NUMBER

SPECIFICATION

TEMPERATURE

RANGE

ORDERING

NUMBER⁽¹⁾

TRANSPORT

MEDIA

PRODUCT

(LSB)

PACKAGE

DAC7724N

±2

"

±1

"

±2

"

±1

"

±2

"

±1

"

±2

"

±1

"

±1

"

±1

"

±1

"

±1

"

±1

"

±1

"

±1

"

±1

"

PLCC-28

251

"

251

"

217

"

217

"

251

"

251

"

217

"

217

"

–40°C to +85°C

DAC7724N

DAC7724N/750

DAC7724NB

DAC7724NB/750

DAC7724U

DAC7724U/1K

DAC7724UB

DAC7724UB/1K

DAC7725N

DAC7725N/750

DAC7725NB

DAC7725NB/750

DAC7725U

DAC7725U/1K

DAC7725UB

DAC7725UB/1K

Rails

Tape and Reel

Rails

Tape and Reel

Rails

Tape and Reel

Rails

Tape and Reel

Rails

Tape and Reel

Rails

Tape and Reel

Rails

Tape and Reel

Rails

Tape and Reel

"

DAC7724NB

PLCC-28

–40°C to +85°C

"

DAC7724U

SO-28

–40°C to +85°C

"

DAC7724UB

SO-28

–40°C to +85°C

"

DAC7725N

PLCC-28

–40°C to +85°C

"

DAC7725NB

PLCC-28

–40°C to +85°C

"

DAC7725U

SO-28

–40°C to +85°C

"

SO-28

"

DAC7725UB

–40°C to +85°C

"

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /750 indicates 750 devices per reel). Ordering 750 pieces

of “DAC7724/750” will get a single 750-piece Tape and Reel.

ESD PROTECTION CIRCUITS

V_CC

RefH

V_OUT

RefL

V_SS

1 of 4

V_DD

GND

Typ of Each

Logic Input Pin

Typ of Each

I/O Pin

®

4

DAC7724, 7725

PIN CONFIGURATIONS

Top View

SO

PLCC

V_REFH

V_OUTB

1

2

3

4

5

6

7

8

9

28 V_REFL

27 V_OUTC

26 V_OUTD

25 V_CC

4

3

2

1

28 27 26

V_OUTA

25 V_CC

GND

RESET

LDAC

5

6

7

V_SS

24 V_DD

GND

24 V_DD

23 CS

RESET

LDAC

23 CS

DAC7724

DAC7725

22 A0

(LSB) DB0

DB1

8

9

22 A0

DAC7724

DAC7725

21 A1

(LSB) DB0

DB1

21 A1

20 R/W

19 DB11 (MSB)

DB2 10

DB3 11

20 R/W

19 DB11 (MSB)

18 DB10

17 DB9

16 DB8

15 DB7

DB2 10

DB3 11

DB4 12

DB5 13

DB6 14

12 13 14 15 16 17 18

PIN DESCRIPTIONS

NAME

DESCRIPTION

1

2

3

4

5

6

V_REFH

V_OUTB

V_OUTA

V_SS

Reference Input Voltage High. Sets maximum output voltage for all DACs.

DAC B Voltage Output.

DAC A Voltage Output.

Negative Analog Supply Voltage, 0V or –15V.

Ground.

GND

RESET

Asynchronous Reset Input. Sets DAC and input registers to either mid-scale (800_H, DAC7724) or zero-scale (000_H, DAC7725)

when LOW.

7

LDAC

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

R/W

A1

Load DAC Input. All DAC Registers are transparent when LOW.

8

Data Bit 0. Least significant bit of 12-bit word.

9

Data Bit 1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bit 8

Data Bit 9

Data Bit 10

Data Bit 11. Most significant bit of 12-bit word.

Read/Write Control Input (read = HIGH, write = LOW).

Register/DAC Select (C or D = HIGH, A or B = LOW).

Register/DAC Select (B or D = HIGH, A or C = LOW).

Chip Select Input.

A0

CS

V_DD

Positive Digital Supply, +5V.

V_CC

Positive Analog Supply Voltage, +15V nominal.

DAC D Voltage Output.

V_OUTD

V_OUTC

V_REFL

DAC C Voltage Output.

Reference Input Voltage Low. Sets minimum output voltage for all DACs.

®

5

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: V_SS= 0V

At T_A= +25°C, V_CC= +15V, V_DD= +5V, V_SS= 0V, V_REFH= +10V, V_REFL= 0V, representative unit, unless otherwise specified.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel 25°C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel 85°C

(Typical of Each Output Channel)

0.5

0.4

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

0.5

0.4

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

000_H200_H

400_H600_H

800_H

A00_HC00_H

E00_HFFF_H

000_H200_H

400_H600_H

800_H

A00_HC00_H

E00_HFFF_H

Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel –40°C

ZERO-SCALE ERROR vs TEMPERATURE

(Code 004_H)

(Typical of Each Output Channel)

2.0

1.5

0.5

0.4

0.3

0.2

0.1

DAC B

0

1.0

DAC D

DAC A

–0.1

–0.2

–0.3

–0.4

–0.5

0.5

0

0.5

0.4

–0.5

–1.0

–1.5

–2.0

0.3

DAC C

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

000_H200_H

400_H600_H

800_H

A00_HC00_H

E00_HFFF_H

Temperature (°C)

Digital Input Code

CURRENT vs CODE

All DACs Sent to Indicated Code

FULL-SCALE ERROR vs TEMPERATURE

(Code FFF_H)

V_REFH

2.0

1.5

1.2

1.0

0.8

0.6

0.4

0.2

0

1.0

DAC B

DAC D

DAC A

0.5

–0.2

–0.4

V_REFL

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–0.5

–1.0

–1.5

–2.0

DAC C

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

000_H200_H

400_H600_H

800_H

A00_HC00_H

E00_HFFF_H

Temperature (°C)

Digital Input Code

®

6

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: V_SS= 0V (Cont.)

At T_A= +25°C, V_CC= +15V, V_DD= +5V, V_SS= 0V, V_REFH= +10V, V_REFL= 0V, representative unit, unless otherwise specified.

POSITIVE SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER SUPPLY CURRENT vs TEMPERATURE

I_CC

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.00

2.50

2.00

1.50

1.00

0.50

0

I_CC

No Load

I_DD

–0.5

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Temperature (°C)

Digital Input Code

OUTPUT VOLTAGE vs SETTLING TIME

(0V to +10V)

OUTPUT VOLTAGE vs SETTLING TIME

(+10V to 0V)

Large Signal Settling Time: 5V/div

Small Signal

Settling Time: 1LSB/div

Small Signal Settling Time: 1LSB/div

+5V

LDAC

0

+5V

LDAC

0

Time (2µs/div)

OUTPUT VOLTAGE

MID-SCALE GLITCH PERFORMANCE

7FF_Hto 800_H

800_Hto 7FF_H

+5V

LDAC

0

+5V

LDAC

0

Time (1µs/div)

®

7

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: V_SS= 0V (Cont.)

At T_A= +25°C, V_CC= +15V, V_DD= +5V, V_SS= 0V, V_REFH= +10V, V_REFL= 0V, representative unit, unless otherwise specified.

LOGIC SUPPLY CURRENT

OUTPUT NOISE vs FREQUENCY

vs LOGIC INPUT LEVEL FOR DATA BITS

1000

100

10

5

4

3

2

1

0

Code 004_H

Code FFF_H

0

0.1

1

10

100

1000

10000

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Logic Input Level for Data Bits (V)

Frequency (kHz)

OUTPUT VOLTAGE vs R_LOAD

SINGLE SUPPLY CURRENT LIMIT vs INPUT CODE

Short to Ground

16

14

12

10

8

20

15

10

Source

5

0

6

–5

4

–10

–15

–20

Short to V_CC

2

Sink

0

0.01

0.1

1

10

100

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

R

_LOAD(kW)

Digital Input Code

POWER SUPPLY REJECTION RATIO vs FREQUENCY

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

+15V

+5V

–100

–110

–120

10¹

10²

10³

10⁴

10⁵

10⁶

Frequency (Hz)

®

8

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: V_SS= –15V

At T_A= +25°C, V_CC= +15V, V_DD= +5V, V_SS= –15V, V_REFH= +10V, V_REFL= –10V, representative unit, unless otherwise specified.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel 85°C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel 25°C

(Typical of Each Output Channel)

0.5

0.4

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

0.5

0.4

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

000_H200_H

400_H600_H

800_H

A00_HC00_H

E00_HFFF_H

000_H200_H

400_H600_H

800_H

A00_HC00_H

E00_HFFF_H

Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

Single Channel –40°C

CURRENT vs CODE

All DACs Sent to Indicated Code

V_REFH

(Typical of Each Output Channel)

0.5

0.4

2.5

2.0

1.5

1.0

0.5

0

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

V_REFL

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

000_H200_H

400_H600_H

800_H

A00_HC00_HE000_HFFF_H

000_H200_H

400_H600_H

800_H

A00_HC00_H

E00_HFFF_H

Digital Input Code

BIPOLAR ZERO-SCALE ERROR vs TEMPERATURE

(Code 800_H)

POSITIVE FULL-SCALE ERROR vs TEMPERATURE

(Code FFF_H)

2.0

1.5

2.0

1.5

1.0

DAC A

DAC B

DAC D

0.5

0

DAC A

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

DAC D

DAC C

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

Temperature (°C)

®

9

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: V_SS= –15V (Cont.)

At T_A= +25°C, V_CC= +15V, V_DD= +5V, V_SS= –15V, V_REFH= +10V, V_REFL= –10V, representative unit, unless otherwise specified.

NEGATIVE FULL-SCALE ERROR vs TEMPERATURE

(Code 000_H)

POWER SUPPLY CURRENT vs TEMPERATURE

I_CC

2.0

1.5

7

6

5

4

1.0

DAC B

3

2

1

Data = FFF_H(all DACs)

No Load

DAC D

DAC A

0.5

0

–1

–2

–3

–4

–5

–6

–7

I_DD

–0.5

–1.0

–1.5

–2.0

DAC C

I_SS

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

Temperature (°C)

OUTPUT VOLTAGE vs R_LOAD

SUPPLY CURRENT vs CODE

6

5

15

10

5

I_CC

4

Source

Data = FFF_H(all DACs)

No Load

3

2

1

0

I_DD

–1

–2

–3

–4

–5

–6

–5

–10

–15

Sink

I_SS

0.01

0.1

1

10

100

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

R_LOAD(kΩ)

Digital Input Code

OUTPUT VOLTAGE vs SETTLING TIME

(–10V to +10V)

OUTPUT VOLTAGE vs SETTLING TIME

(+10V to –10V)

Large Signal

Settling Time: 5V/div

Small Signal

Settling Time: 0.5LSB/div

Small Signal

Settling Time: 0.5LSB/div

Large Signal

Settling Time: 5V/div

+5V

LDAC

0

LDAC

0

Time (2µs/div)

®

10

DAC7724, 7725

TYPICAL PERFORMANCE CURVES: V_SS= –15V (Cont.)

At T_A= +25°C, V_CC= +15V, V_DD= +5V, V_SS= –15V, V_REFH= +10V, V_REFL= –10V, representative unit, unless otherwise specified.

DUAL SUPPLY CURRENT LIMIT vs INPUT CODE

POWER SUPPLY REJECTION RATIO vs FREQUENCY

SHORT TO GROUND

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

20

15

10

5

–15V

0

+15V

–5

–10

–15

–20

+5V

10¹

10²

10³

10⁴

10⁵

10⁶

000_H200_H400_H600_H800_HA00_HC00_HE00_HFFF_H

Frequency (Hz)

Digital Input Code

OUTPUT VOLTAGE

MID-SCALE GLITCH PERFORMANCE

BROADBAND NOISE

7FF_Hto 800_H

800_Hto 7FF_H

BW = 1MHz

Code = 800_H

+5V

LDAC

0

Time (1µs/div)

Time (1ms/div)

OUTPUT NOISE vs FREQUENCY

DATA BUS FEEDTHROUGH GLITCH

1000

100

10

Noise at any code

+5V

DATA BUS

0

0.1

1

10

100

1000

10000

Time (0.5µs/div)

Frequency (kHz)

®

11

DAC7724, 7725

output (“full-scale”) are set by the external voltage refer-

ences (V_REFLand V_REFH, respectively). The digital input is

a 12-bit parallel word and the DAC input registers offer a

readback capability. The converters can be powered from a

single +15V supply or a dual ±15V supply. Each device

offers a reset function which immediately sets all DAC

registers and DAC output voltages to mid-scale (DAC7724,

code 800_H) or to zero-scale (DAC7725, code 000_H). See

Figures 2 and 3 for the basic operation of the DAC7724/25.

THEORY OF OPERATION

The DAC7724 and DAC7725 are quad voltage output,

12-bit digital-to-analog converters (DACs). The architecture

is a classic R-2R ladder configuration followed by an opera-

tional amplifier that serves as a buffer, as shown in Figure 1.

Each DAC has its own R-2R ladder network and output op-

amp, but all share the reference voltage inputs. The mini-

mum voltage output (“zero-scale”) and maximum voltage

R_F

V_OUT

R

2R

V_REFH

V_REFL

FIGURE 1. DAC7724/25 Architecture.

DAC7724

DAC7725

+10.00V

0.1µF

+15V

+

1

2

3

4

5

6

7

8

9

V_REFH

V_OUTB

V_OUTA

V_SS

V_REFL28

V_OUTC27

V_OUTD26

V_CC25

V_DD24

CS 23

0V to +10V

0.1µF

1µF to 10µF

+5V

+

GND

RESET

LDAC

DB0

1µF to 10µF

Reset DACs⁽¹⁾

Chip Select

A0 22

Load DAC Registers

Address Bus

or Decoder

A1 21

DB1

R/W 20

DB11 19

DB10 18

DB9 17

DB8 16

DB7 15

Read/Write

10 DB2

11 DB3

12 DB4

13 DB5

14 DB6

Data Bus

NOTE: (1) Reset LOW sets all DACs to code 800_Hon the DAC7724 and to code 000_Hon the DAC7725.

FIGURE 2. Basic Single-Supply Operation of the DAC7724/25.

®

12

DAC7724, 7725

DAC7724

DAC7725

+10.000V

–10.000V

0.1µF

–10V to +10V

0.1µF

–10V to +10V

+15V

+

1

2

3

4

5

6

7

8

9

V_REFH

V_OUTB

V_OUTA

V_SS

V_REFL28

V_OUTC27

V_OUTD26

V_CC25

V_DD24

CS 23

0.1µF

1µF to 10µF

–15V

+5V

+

1µF to 10µF

0.1µF

+

GND

RESET

LDAC

DB0

1µF to 10µF

Reset DACs⁽¹⁾

Chip Select

Load DAC Registers

A0 22

Address Bus

or Decoder

A1 21

Read/Write

DB1

R/W 20

DB11 19

DB10 18

DB9 17

DB8 16

DB7 15

10 DB2

11 DB3

12 DB4

13 DB5

14 DB6

Data Bus

NOTE: (1) Reset LOW sets all DACs to code 800_Hon the DAC7724 and to code 000_Hon the DAC7725.

FIGURE 3. Basic Dual-Supply Operation of the DAC7724/25.

ANALOG OUTPUTS

tially, the offset of the output op-amp). The maximum

output is equal to V_REFHplus a similar offset voltage. Note

that V_SS(the negative power supply) must either be con-

nected to ground or must be in the range of –14.25V to

–15.75V. The voltage on V_SSsets several bias points within

the converter, if V_SSis not in one of these two configura-

tions, the bias values may be in error and proper operation

of the device is not guaranteed.

When V_SS= –15V (dual supply operation), the output

amplifier can swing to within 4V of the supply rails, guar-

anteed over the –40°C to +85°C temperature range. With

V_SS= 0V (single-supply operation) and R_LOADconnected to

ground, the output can swing to ground. Note that the

settling time of the output op-amp will be longer with

voltages very near ground. Additionally, care must be taken

when measuring the zero-scale error when V_SS= 0V. Since

the output voltage cannot swing below ground, the output

voltage may not change for the first few digital input codes

(000_H, 001_H, 002_H, etc.) if the output amplifier has a nega-

tive offset. At the negative offset limit of –4 LSB (-9.76mV),

for the single-supply case, the first specified output starts at

code 004_H.

The current into the V_REFH input and out of V_REFL depends

on the DAC output voltages and can vary from a few

microamps to approximately 0.3mA. The reference input

appears as a varying load to the reference. If the reference

can sink or source the required current, a reference buffer is

not required. See “Reference Current vs Code” in the Typi-

cal Performance Curves.

The analog supplies (or the analog supplies and the refer-

ence power supplies) have to come up first. If the power

supplies for the references come up first, then the V_CCand

V_SSsupplies will be “powered from the reference via the

ESD protection diodes” (see page 4).

REFERENCE INPUTS

For dual-supply operation, the reference inputs, V_REFLand

V_REFH, can be any voltage between V_SS+ 4V and V_CC– 4V

provided that V_REFHis at least 1.25V greater than V_REFL

.

For single-supply operation (V_SS= 0V), V_REFLvalue can be

above 0V, with the same provision that V_REFHis at least

1.25V greater than V_REFL. The minimum output of each

DAC is equal to V_REFLplus a small offset voltage (essen-

Bypassing the reference voltage or voltages with at least a

0.1uF capacitor placed as close to the DAC7724/25 package

is strongly recommended.

®

13

DAC7724, 7725

DIGITAL INTERFACE

The double buffered architecture is mainly designed so that

each DAC Input Register can be written at any time and then

all DAC output voltages updated simultaneously by pulling

LDAC LOW. It also allows a DAC Input Register to be

written to at any point and the DAC voltage to be synchro-

nously changed via a trigger signal connected to LDAC.

Table I shows the basic control logic for the DAC7724/25.

Note that each internal register is level triggered and not

edge triggered. When the appropriate signal is LOW, the

register becomes transparent. When this signal is returned

HIGH, the digital word currently in the register is latched.

The first set of registers (the Input Registers) are triggered

via the A0, A1, R/W, and CS inputs. Only one of these

registers is transparent at any given time. The second set of

registers (the DAC Registers) are all transparent when LDAC

input is pulled LOW.

DIGITAL TIMING

Figure 4 and Table II provide detailed timing for the digital

interface of the DAC7724 and DAC7725.

DIGITAL INPUT CODING

Each DAC can be updated independently by writing to the

appropriate Input Register and then updating the DAC

Register. Alternatively, the entire DAC Register set can be

configured as always transparent by keeping LDAC LOW—

the DAC update will occur when the Input Register is

written.

The DAC7724 and DAC7725 input data is in straight binary

format. The output voltage is given by the following equa-

tion:

V

– V_REFL• N

(

)

REFH

V_OUT= V_REFL

+

4096

where N is the digital input code. This equation does not

include the effects of offset (zero-scale) errors.

STATE OF

SELECTED

INPUT

SELECTED

INPUT

STATE OF

ALL DAC

A1

A0

R/W

CS

RESET

LDAC

REGISTER

REGISTERS

L⁽¹⁾

L

H

L

H

L

H

L

H

L

H

L

H

L

H

X

L

H

X

L

H

X

H⁽²⁾

H

L

A

B

C

D

A

B

C

D

A

Transparent

Readback

(All Latched)

Reset⁽⁴⁾

Transparent

Latched

Transparent

Latched

Reset⁽⁴⁾

L

H

L

H

L

B

C

D

H

X⁽³⁾

X

NONE

ALL

H

X

NOTES: (1) L = Logic LOW. (2) H= Logic HIGH. (3) X = Don’t Care. (4) DAC7724 resets to 800_H, DAC7725 resets to 000_H. When RESET rises, all registers

that are in their latched state retain the reset value.

TABLE I. DAC7724 and DAC7725 Control Logic Truth Table.

®

14

DAC7724, 7725

t_LD

t_WCS

CS

t_WS

t_WH

R/W

t_RCS

t_AH

t_AS

CS

A0/A1

t_RDH

t_RDS

t_LWD

R/W

t_AS

t_AH

LDAC

±0.012% of FSR

Error Band

t_DH

t_DS

A0/A1

Data In

t_DZ

t_S

Data Out

Data Valid

t_CSD

V_OUT

Data Read Timing

Data Write Timing

±0.012% of FSR

Error Band

t_RESET

RESET

t_S

+FS

V_OUT, DAC7725

–FS

±0.012% of FSR

Error Band

+FS

V_OUT, DAC7724

–FS

Mid-Scale

±0.012% of FSR

DAC7724/25 Reset Timing

Error Band

FIGURE 4. Digital Input and Output Timing.

SYMBOL

DESCRIPTION

CS LOW for Read

R/W HIGH to CS LOW

R/W HIGH after CS HIGH

CS HIGH to Data Bus in High Impedance

CS LOW to Data Bus Valid

CS LOW for Write

MIN

TYP

MAX

UNITS

t_RCS

t_RDS

t_RDH

t_DZ

t_CSD

t_WCS

t_WS

t_WH

t_AS

t_AH

t_LD

t_DS

t_DH

t_LWD

t_RESET

t_S

200

10

ns

µs

100

160

50

0

10

0

50

R/W LOW to CS LOW

R/W LOW after CS HIGH

Address Valid to CS LOW

Address Valid after CS HIGH

LDAC Delay from CS HIGH

Data Valid to CS LOW

Data Valid after CS HIGH

LDAC LOW

RESET LOW Time

Settling Time

10

TABLE II. Timing Specifications (T_A= –40°C to +85°C).

®

15

DAC7724, 7725

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