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产品型号DAC8043U的概述

DAC8043U概述 DAC8043U是一款高性能、多通道数模转换器（DAC），其设计目的是满足现代工业设备和消费电子产品对信号精度和动态范围的持续追求。作为一家技术创新型企业的产品，DAC8043U为用户提供了低功耗、高线性度和高精度的数模转换解决方案。DAC8043U的应用广泛，包括自动化控制、数据采集系统、音频设备以及其他需要将数字信号转换为模拟信号的场合。该DAC具有四个独立的通道，支持高达12位的分辨率。这种灵活性使其能够在多种应用中同时处理多个信号，极大地提高了成本效益。此外，DAC8043U的快速转换时间和低失真特性，使得其在精密仪器和音频处理中的表现相当出色。 DAC8043U详细参数 DAC8043U的主要技术参数如下： - 分辨率：12位 - 通道数：4 - 工作电压：5V ±10% - 输入接口：串行接口（SPI/I2C） - 转换时间：约为5μs（在标准条件下...

产品型号DAC8043U的Datasheet PDF文件预览

DAC8043

CMOS 12-Bit Serial Input Multiplying

DIGITAL-TO-ANALOG CONVERTER

FEATURES

APPLICATIONS

● 12-BIT ACCURACY IN 8-PIN SOIC

● FAST 3-WIRE SERIAL INTERFACE

● LOW INL AND DNL: ±1/2 LSB max

● GAIN ACCURACY TO ±1LSB max

● LOW GAIN TEMPCO: 5ppm/°C max

● OPERATES WITH +5V SUPPLY

● TTL/CMOS COMPATIBLE

● AUTOMATIC CALIBRATION

● MOTION CONTROL

● MICROPROCESSOR CONTROL SYSTEMS

● PROGRAMMABLE AMPLIFIER/

ATTENUATORS

● DIGITALLY CONTROLLED FILTERS

● ESD PROTECTED

DESCRIPTION

The DAC8043 is a 12-bit current output multiplying

digital-to-analog converter (DAC) that is packaged in a

space-saving, surface-mount 8-pin SOIC. Its 3-wire se-

rial interface saves additional circuit board space which

results in low power dissipation. When used with micro-

processors having a serial port, the DAC8043 minimizes

the digital noise feedthrough from its input to output.

The serial port can be used as a dedicated analog bus and

kept inactive while the DAC8043 is in use. Serial inter-

facing reduces the complexity of opto or transformer

isolation applications.

R_FB

12-Bit

D/A

Converter

V_REF

I_OUT

12-Bit

DAC Register

The DAC8043 contains a 12-bit serial-in, parallel-out

shift register, a 12-bit DAC register, a 12-bit CMOS

DAC, and control logic. Serial input (SRI) data is clocked

into the input register on the rising edge of the clock

(CLK) pulse. When the new data word had been clocked

in, it is loaded into the DAC register by taking the LD

input low. Data in the DAC register is converted to an

output current by the D/A converter.

V_DD

GND

CLK

SRI

12-Bit Input

Shift Register

The DAC8043 operates from a single +5V power supply

which makes the DAC8043 an ideal low power, small

size, high performance solution for several applications.

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

FAXLine: (800) 548-6133 (US/Canada Only)

• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1197B

Printed in U.S.A. March, 1998

DAC8043

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

At V_DD= +5V; V_REF= +10V; I_OUT= GND = 0V; T_A= Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.

DAC8043U

TYP

DAC8043UC

TYP

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

STATIC PERFORMANCE

Resolution

Bits

LSB

ppm/°C

%/%

Nonlinearity⁽¹⁾

INL

DNL

FSE

±1

±2

±5

±1/2

±1

±2

±5

Differential Nonlinearity⁽²⁾

Gain Error⁽³⁾

T_A= +25°C

T_A= Full Temp Range

Gain Tempco⁽⁵⁾

Power Supply Rejection Ratio

Output Leakage Current⁽⁴⁾

TC_FSE

PSRR

I_LKG

∆V_DD= ±5%

T_A= +25°C

±0.0006

±0.002

±5

±0.0006

±0.002

±5

T_A= Full Temp Range

T_A= +25°C

T_A= Full Temp Range

±100

0.03

0.60

±25

0.03

0.15

Zero Scale Error^{(7, 12)}

Input Resistance⁽⁸⁾

I_ZSE

R_IN

LSB

kΩ

AC PERFORMANCE

Output Current Settling Time^{(5, 6)}

Digital-to-Analog Glitch

Energy^{(5, 10)}

t_S

T_A= +25°C

0.25

µs

nVs

_REF= 0V

I_OUT= Load = 100Ω

C_EXT= 13pF

DAC Register Loaded Alternately with all 0s and all 1s

Feedthrough Error^{(5, 11)}

V_REF= 20Vp-p at f = 10kHz

0.7

mVp-p

(V_REFto I_OUT

)

Digital Input = 0000 0000 0000

_A= +25°C

Total Harmonic Distortion⁽⁵⁾

THD

e_N

V_REF= 6V_RMSat 1kHz

DAC Register Loaded with all 1s

10Hz to 100kHz

–85

Output Noise Voltage Density^{(5, 13)}

nV/√Hz

Between R_FBand I_OUT

DIGITAL INPUTS

Digital Input High

Digital Input Low

Input Leakage Current⁽⁹⁾

Input Capacitance^{(5, 11)}

V_IH

V_IL

I_IL

2.4

µA

0.8

±1

0.8

±1

V_IN= 0V to +5V

V_IN= 0V

C_IN

ANALOG OUTPUTS

Output Capacitance⁽⁵⁾

C_OUT

Digital Inputs = V_IH

Digital Inputs = V_IL

110

TIMING CHARACTERISTICS^{(5, 14)}

Data Setup Time

Data Hold Time

Clock Pulse Width High

Clock Pulse Width Low

Load Pulse Width

t_DS

t_DH

t_CH

t_CL

t_LD

T_A= Full Temperature Range

120

LSB Clock into Input Register

to Load DAC Register Time

t_ASB

T_A= Full Temperature Range

POWER SUPPLY

Supply Voltage

Supply Current

V_DD

I_DD

4.75

5.25

500

100

4.75

5.25

500

100

µA

Digital Inputs = V_IHor V_IL

Digital Inputs = 0V or V_DD

NOTES: (1) ±1/2 LSB = ±0.012% of Full Scale. (2) All grades are monotonic to 12-bits over temperature. (3) Using internal feedback resistor. (4) Applies to I_OUT; All

digital inputs = 0V. (5) Guaranteed by design and not tested. (6) I_OUTLoad = 100Ω, C_EXT= 13pF, digital input = 0V to V_DDor V_DDto 0V. Extrapolated to 1/2 LSB:

_S= propagation delay (t_PD) + 9τ where τ = measured time constant of the final RC decay. (7) V_REF= +10V, all digital inputs = 0V. (8) Absolute temperature coefficient

is less than ±50ppm/°C. (9) Digital inputs are CMOS gates: I_INis typically 1nA at +25°C. (10) V_REF= 0V, all digital inputs = 0V to V_DDor V_DDto 0V. (11) All digital

inputs = 0V. (12) Calculated from worst case R_REF: I_ZSE(in LSBs) = (R_REFX I_LKGX 4096)/V_REF. (13) Calculations from en = √4K TRB where: K = Boltzmann constant,

J/°K, R = resistance, Ω. T = Resistor temperature, °K, B = bandwidth, Hz. (14) Tested at V_IN= 0V or V_DD

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

DAC8043

WAFER TEST LIMITS

At V_DD= +5V; V_REF= +10V; I_OUT= GND = 0V; T_A= +25°C.

DAC8043

UNITS

PARAMETER

SYMBOL

CONDITIONS

LIMIT

STATIC ACCURACY

Resolution

Integral Nonlinearity

Differential Nonlinearity

Gain Error

INL

DNL

G_FSE

PSRR

I_LKG

±1

±2

±0.002

±5

Bits min

LSB max

%/% max

nA max

Using Internal Feedback Resistor

∆V_DD= ±5%

Power Supply Rejection Ratio

Output Leakage Current (I_OUT

)

Digital Inputs = V_IL

REFERENCE INPUT

Input Resistance

R_IN

7/15

kΩ min/max

DIGITAL INPUTS

Digital Input HIGH

Digital Input LOW

Input Leakage Current

V_IH

V_IL

I_IL

2.4

0.8

±1

V min

V max

µA max

V_IN= 0V to V_DD

POWER SUPPLY

Supply Current

I_DD

Digital Inputs = V_IHor V_IL

Digital Inputs = 0V to V_DD

500

100

µA max

NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not

guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

V_DDto GND .................................................................................. 0V, +7V

V_REFto GND ...................................................................................... ±25V

V_RFBto GND ...................................................................................... ±25V

Digital Input Voltage Range ................................................. –0.3V to V_DD

Output Voltage (Pin 3)......................................................... –0.3 V to V_DD

Operating Temperature Range

AD ........................................................................................0°C to +70°C

U, UC ............................................................................... –40°C to +85°C

Junction Temperature .................................................................... +150°C

Storage Temperature.................................................... –65°C to + 150°C

Lead Temperature (soldering, 10s) .............................................. +300° C

Top View

8-Pin SOIC

V_REF

V_DD

R_FB

I_OUT

CLK

SRI

GND

θ_JA

^{..........................................................................................................................}+100°C/W

θ_JC........................................................................................... +42°C/W

CAUTION: 1. Do not apply voltages higher than V_DDor less than GND

potential on any terminal except V_REF(Pin 1) and R_FB(Pin 2). 2. The digital

control inputs are ESD protected: however, permanent damage may occur on

unprotected units from high-energy electrostatic fields. Keep units in conduc-

tive foam at all times until ready to use. 3. Use proper anti-static handling

procedures. 4. Absolute Maximum Ratings apply to both packaged devices.

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device.

ELECTROSTATIC

DISCHARGE SENSITIVITY

Any integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

PACKAGE/ORDERING INFORMATION

PACKAGE

DRAWING

NUMBER⁽¹⁾

TEMPERATURE

RANGE

PRODUCT

INL

PACKAGE

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

published specifications.

DAC8043U

DAC8043UC 1/2LSB

1LSB

–40°C to +85°C

8-pin SOIC

182

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

Digital Inputs: All digital inputs of the DAC8043 incorpo-

rate on-chip ESD protection circuitry. This protection is

designed and has been tested to withstand five 2500V

positive and negative discharges (100pF in series with 1500Ω)

applied to each digital input.

Analog Pins: Each analog pin has been tested to Burr-

Brown’s analog ESD test consisting of five 1000V positive

and negative discharges (100pF in series with 1500Ω) ap-

plied to each pin. V_REFand R_FBshow some sensitivity.

DAC8043

WRITE CYCLE TIMING DIAGRAM

Bit 1

Bit 12

LSB

SRI

Bit 2

Bit 11

MSB⁽¹⁾

t_DH

t_DS

t_CL

t_CH

CLK INPUT

t_ASB

Load Serial Data

Into Input Register

t_LD

Load Input Register's

Data Into DAC Register

NOTE: (1) Data loaded MSB first.

DAC8043

TYPICAL PERFORMANCE CURVES

At V_DD= +5V; V_REF= +10V; I_OUT= GND = 0V; T_A= Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.

LINEARITY ERROR vs REFERENCE VOLTAGE

GAIN vs FREQUENCY

–20

0.5

0.25

Digital Input

= 1111 1111 1111

–40

–60

Digital Input

= 0000 0000 0000

–80

–0.25

–0.5

V_DD= +5V

V_REF= 100mV

T_A= +25°C

–100

–120

10k

100k

Frequency (Hz)

10M

V_REF(V)

TOTAL HARMONIC DISTORTION vs FREQUENCY

(Multiplying Mode)

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

V_DD= +5V

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

–20

V_DD= +5V

V_IN= 6Vrms

T_A= +25°C

–40

–60

–80

–100

–120

100

1000

Frequency (Hz)

10000

V_IN(V)

LINEARITY ERROR vs DIGITAL CODE

DNL ERROR vs REFERENCE VOLTAGE

0.75

0.5

0.25

T_A= +25°C

_REF= +10V

0.25

–0.25

–0.5

–0.75

–1

–0.25

–0.5

1024

2048

3072

4096

Digital Input Code (Decimal)

V_REF(V)

DAC8043

tains a constant current in each leg of the ladder regardless of

the input code. The input resistance at V_REFis therefore

constant and can be driven by either a voltage or current, AC

or DC, positive or negative polarity, and have a voltage range

up to ±20V.

DISCUSSION OF

SPECIFICATIONS

RELATIVE ACCURACY

This term, also known as end point linearity or integral

linearity, describes the transfer function of analog output to

digital input code. Relative accuracy describes the deviation

from a straight line, after zero and full scale errors have been

adjusted to zero.

A CMOS switch transistor, included in series with the ladder

terminating resistor and in series with the feedback resistor,

R_FB, compensates for the temperature drift of the ON resis-

tance of the ladder switches.

Figure 2 shows an equivalent circuit for the DAC. C_OUTis the

output capacitance due to the N-channel switches and varies

from about 80pF to 110pF with digital input code. The current

source I_LKGis the combination of surface and junction leak-

ages to the substrate. I_LKGapproximately doubles every 10°C.

R_Ois the equivalent output resistance of the D/A and it varies

with input code.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1LSB

change in the output when the input code changes by 1LSB.

A differential nonlinearity specification of 1LSB maximum

guarantees monotonicity.

GAIN ERROR

Gain error is the difference between the full-scale DAC

output and the ideal value. The ideal full scale output value

for the DAC8043 is –(4095/4096)V_REF. Gain error may be

adjusted to zero using external trims as shown in Figure 4.

R_FB

V_REF

I_OUT

I_LKG

D_INV_REF

C_OUT

R_O

4096

OUTPUT LEAKAGE CURRENT

GND

The current which appears at I_OUTwith the DAC loaded with

all zeros.

FIGURE 2. Equivalent Circuit for the DAC.

OUTPUT CAPACITANCE

The parasitic capacitance measured from I_OUTto GND.

INSTALLATION

ESD PROTECTION

FEEDTHROUGH ERROR

The AC output error due to capacitive coupling from V_REFto

I_OUTwith the DAC loaded with all zeros.

All digital inputs of the DAC8043 incorporate on-chip ESD

protection circuitry. This protection is designed to withstand

2.5kV (using the Human Body Model, 100pF and 1500Ω).

However, industry standard ESD protection methods should

be used when handling or storing these components. When

not in use, devices should be stored in conductive foam or

rails. The foam or rails should be discharged to the destina-

tion socket potential before devices are removed.

OUTPUT CURRENT SETTLING TIME

The time required for the output current to settle to within

+0.01% of final value for a full scale step.

DIGITAL-TO-ANALOG GLITCH ENERGY

The integrated area of the glitch pulse measured in nanovolt-

seconds. The key contributor to digital-to-analog glitch is

charge injected by digital logic switching transients.

POWER SUPPLY CONNECTIONS

The DAC8043 is designed to operate on V_DD= +5V ±5%.

For optimum performance and noise rejection, power supply

decoupling capacitors C_Dshould be added as shown in the

application circuits. These capacitors (1µF tantalum recom-

mended) should be located close to the D/A. Output op amp

analog common (+ input) should be connected as near to the

GND pins of the DAC8043 as possible.

CIRCUIT DESCRIPTION

Figure 1 shows a simplified schematic of a DAC8043. The

current from the V_REFpin is switched between I_OUTand GND

by 12 single-pole double-throw CMOS switches. This main-

V_REF

WIRING PRECAUTIONS

To minimize AC feedthrough when designing a PC board,

care should be taken to minimize capacitive coupling be-

tween the V_REFlines and the I_OUTlines. Coupling from any

of the digital control or data lines might degrade the glitch

performance. Solder the DAC8043 directly into the PC board

without a socket. Sockets add parasitic capacitance (which

can degrade AC performance).

R_FB

I_OUT

GND

Bit 1

(MSB)

Bit 2

Bit 3

Bit 12

(LSB)

FIGURE 1. Simplified Circuit Diagram for the DAC.

DAC8043

AMPLIFIER OFFSET VOLTAGE

versus digital input code are listed in Table I. The operational

amplifiers used in this circuit can be single amplifiers such as

the OPA602, or a dual amplifier such as the OPA2107. C1

provides phase compensation to minimize settling time and

overshoot when using a high speed operational amplifier.

The output amplifier used with the DAC8043 should have

low input offset voltage to preserve the transfer function

linearity. The voltage output of the amplifier has an error

component which is the offset voltage of the op amp multi-

plied by the “noise gain” of the circuit. This “noise gain” is

equal to (R_F/R_O+ 1) where R_Ois the output impedance of the

D/A I_OUTterminal and R_Fis the feedback network imped-

ance. The nonlinearity occurs due to the output impedance

varying with code. If the 0 code case is excluded (where

R_O= infinity), the R_Owill vary from R to 3R providing a

“noise gain” variation between 4/3 and 2. In addition, the

variation of R_Ois nonlinear with code, and the largest steps

in R_Ooccur at major code transitions where the worst

differential nonlinearity is also likely to be experienced. The

nonlinearity seen at the amplifier output is

If an application requires the D/A to have zero gain error, the

circuit shown in Figure 4 may be used. Resistor R2 induces

a positive gain error greater than worst-case initial negative

gain error. Trim resistor R1 provides a variable negative gain

error and have sufficient trim range to correct for the worst-

case initial positive gain error plus the error produced by R2.

BIPOLAR CONFIGURATION

Figure 5 shows the DAC8043 in a typical bipolar (four-

quadrant) multiplying configuration. The analog output val-

ues versus digital input code are listed in Table II.

2V_OS– 4V_OS/3 = 2V_OS/3.

The operational amplifiers used in this circuit can be single

amplifiers such as the OPA602 or a dual amplifier such as

the OPA2107. C1 provides phase compensation to minimize

settling time and overshoot when using a high speed opera-

tional amplifier. The bipolar offset resistors R1–R2 should

be ratio-matched to 0.01% to ensure the specified gain error

performance.

Thus, to maintain good nonlinearity the op amp offset should

be much less than 1/2LSB.

UNIPOLAR CONFIGURATION

Figure 3 shows DAC8043 in a typical unipolar (two-quad-

rant) multiplying configuration. The analog output values

DATA INPUT

↓ LSB

1111 1111 1111

1000 0000 0001

1000 0000 0000

0111 1111 1111

0000 0000 0000

ANALOG OUTPUT

DATA INPUT

↓ LSB

1111 1111 1111

1000 0000 0000

0000 0000 0001

0000 0000 0000

ANALOG OUTPUT

MSB ↓

+V_REF(2047/2048)

+V_REF(1/2048)

0 Volts

–V_REF(1/2048)

–V_REF(2048/2048)

–V_REF(4095/4096)

–V_REF(2048/4096) = –1/2V_REF

–V_REF(1/4096)

0 Volts

TABLE I. Unipolar Output Code.

TABLE II. Bipolar Output Code.

V_DD

+5V

V_IN

V_DDV_REF

+5V

R₁

100Ω

V_REF

C_D

1µF

C_D

1µF

R_FB

R₂

R_FB

C₁

C₁10pF

–

I_OUT

10pF

47Ω

–

I_OUT

DAC

GND

V_OUT

DAC

GND

V_OUT

DAC8043

A1 OPA602 or 1/2 OPA2107.

FIGURE 3. Unipolar Configuration.

FIGURE 4. Unipolar Configuration with Gain Trim.

+5V

R₁

V_DD

20kΩ

V_REF

R₂

20kΩ

–

C_D

1µF

V_OUT

R₃

10kΩ

R_FB

I_OUT

C₁

10pF

–

DAC

GND

A1–A2, OPA602 or 1/2 OPA2107.

DAC8043

FIGURE 5. Bipolar Configuration.

DAC8043

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产品型号DAC8043U的概述

产品型号DAC8043U的Datasheet PDF文件预览

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