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产品型号DAC811BH的概述

DAC811BH概述 DAC811BH是一款高性能、单通道数模转换器（DAC），广泛用于各种需要精确模拟信号生成的应用。这款DAC采用了创新的电流输出架构，具备16位的分辨率和高达5V的输出范围，因此在精密仪器、工业控制、音频处理以及通信系统等领域得到了广泛应用。DAC811BH的精准度和线性度特别适合于对信号调节要求极高的场合。 DAC811BH内部集成了多种功能模块，如电压参考源、环路补偿和故障检测等，这使其成为了用户设计过程中的理想选择。此外，DAC811BH的功耗低，响应速度快，能够适应各种复杂的应用环境。详细参数 DAC811BH的主要参数包括： 1. 分辨率：16位 2. 输入接口：SPI（串行外设接口）或并行数据接口 3. 输出电压范围：0V至5V 4. 线性度：±1LSB的DNL（差分非线性）和±1LSB的INL（积分非线性） 5. 电源电压：+5V 6. 功耗：典型...

产品型号DAC811BH的Datasheet PDF文件预览

DAC811

For most current data sheet and other product

information, visit www.burr-brown.com

Microprocessor-Compatible

12-BIT DIGITAL-TO-ANALOG CONVERTER

Input gating logic is designed so that loading the last

FEATURES

● SINGLE INTEGRATED CIRCUIT CHIP

nibble or byte of data can be accomplished simulta-

neously with the transfer of data (previously stored in

adjacent latches) from adjacent input latches to the

D/A latch. This feature avoids spurious analog output

values while using an interface technique that saves

computer instructions.

● MICROCOMPUTER INTERFACE:

DOUBLE-BUFFERED LATCH

● VOLTAGE OUTPUT: ±10V, ±5V, +10V

● MONOTONICITY GUARANTEED OVER

The DAC811 is laser trimmed at the wafer level and

is specified to ±1/4LSB maximum linearity error (B,

K, and S grades) at 25°C and ±1/2LSB maximum over

the temperature range. All grades are guaranteed mono-

tonic over the specification temperature range.

TEMPERATURE

● ±1/2LSB MAXIMUM NONLINEARITY OVER

TEMPERATURE

● GUARANTEED SPECIFICATIONS AT ±12V

AND ±15V SUPPLIES

The DAC811 is available in six performance grades

and three package types. DAC811J and K are speci-

fied over the temperature ranges of 0°C to +70°C;

DAC811A and B are specified over –25°C to +85°C;

DAC811R and S are specified over –55°C to +125°C.

DAC811J and K are packaged in a reliable 28-pin

plastic DIP or plastic SOIC package, while DAC811A,

B, R and S are available in a 28-pin 0.6" wide dual-

inline hermetically sealed ceramic side-brazed pack-

age (H package).

● TTL/5V CMOS-COMPATIBLE LOGIC

INPUTS

DESCRIPTION

The DAC811 is a complete, single-chip integrated-

circuit, microprocessor-compatible, 12-bit digital-to-

analog converter. The chip combines a precision volt-

age reference, microcomputer interface logic, and

double-buffered latch, in a 12-bit D/A converter with

a voltage output amplifier. Fast current switches and a

laser-trimmed thin-film resistor network provide a

highly accurate and fast D/A converter.

4 MSBs

4 LSBs

S_J

Input Latch

D/A Latch

Input Latch

Microcomputer interfacing is facilitated by a double-

buffered latch. The input latch is divided into three

4-bit nibbles to permit interfacing to 4-, 8-, 12-, or

16-bit buses and to handle right-or left-justified data.

The 12-bit data in the input latches is transferred to the

D/A latch to hold the output value.

R_F

10V

R_F

12-Bit D/A Converter

R_BPO

V_OUT

Voltage Reference

BPO

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

•

Tel: (520) 746-1111

Twx: 910-952-1111 Internet: http://www.burr-brown.com/

•

Cable: BBRCORP Telex: 066-6491

•

FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

^PDS1^-503K

^PD^rinA^tedCⁱⁿ8^U.1^S.A1^{. January, 2000}

SPECIFICATIONS

At T_A= +25°C. ±V_CC= 12V or 15V, unless otherwise noted.

DAC811AH, JP, JU

DAC811BH, KP, KU

DAC811RH

DAC811SH

PARAMETER

MIN

TYP

MAX

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

DIGITAL INPUT

Resolution

✻

Bits

Codes⁽¹⁾

USB, BOB

✻

Digital Inputs Over Temperature Range⁽²⁾

V_IH

V_IL

+15

+0.8

+10

±20

✻

VDC

µA

I_IH, V_I= +2.7V

I_IL, V_I= +0.4V

µA

Digital Interface Timing Over Temperature Range

t_WP, WR Pulse Width

✻

t_AW1, N_Xand LDAC Valid to End of WR

t_DW, Data Valid to End of WR

t_DH, Data Valid Hold Time

+10

ACCURACY

Linearity Error

Differential Linearity Error

Gain Error⁽³⁾

Offset Error^{(3, 4)}

Monotonicity

Power Supply Sensitivity: +V_CC

–V_CC

V_DD

±1/4

±1/2

±0.1

±1/2

±3/4

±0.2

±1/8 ±1/4

±1/4 ±1/2

±1/2 ±3/4

±1/8 ±1/4

±1/4 ±1/2

LSB

✻

±0.05

±0.15

% of FSR⁽⁵⁾

Guaranteed

±0.001

±0.002

±0.003

±0.006

✻

% of FSR/%V_CC

% of FSR/%V_DD

±0.0005 ±0.0015

DRIFT (Over Specification Temperature Range)

Gain

Unipolar Offset

Bipolar Zero

Linearity Error Over Temperature Range

Monotonicity Over Temperature Range

±10

±5

±30

±10

±3/4

±10 ±20

±15 ±30

ppm/°C

ppm of FSR/°C

LSB

±5

±7

±5

±10

±5

±7

±1/2

±1/4 ±1/2

✻

±1/2 ±3/4

✻

±1/4 ±1/2

✻

Guaranteed

SETTLING TIME⁽⁶⁾(to within ±0.01% of FSR of Final Value; 2kΩ load)

For Full Scale Range Change, 20V Range

10V Range

For 1LSB Change at Major Carry⁽⁷⁾

Slew Rate⁽⁶⁾

✻

µs

✻

V/µs

ANALOG OUTPUT

Voltage Range (±V_CC= 15V)⁽⁸⁾: Unipolar

Bipolar

Output Current

Output Impedance (at DC)

Short Circuit to Common Duration

0 to +10

±5, ±10

✻

Ω

±5

0.2

Indefinite

✻

REFERENCE VOLTAGE

Voltage

Source Current Available for External Loads

Temperature Coefficient

+6.2

+6.3

+6.4

✻

ppm/°C

±10

±30

±10 ±20

±10 ±30

±10 ±20

Short Circuit to Common Duration

Indefinite

✻

POWER SUPPLY REQUIREMENTS

Voltage: +V_CC

–V_CC

V_DD

Current (no load): +V_CC

–V_CC

V_DD

+11.4

–11.4

+4.5

+15

–15

+16

–23

+16.5

–16.5

+5.5

+25

–35

+15

✻

VDC

Potential at DCOM with Respect to ACOM⁽⁹⁾

Power Dissipation

±0.5

625

800

✻

TEMPERATURE RANGE

Specification: J, K

A, B

R, S

–25

–65

+70

+85

+150

✻

–55

✻

+125

✻

°C

Storage: J, K

A, B, R, S

–60

–65

+100

+150

✻

✻ Specification same as DAC811AH.

NOTES: (1) USB = unipolar straight binary; BOB = bipolar offset binary. (2) TTL, LSTTL and 54/74 HC compatible. (3) Adjustable to zero with external trim

potentiometer. (4) Error at input code 000₁₆for both unipolar and bipolar ranges. (5) FSR means full scale range and is 20V for the ±10V range. (6) Maximum

represents the 3σ limit. Not 100% tested for this parameter. (7) At the major carry, 7FF₁₆to 800₁₆and 800₁₆to 7FF₁₆. (8) Minimum supply voltage required for ±10V

output swing is ±13.5V. Output swing for ±11.4V supplies is at least –8V to +8V. (9) The maximum voltage at which ACOM and DCOM may be separated without

affecting accuracy specifications.

DAC811

PIN DESCRIPTIONS

ABSOLUTE MAXIMUM RATINGS

PIN NAME

FUNCTION

+V_CC................................................................................................................................ 0 to +18V

–V_CCto ACOM .......................................................................... 0 to –18V

V_DDto DCOM .............................................................................. 0 to +7V

V_DDto ACOM ...................................................................................... ±7V

ACOM to DCOM.................................................................................. ±7V

Digital Inputs (Pins 2–14, 16–19) to DCOM ...................... –0.4V to +18V

External Voltage Applied to 10V Range Resistor ............................ ±12V

Ref Out ............................................................. Indefinite Short to ACOM

External Voltage Applied to DAC Output................................ –5V to +5V

Power Dissipation ........................................................................ 1000mW

Lead Temperature (soldering, 10s)............................................... +300°C

Max Junction Temperature............................................................ +165°C

Thermal Resistance, θ_J-A: Plastic DIP and SOIC ....................... 100°C/W

Ceramic DIP .................................................................................. 65°C/W

+V_DD

Logic supply, +5V.

Write, command signal to load latches. Logic low

loads latches.

LDAC

N_A

Load D/A converter, enables WR to load the D/A

latch. Logic low enables.

Nibble A, enables WR to load input latch A (the

most significant nibble). Logic low enables.

N_B

Nibble B, enables WR to load input latch B. Logic

low enables.

N_C

Nibble C, enables WR to load input latch C (the

least significant nibble). Logic low enables.

D₁₁

Data bit 12, MSB, positive true.

Data bit 11.

NOTE: Stresses above those listed above may cause permanent damage to

the device. Exposure to absolute maximum conditions for extended periods

may affect device reliability.

D₁₀

D₉

Data bit 10.

D₈

Data bit 9.

D₇

Data bit 8.

D₆

Data bit 7.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

D₅

Data bit 6.

D₄

Data bit 5.

DCOM

D₀

Digital common, V_DDsupply return.

Data bit 1, LSB.

D₁

Data bit 2.

D₂

Data bit 3.

D₃

Data bit 4.

+V_CC

–V_CC

Gain Adj

ACOM

V_OUT

Analog supply input, +15V or +12V.

Analog supply input, –15V or –12V.

To externally adjust gain.

Analog common, ±V_CCsupply return.

D/A converter voltage output.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

10V Range Connect to pin 24 for 10V range.

Summing junction of output amplifier.

BPO

Bipolar offset. Connect to pin 26 for bipolar

operation.

Ref Out

6.3V reference output.

PACKAGE/ORDERING INFORMATION

MINIMUM

RELATIVE

ACCURACY

(LSB)

DIFFERENTIAL

LINEARITY

(LSB)

PACKAGE

DRAWING

NUMBER

SPECIFICATION

TEMPERATURE

RANGE

ORDERING

NUMBER⁽¹⁾

TRANSPORT

MEDIA

PRODUCT

PACKAGE

DAC811AH

DAC811JP

DAC811JU

±1/2 LSB

3/4

CerDIP-28

DIP-28

149

215

217

–25°C to +85°C

0°C to +70°C

DAC811AH

DAC811JP

DAC811JU

Rails

SOIC-28

1/2

215

217

DAC811JU/1K

DAC811KP

DAC811KU

Tape and Reel

Rails

DAC811KP

±1/4 LSB

DIP-28

0°C to +70°C

DAC811KU

±1/4 LSB

SOIC-28

0°C to +70°C

Rails

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces

of “DAC811JU/1K” will get a single 1000-piece Tape and Reel.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

DAC811

TIMING DIAGRAMS

Write Cycle #2

Write Cycle #1

Load second rank from first rank: N_A, N_B, N_C= 1

Load first rank from Data Bus: LDAC = 1

t_AW

LDAC

N_A, N_B, N_C

t_WP

t_DW

DB₁₁–DB₀

t_SET

t_DH

t_WP

±1/2LSB

DRIFT

DISCUSSION OF

SPECIFICATIONS

Gain drift is a measure of the change in the full scale range

(FSR) output over the specification temperature range. Drift is

expressed in parts per million per degree centigrade

(ppm/°C). Gain drift is established by testing the full scale

range value (e.g., +FS minus –FS) at high temperature, +25°C,

and low temperature, calculating the error with respect to the

+25°C value, and dividing by the temperature change.

INPUT CODES

The DAC811 accepts positive-true binary input codes.

DAC811 may be connected by the user for any one of the

following codes: USB (unipolar straight binary), BOB (bi-

polar offset binary) or, using an external inverter on the

MSB line, BTC (binary two’s complement). See Table I.

Unipolar offset drift is a measure of the change in output

with all 0s on the input over the specification temperature

range. Offset is measured at high temperature, +25°C, and

low temperature. The offset drift is the maximum change in

offset referred to the +25°C value, divided by the tempera-

ture change. It is expressed in parts per million of full scale

range per degree centigrade (ppm of FSR/°C).

DIGITAL INPUT

ANALOG OUTPUT

USB

BOB

Bipolar

Offset

Binary

BTC⁽¹⁾

Binary

Two’s

Unipolar

Straight

Binary

MSB

LSB

Complement

↓

111111111111

100000000000

011111111111 + 1/2 Full Scale – 1LSB

000000000000 Zero

+ Full Scale

+ 1/2 Full Scale

+ Full Scale

Zero

–1LSB

– Full Scale

+ Full Scale

Zero

Bipolar zero drift is measured at a digital input of 800₁₆, the

code that gives zero volts output for bipolar operation.

– Full Scale

NOTE: (1) Invert MSB of the BOB code with external inverter to obtain BTC code.

SETTLING TIME

Settling time is the total time (including slew time) for the

output to settle within an error band around its final value

after a change in input. Three settling times are specified to

±0.01% of full scale range (FSR): two for maximum full

scale range changes of 20V and 10V, and one for a 1LSB

change. The 1LSB change is measured at the major carry

(7FF₁₆to 800₁₆and 800₁₆to 7FF₁₆), the input transition at

which worst-case settling time occurs.

TABLE I. Digital Input Codes.

LINEARITY ERROR

Linearity error as used in D/A converter specifications by

Burr-Brown is the deviation of the analog output from a

straight line drawn between the end points (inputs all 1s and

all 0s). The DAC811 linearity error is specified at ±1/4LSB

(max) at +25°C for B and K grades, and ±1/2LSB (max) for

A, J, and R grades.

REFERENCE SUPPLY

DAC811 contains an on-chip 6.3V reference. This voltage

(pin 28) has a tolerance of ±0.1V. The reference output may

be used to drive external loads, sourcing at least 2mA. This

current should be constant for best performance of the D/A

converter.

DIFFERENTIAL LINEARITY ERROR

Differential linearity error (DLE) is the deviation from a

1LSB output change from one adjacent state to the next. A

DLE specification of 1/2LSB means that the output step size

can range from 1/2LSB to 3/2LSB when the input changes

from one state to the next. Monotonicity requires that DLE

be less than 1LSB over the temperature range of interest.

POWER SUPPLY SENSITIVITY

Power supply sensitivity is a measure of the effect of a

power supply change on the D/A converter output. It is

defined as a percent of FSR output change per percent of

change in either the positive, negative, or logic supply

voltages about the nominal voltages. Figure 1 shows typical

power supply rejection versus power supply ripple frequency.

MONOTONICITY

A D/A converter is monotonic if the output either increases

or remains the same for increasing digital inputs. All grades

of DAC811 are monotonic over their specification tempera-

ture range.

DAC811

The D/A latch is controlled by LDAC and WR. LDAC and

WR are internally NORed so that the latches transmit data to

the D/A switches when both LDAC and WR are at logic 0.

When either LDAC or WR are at logic 1, the data is latched

in the D/A latch and held until LDAC and WR go to logic 0.

0.1

–V_CC

V_DD

All latches are level-triggered. Data present when the con-

trol signals are logic 0 will enter the latch. When any one of

the control signals returns to logic 1, the data is latched.

Table II is a truth table for all latches.

0.01

+V_CC

0.001

0.0001

N_A

N_B

N_C

LDAC

OPERATION

100

10k

100k

No operation

Enables input latch 4MSBs

Enables input latch 4 middle bits

Enables input latch 4LSBs

Loads D/A latch from input latches

Makes all latches transparent

Frequency (Hz)

FIGURE 1. Power Supply Rejection vs Power Supply Ripple

Frequency.

“X” = Don’t care.

OPERATION

TABLE II. DAC813 Interface Logic Truth Table.

DAC811 is a complete single IC chip 12-bit D/A converter.

The chip contains a 12-bit D/A converter, voltage reference,

output amplifier, and microcomputer-compatible input logic

as shown in Figure 2.

GAIN AND OFFSET ADJUSTMENTS

Figures 3 and 4 illustrate the relationship of offset and gain

adjustments to unipolar and bipolar D/A converter output.

INTERFACE LOGIC

OFFSET ADJUSTMENT

Input latches A, B, and C hold data temporarily while a

complete 12-bit word is assembled before loading into the

D/A register. This double-buffered organization prevents the

generation of spurious analog output values. Each register is

independently addressable.

For unipolar (USB) configurations, apply the digital input

code that should produce zero voltage output, and adjust the

offset potentiometer for zero output. For bipolar (BOB,

BTC) configurations, apply the digital input code that should

produce the maximum negative output voltage and adjust

the offset potentiometer for minus full scale voltage. Ex-

ample: If the full scale range is connected for 20V, the

maximum negative output voltage is –10V. See Table III for

corresponding codes.

These input latches are controlled by N_A, N_B, N_C, and WR.

N_A, N_B, and N_Care internally NORed with WR so that the

input latches transmit data when both N_A(or N_B, N_C) and

WR are at logic 0. When either N_A, (N_B, N_C) or WR go to

logic 1, the input data is latched into the input registers and

held until both N_A(or N_B, N_C) and WR go to logic 0.

MSB D11

D0 LSB

11 12 13 14

19 18 17 16

R_BPO

N_A

N_B

N_C

4-Bit Latch, A

4-Bit Latch, B

4-Bit Latch, C

BPO

R_F

10V

Range

12-Bit D/A Latch

LDAC

R_F

12-Bit D/A Converter

V_OUT

Reference

ACOM

Ref Out 28

FIGURE 2. DAC811 Block Diagram.

DAC811

±12V OPERATION

The DAC811 is fully specified for operation on ±12V power

supplies. However, in order for the output to swing to ±10V,

the power supplies must be ±13.5V or greater. When oper-

ating with ±12VB supplies, the output swing should be

restricted to ±8V in order to meet specifications.

+ Full Scale

Range of

Gain Adjust

1LSB

LOGIC INPUT COMPATIBILITY

Gain Adjust

Rotates the Line

The DAC811 digital inputs are TTL, LSTTL, and 54/74HC

CMOS-compatible over the operating range of V_DD. The

input switching threshold remains at the TLL threshold over

the supply range.

All Bits

Logic 0

Range of

Offset Adj.

All Bits

Logic 1

The logic input current over temperature is low enough to

permit driving the DAC811 directly from the outputs of

4000B and 54/74C CMOS devices.

Digital Input

Offset Adjust Translates the Line

Resistors of 47Ω should be placed in series with D0 through

D11, WR, N_A, N_B, N_Cand LDAC if edges are <10ns or if

the logic input is driven below ground by undershoot.

FIGURE 3. Relationship of Offset and Gain Adjustments

for a Unipolar D/A Converter.

INSTALLATION

POWER SUPPLY CONNECTIONS

+ Full Scale

1LSB

For optimum performance and noise rejection, power supply

decoupling capacitors should be added as shown in Figure 5.

Range of

Gain Adjust

Full Scale

All Bits

These capacitors (1µF tantalum recommended) should be

located close to the DAC811.

Range

Gain Adjust

Rotates the Line

Logic 0

Bipolar V

Offset

All Bits

Logic 1

MSB on All

Others Off

Connect for

Range of

Offset Adjust

Bipolar Operation

V_DD

–V_CC

– Full Scale

BPO 27

Offset Adj.

Translates

the Line

1MΩ

Summing

Junction

10kΩ to

100kΩ

1µF

Digital Input

≈ ±0.4%

V_OUT

FIGURE 4. Relationship of Offset and Gain Adjustments

for a Bipolar D/A Converter.

+V_CC

ACOM 23

3.9MΩ

10kΩ to

100kΩ

Gain Adjust 22

ANALOG OUTPUT

–V_CC

+V_CC

DIGITAL INPUT

0 to +10V

±5V

±10V

+V_CC

MSB

↓

LSB

↓

111111111111

100000000000

011111111111

000000000000

LSB

+9.9976V

+5V

+4.9976V

–0.0024V

–5V

+9.9951V

–0.0049V

–10V

0.0022µF

1µF

2.4mV

2.44mV

4.88mV

1µF

DCOM 15

TABLE III. Digital Input/Analog Output.

GAIN ADJUSTMENT

For either unipolar or bipolar configurations, apply the

digital input that should give the maximum positive voltage

output. Adjust the gain potentiometer for this positive full

scale voltage. See Table III for positive full scale voltages.

FIGURE 5. Power Supply, Gain, and Offset Potentiometer

Connections.

DAC811

DAC811 features separate digital and analog power supply

returns to permit optimum connections for low noise and

high speed performance. The analog common (pin 23) and

digital common (pin 15) should be connected together at one

point. Separate returns minimize current flow in low level

signal paths if properly connected. Logic return currents are

not added into the analog signal return path. A ±0.5V

difference between ACOM and DCOM is permitted for

specified operation. High frequency noise on DCOM with

respect to ACOM may permit noise to be coupled through to

the analog output; therefore, some caution is required in

applying these common connections.

5.36kΩ

4.26kΩ

From Voltage

Reference

Bipolar Offset

26 Summing Junction

25 10V Range

From D/A

Converter

4.26kΩ

V_OUT

Analog Common

FIGURE 7. Output Amplifier Voltage Range Scaling Circuit.

The Analog Common is the high quality return for the D/A

converter and should be connected directly to the analog

reference point of the system. The load driven by the output

amplifier should be returned to the Analog Common.

OUTPUT

RANGE

DIGITAL

INPUT CODES

CONNECT

PIN 25 TO

CONNECT

PIN 27 TO

0 to +10V

±5

±10V

USB

BOB or BTC

EXTERNAL OFFSET AND GAIN ADJUSTMENT

TABLE IV. Output Range Connections.

Offset and Gain may be trimmed by installing external

Offset and Gain potentiometers. Connect these potentiom-

eters as shown in Figure 5. TCR of the potentiometers

should be 100ppm/°C or less. The 1MΩ and 3.9MΩ resis-

tors (20% carbon or better) should be located close to the

DAC811 to prevent noise pickup. If it is not convenient to

use these high value resistors, an equivalent “T” network, as

shown in Figure 6, may be substituted in each case. The

Gain Adjust (pin 22) is a high impedance point and a

0.001µF to 0.01µF ceramic capacitor should be connected

from this pin to Analog Common to reduce noise pickup in

all applications, including those not employing external gain

adjustment. Excessive capacitance on the Gain Adjust or

Offset Adjust pin may affect slew rate and settling time.

APPLICATIONS

MICROCOMPUTER BUS INTERFACING

The DAC811 interface logic allows easy interface to micro-

computer bus structures. The control signal WR is derived

from external device select logic and the I/O Write or

Memory Write (depending upon the system design) signals

from the microcomputer.

The latch enable lines N_A, N_B, N_Cand LDAC determine

which of the latches are enabled. It is permissible to enable

two or more latches simultaneously, as shown in some of the

following examples.

The double-buffered latch permits data to be loaded into the

input latches of several DAC811s and later strobed into the

D/A latch of all D/As, simultaneously updating all analog

outputs. All the interface schemes shown below use a base

address decoder. If blocks of memory are used, the base

address decoder can be simplified or eliminated altogether.

For instance, if half the memory space is unused, address

line A15 of the microcomputer can be used as the chip select

control.

1MΩ

100kΩ

180kΩ

100kΩ

12kΩ

3.9MΩ

180kΩ

10kΩ

4-BIT INTERFACE

FIGURE 6. Equivalent Resistances.

An interface to a 4-bit microcomputer is shown in Figure 8.

Each DAC811 occupies four address locations. A 74LS139

provides the two-to-four decoder and selects it with the base

address. Memory Write (WR) of the microcomputer is

connected directly to the WR pin of the DAC811. An 8205

decoder is an alternative to the 74LS139.

OUTPUT RANGE CONNECTIONS

Internal scaling resistors provided in the DAC811 may be

connected to produce bipolar output voltage ranges of ±10V

and ±5V or a unipolar output voltage range of 0 to +10V.

The 20V range (±10V bipolar range) is internally connected.

Refer to Figure 7. Connections for the output ranges are

listed in Table IV.

DAC811

8-BIT INTERFACE

16 D0

10 D8

17 D1

The control logic of DAC811 permits interfacing to right-

justified data formats, as illustrated in Figure 9. When a

12-bit D/A converter is loaded from an 8-bit bus, two bytes

of data are required. Figures 10 and 11 show an addressing

scheme for right-justified and left-justified data respectively.

The base address is decoded from the high-order address

bits. A₀and A₁address the appropriate latches. Note that

adjacent addresses are used. For the right-justified case,

X10₁₆loads the 8LSBs, and X01₁₆loads the 4MSBs and

simultaneously transfers input latch data to the D/A latch.

Addresses X00₁₆and X11₁₆are not used.

DB0

DB1

DB2

DB3

18 D2

D10

19 D3

D11

14 D4

13 D5

12 D6

11 D7

DB4

DB5

DB6

DB7

Left-justified data is handled in a similar manner, shown in

Figure 11. The DAC811 still occupies two adjacent loca-

tions in the microcomputer's memory map.

A₁₅

Base

Address

Decoder

16 D0

A₂

A₁

14 D4

10 D8

17 D1

13 D5

DB0

DB1

DB2

DB3

LDAC

N_A

N_B

A₀

N_C

18 D2

12 D6

FIGURE 10. Right-Justified Data Bus Interface.

D10

19 D3

11 D7

14 D4

13 D5

DB0

DB1

DB2

DB3

D11

12 D6

11 D7

10 D8

16 D0

A_N

Base

Address

Decoder

(Chip

A₂

Select)

A₁

LDAC

N_A

17 D1

A₁

A₀

D10

DB4

DB5

DB6

DB7

A₀

N_B

18 D2

1/2

74LS139

N_C

D11

19 D3

FIGURE 8. Addressing and Control for 4-Bit Microcom-

puter Interface.

A₁₅

A₂

Base

Address

Decoder

D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

LDAC

N_A

A₁

a. Right-Justified

N_B

D11 D10 D9 D8 D7 D6 D5 D4

D3 D2 D1 D0

A₀

N_C

b. Left-Justified

FIGURE 11. Left-Justified Data Bus Interface.

FIGURE 9. 12-Bit Data Format for 8-Bit Systems.

DAC811

INTERFACING MULTIPLE DAC811s

IN 8-BIT SYSTEMS

eight address spaces for other uses. Incorporate A₃into the

base address decoder, remove the inverter, connect the

common LDAC line to N_Cof D/A #4, and connect D1 of the

74LS138 to +5V.

Many applications, such as automatic test systems, require

that the outputs of several D/A converters be updated simul-

taneously. The interface shown in Figure 12 uses a 74LS138

decoder to decode a set of eight adjacent addresses, to load

the input latches of four DAC811s. The example shows a

right-justified data format.

12- AND 16-BIT MICROCOMPUTER INTERFACE

For this application, the input latch enable lines, N_A, N_Band

N_C,are tied low, causing the latches to be transparent. The

D/A latch, and therefore DAC811, is selected by the address

decoder and strobed by WR.

A ninth address using A₃causes all DAC811s to be updated

simultaneously. If a particular DAC811 is always loaded

last—for instance, D/A #4—A₃is not needed, thus saving

A₁₅

LDAC

N_C

Base

Address

Decoder

DAC811

(1)

A₄

A₃

N_B

ADDRESS BUS

N_A

OPERATION

Load 8 LSB – D/A #1

Load 4 MSB – D/A #1

Load 8 MSB – D/A #2

Load 4 MSB – D/A #2

Load 8 MSB – D/A #3

Load 4 MSB – D/A #3

Load 8 MSB – D/A #4

Load 4 MSB – D/A #4

Load D/A Latch—All D/A

LDAC

N_C

74LS138

G_2A

DAC811

(2)

N_B

G_2B

N_A

G₁

LDAC

N_C

DAC811

(4)

A₂

A₁

A₀

N_B

N_A

FIGURE 12. Interfacing Multiple DAC811s to an 8-Bit Bus.

DAC811

DAC811BH相关文章

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DAC811BH产品参数

型号:	DAC811BH
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	BURR-BROWN CORP
包装说明：	0.600 INCH, CERAMIC, DIP-28
Reach Compliance Code：	unknown
风险等级：	5.71
Is Samacsys：	N
最大模拟输出电压：	10 V
最小模拟输出电压：	-10 V
转换器类型：	D/A CONVERTER
输入位码：	BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY
输入格式：	PARALLEL, WORD
JESD-30 代码：	R-CDIP-T28
JESD-609代码：	e0
最大线性误差 (EL)：	0.0061%
标称负供电电压：	-15 V
位数：	12
功能数量：	1
端子数量：	28
最高工作温度：	85 °C
最低工作温度：	-25 °C
封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP
封装等效代码：	DIP28,.6
封装形状：	RECTANGULAR
封装形式：	IN-LINE
电源：	5,+-12/+-15 V
认证状态：	Not Qualified
最大稳定时间：	4 µs
标称安定时间 (tstl)：	3 µs
子类别：	Other Converters
最大压摆率：	75 mA
标称供电电压：	15 V
表面贴装：	NO
技术：	BIPOLAR
温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
Base Number Matches：	1

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