DAC8554IPW原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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DAC8554

SLAS431A–JUNE 2005–REVISED AUGUST 2005

16-BIT, QUAD CHANNEL, ULTRALOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

FEATURES

DESCRIPTION

•

Relative Accuracy: 12 LSB (Max)

The DAC8554 is a 16-bit, quad channel, voltage

output, digital-to-analog converter (DAC), offering

Glitch Energy: 0.15 nV-s

low-power operation and

a flexible serial host

Power Supply: +2.7 V to +5.5 V

MicroPower Operation: 850 µA at 5 V

16-Bit Monotonic Over Temperature

Settling Time: 10 µs to ±0.003% FSR

Ultra-Low AC Crosstalk: –100 dB Typ

Power-On Reset to Zero-Scale

interface. It offers monotonicity, good linearity, and

exceptionally low glitch. Each on-chip precision out-

put amplifier allows rail-to-rail output swing to be

achieved over the supply range of 2.7 V to 5.5 V. The

device supports a standard 3-wire serial interface

capable of operating with input data clock frequencies

up to 50 MHz for IOV_DD= 5 V.

On-Chip Output Buffer Amplifier With

Rail-to-Rail Operation

The DAC8554 requires an external reference voltage

to set the output range of each DAC channel. Also

incorporated into the device is a power-on reset

circuit which ensures that the DAC outputs power up

at zero-scale and remain there until a valid write

takes place. The DAC8554 provides a per channel

power-down feature, accessed over the serial

interface, that reduces the current consumption to

200 nA per channel at 5 V.

•

Double Buffered Input Architecture

Simultaneous or Sequential Output Update

and Power-Down

•

16-Channel Broadcast Capability

Schmitt-Triggered Inputs

SPI Compatible Serial Interface: Up to 50 MHz

1.8 V to 5.5 V Logic Compatibility

Available in a TSSOP-16 Package

The low-power consumption of this device in normal

operation makes it ideally suited to portable battery-

operated equipment and other low-power appli-

cations. The power consumption is 4.25 mW at 5 V,

reducing to 4 µW in power-down mode.

APPLICATIONS

•

Portable Instrumentation

Closed-Loop Servo-Control

Process Control

Data Acquisition Systems

Programmable Attenuation

PC Peripherals

The DAC8554 is available in a TSSOP-16 package

with a specified operating temperature range of

–40°C to 105°C.

V

ref

H

AV

IOV

DD

Data

DAC

DAC A

DAC D

V

A

OUT

Buffer A

Register A

B

C

D

OUT

Data

Buffer D

DAC

Register D

18

Buffer

Control

Register

Control

SYNC

SCLK

24-Bit

Serial-to-

Parallel Shift

Register

Power-Down

Control Logic

8

D

IN

Resistor

Network

A0

A1

LDAC ENABLE

V L

ref

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI, QSPI are trademarks of Motorola.

Microwire is a trademark of National Semiconductor.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications. This device is rated at 1500 V HBM and 1000

V CDM.

PACKAGING/ORDERING INFORMATION

PACKAGE

LEAD

PACKAGE

DESIGNATOR⁽¹⁾

SPECIFICATION

TEMPERATURE RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

DAC8554IPW

Tube, 90

DAC8554

TSSOP-16

PW

–40°C TO 105°C

D8554

DAC8554IPWR

Tape and Reel, 2000

(1) For the most current specifications and package information, refer to our web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

UNIT

AV_DDto GND

–0.3 V to 6 V

–0.3 V to AV_DD+ 0.3 V

–40°C to 105°C

–65°C to 150°C

150°C

Digital input voltage to GND

V_O(A)to V_O(D)to GND

Operating temperature range

Storage temperature range

Junction temperature range (T_Jmax)

Power dissipation

(T_Jmax – T_A)/θ_JA

118°C/W

θ_JAThermal impedance

θ_JCThermal impedance

29°C/W

Vapor phase (60 s)

Lead temperature, soldering

Infrared (15 s)

215°C

220°C

(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

STATIC PERFORMANCE⁽¹⁾

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

16

Bits

Relative accuracy

Measured by line passing through codes 485 and

64741

±4

±12

LSB

Differential nonlinearity

Zero-scale error

16-bit Monotonic

±0.25

±1

LSB

mV

Measured by line passing through codes 485 and

64741

±2

±12

Zero-scale error drift

Full-scale error

±5

µV/°C

Measured by line passing through codes 485 and

64741, AV_DD= 5 V, V_ref= 4.99 V

±0.3

±0.5

% of FSR

Gain error

Measured by line passing through codes 485 and

64741, AV_DD= 5 V

±0.05

±0.15

% of FSR

Gain temperature coefficient

±1

8

ppm of FSR/°C

mV

Power Supply Rejection Ratio

(PSRR)

R_L= 2 kΩ, C_L= 200 pF

0.75

mV/V

(1) Linearity calculated using a reduced code range of 485 to 64741; output unloaded.

2

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

OUTPUT CHARACTERISTICS⁽²⁾

Output voltage range

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0

V_ref

H

V

Output voltage settling time

To ±0.003% FSR, 0200_Hto FD00_H, R_L= 2 kΩ, 0 pF

8

10

µs

< C_L< 200 pF

R_L= 2 kΩ, C_L= 500 pF

12

1.8

µs

V/µs

pF

Slew rate

R_L= ∞

470

Capacitive load stability

R_L= 2 kΩ

1000

0.15

0.25

pF

Code change glitch impulse

Digital feedthrough

DC crosstalk

1 LSB change around major carry

nV-s

LSB

Full-scale swing on adjacent channel. AV_DD= 5 V,

V_ref= 4.096 V

AC crosstalk

1 kHz sine wave

–100

1

dB

DC output impedance

At mid-point input

Ω

AV_DD= 5 V

50

20

2.5

5

Short-circuit current

Power-up time

mA

µs

AV_DD= 3 V

Coming out of power-down mode AV_DD= 5 V

Coming out of power-down mode AV_DD= 3 V

AC PERFORMANCE

SNR (1st 19 harmonics removed)

THD

95

-85

87

BW = 20 kHz, AV_DD= 5 V, F_OUT= 1 kHz

dB

SFDR

SINAD

84

REFERENCE INPUT

V_ref(H)Voltage

V_ref(L)Voltage

V_ref(L)< V_ref(H), AV_DD- (V_ref(H)+ V_ref(L)) /2 > 1.2 V

V_ref(L)= GND, V_ref(H)= AV_DD= 5 V

V_ref(L)= GND, V_ref(H)= AV_DD= 3 V

V_ref(L)< V_ref(H)

0

AV_DD

AV_DD/2

250

V

180

120

31

µA

kΩ

Reference input current

200

Reference input impedance

(3)

LOGIC INPUTS

0.3 ×

I0V_DD

2.7 V ≤ IOV_DD≤ 5.5 V

1.8 V ≤ IOV_DD≤ 2.7 V

2.7 ≤ IOV_DD≤ 5.5 V

1.8 ≤ IOV_DD< 2.7 V

V_I(L), logic input LOW voltage

V_I(H), logic input HIGH voltage

V

0.1 ×

I0V_DD

0.7 ×

I0V_DD

V

0.95 ×

I0V_DD

Pin capacitance

POWER REQUIREMENTS

AV_DD

3

pF

2.7

1.8

5.5

V

IOV_DD

AI_DD(normal mode)

Input code = 32768, reference current included, no

load

(2) Ensured by design and characterization, not production tested.

(3) Ensured by design and characterization, not production tested.

3

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

10

MAX

20

UNIT

IOI_DD

µA

AV_DD= 3.6 V to 5.5 V

AV_DD= 2.7 V to 3.6 V

AI_DD(all power-down modes)

AV_DD= 3.6 V to 5.5 V

AV_DD= 2.7 V to 3.6 V

POWER EFFICIENCY

I_OUT/I_DD

V_IH= IOV_DDand V_IL= GND

0.65

0.6

1.0

mA

µA

0.96

V_IH= IOV_DDand V_IL= GND

I_L= 2 mA, AV_DD= 5 V

0.2

2

0.05

89%

TEMPERATURE RANGE

Specified performance

–40

105

°C

PIN CONFIGURATION

1

2

3

4

5

6

7

8

V_OUT

V_REF

AV_DD

V_REF

GND

A

16 LDAC

15

14

13

12

B

ENABLE

A1

H

A0

DAC8554

L

IOV_DD

11 D_IN

V_OUT

C

D

10 SCLK

V_OUT

9

SYNC

PIN DESCRIPTIONS

1

NAME

DESCRIPTION

V_OUT

A

B

Analog output voltage from DAC A.

Analog output voltage from DAC B.

Positive reference voltage input.

Power supply input, 2.7 V to 5.5 V.

Negative reference voltage input.

2

3

V_ref

AV_DD

V_ref

GND

H

4

5

L

6

Ground reference point for all circuitry on the part.

Analog output voltage DAC C.

7

V_OUT

C

8

D

Analog output voltage DAC D.

Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When

SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the

following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge

in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the

DAC8554).

9

SYNC

10

11

SCLK

D_IN

Serial clock input. Data can be transferred at rates up to 50 MHz.

Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock

input.

12

13

14

15

IOV_DD

A0

Digital input-output power supply

Address 0 — sets device address, see Table 2

Address 1 — sets device address, see Table 2

Active LOW, ENABLE LOW connects the SPI interface to the serial port.

A1

ENABLE

4

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

PIN DESCRIPTIONS (continued)

16

NAME

DESCRIPTION

LDAC

Load DACs, rising edge triggered, loads all DAC registers.

TIMING REQUIREMENTS⁽¹⁾⁽²⁾

AV_DD= 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

IOV_DD= AV_DD= 2.7 V to 3.6 V

40

ns

20

(3)

t ₁

t ₂

t ₃

t ₄

t ₅

t ₆

t ₇

SCLK cycle time

IOV_DD= AV_DD= 3.6 V to 5.5 V

IOV_DD= AV_DD= 2.7 V to 3.6 V

IOV_DD= AV_DD= 3.6 V to 5.5 V

IOV_DD= AV_DD= 2.7 V to 3.6 V

IOV_DD= AV_DD= 3.6 V to 5.5 V

IOV_DD= AV_DD= 2.7 V to 3.6 V

IOV_DD= AV_DD= 3.6 V to 5.5 V

IOV_DD= AV_DD= 2.7 V to 3.6 V

IOV_DD= AV_DD= 3.6 V to 5.5 V

IOV_DD= AV_DD= 2.7 V to 3.6 V

IOV_DD= AV_DD= 3.6 V to 5.5 V

IOV_DD= AV_DD= 2.7 V to 3.6 V

IOV_DD= AV_DD= 3.6 V to 5.5 V

IOV_DD= AV_DD= 2.7 V to 3.6 V

IOV_DD= AV_DD= 3.6 V to 5.5 V

IOV_DD= AV_DD= 2.7 V to 5.5 V

20

ns

10

SCLK HIGH time

20

ns

10

SCLK LOW time

0

SYNC falling edge to SCLK rising edge setup time

Data setup time

ns

0

5

ns

5

4.5

Data hold time

ns

4.5

0

24th SCLK falling edge to SYNC rising edge

ns

0

40

ns

20

t ₈

t ₉

Minimum SYNC HIGH time

24th SCLK falling edge to SYNC falling edge

130

ns

(1) All input signals are specified with t_R= t_F= 3 ns (10% to 90% of AV_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

(2) See Serial Write Operation timing diagram.

(3) Maximum SCLK frequency is 50 MHz at IOV_DD= AV_DD= 3.6 V to 5.5 V and 25 MHz at IOV_DD= AV_DD= 2.7 V to 3.6 V.

SERIAL WRITE OPERATION

t₁

t₉

SCLK

1

24

t₂

t₈

t₃

t₇

t₄

SYNC

t₆

t₅

DB23

DB0

DB23

D_IN

5

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

TYPICAL CHARACTERISTICS

At T_A= 25°C, unless otherwise noted

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR

vs

LINEARITY ERROR

vs

DIGITAL INPUT CODE

8

6

8

6

AV

= 5 V, V = 4.99 V

ref

Channel A

DD

AV

= 5 V, V = 4.99 V

ref

Channel B

DD

4

2

4

2

0

−2

−4

−6

−8

−2

−4

−6

−8

1

0.5

0

1

0.5

0

−0.5

−1

−0.5

−1

8192

0

16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192

16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 1.

Figure 2.

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR

vs

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR

vs

DIGITAL INPUT CODE

8

6

4

2

0

−2

−4

−6

−8

8

6

4

2

0

−2

−4

−6

−8

AV

= 5 V,

V

ref

= 4.99 V

Channel C

DD

AV

= 5 V, V = 4.99 V

ref

Channel D

DD

1

0.5

0

0.5

0

−0.5

−1

−0.5

−1

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 3.

Figure 4.

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR

vs

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR

vs

DIGITAL INPUT CODE

8

6

4

2

0

−2

−4

8

6

4

2

0

−2

−4

−6

−8

AV

= 2.7 V,

V

ref

= 2.69 V

Channel B

Channel A

AV

= 2.7 V,

V

ref

= 2.69 V

DD

−6

−8

1

0.5

0

1

0.5

0

−0.5

−1

−0.5

−1

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 5.

Figure 6.

6

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, unless otherwise noted

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR

vs

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR

vs

DIGITAL INPUT CODE

8

6

4

2

8

Channel C

Channel D

AV

= 2.7 V, V = 2.69 V

ref

AV

= 2.7 V, V = 2.69 V

DD ref

6

4

2

DD

0

−2

−4

−6

−8

−2

−4

−6

−8

1

0.5

0

1

0.5

0

−0.5

−1

−0.5

−1

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 7.

Figure 8.

ZERO-SCALE ERROR

vs

ZERO-SCALE ERROR

vs

TEMPERATURE

5

AV = 2.7 V, V = 2.69 V

DD ref

AV

= 5 V, V = 4.99 V

ref

DD

CH C

2.5

0

CH A

CH B

0

−2.5

−5

CH D

CH B

−2.5

−5

−40

0

40

80

120

−40

0

40

80

120

T − Temperature − °C

A

T

A

− Temperature − °C

Figure 9.

Figure 10.

FULL-SCALE ERROR

vs

FULL-SCALE ERROR

vs

TEMPERATURE

0

−5

AV

= 5 V, V = 4.99 V

ref

AV

= 2.7 V, V = 2.69 V

ref

DD

−5

−10

−15

CH C

CH A

−10

−15

−20

−25

CH D

CH C

CH B

CH A

CH B

CH D

−20

−25

−40

0

40

80

120

−40

0

40

80

120

T

A

− Temperature − °C

T

A

− Temperature − °C

Figure 11.

Figure 12.

7

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, unless otherwise noted

SINK CURRENT CAPABILITY (ALL CHANNELS)

SOURCE CURRENT CAPABILITY (ALL CHANNELS)

0.150

6

V

AV −10 mV

DD

ref =

DAC Loaded With FFFF

V

= AV −10 mV

DD

ref

DAC Loaded With 0000

H

0.125

0.100

0.075

0.050

0.025

0

V

= 5.5 V

DD

5.6

5.2

4.8

4.4

4

V = 5.5 V

DD

V

= 2.7 V

DD

0

2

4

I

6

8

10

0

2

4

I

6

8

10

(mA)

SINK

SIOURCE

Figure 13.

Figure 14.

SOURCE CURRENT CAPABILITY (ALL CHANNELS)

SUPPLY CURRENT

vs

DIGITAL INPUT CODE

3

1200

V

AV −10 mV

DD

ref =

DAC Loaded With FFFF

Reference Current Included

H

1000

800

600

400

200

0

2.7

2.4

2.1

1.8

1.5

AV

V

= 5.5 V

DD = ref

AV

= 2.7 V

DD

AV

V

= 2.7 V

DD = ref

0

2

4

I

6

(mA)

8

10

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

SIOURCE

Figure 15.

Figure 16.

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

1200

1000

800

900

850

800

750

700

650

600

Reference Current Included

V

AV

All DACs Powered,

DD

ref =

Reference Current Included, No Load

AV

V

= 5.5 V

DD = ref

AV

V

= 2.7 V

DD = ref

600

400

200

0

2.7

3.05

3.4

3.75

4.1

V (V)

DD

4.45

4.8

5.15

5.5

−40

0

40

80

120

T

A

− Temperature − °C

Figure 17.

Figure 18.

8

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, unless otherwise noted

SUPPLY CURRENT

vs

LOGIC INPUT VOLTAGE

SUPPLY CURRENT

vs

LOGIC INPUT VOLTAGE

2000

800

600

400

200

0

T

= 25°C, SYNC Input (All Other Inputs = GND

A

T

A

= 25°C, SYNC Input (All Other Inputs = GND

CHA Powered Up; All Other Channels in Powerdown

Reference Current Included

CHA Powered Up; All Other Channels in Powerdown

Reference Current Included

1600

1200

800

400

0

IOV

DD

=

AV

= V = 5 V

ref

DD

IOV

DD

=

AV

= V = 2.7 V

ref

DD

0

0.5

1

1.5

(V)

2

2.5

0

1

2

3

4

5

V

(V)

LOGIC

V

LOGIC

Figure 19.

HISTOGRAM OF CURRENT CONSUMPTION

Figure 20.

HISTOGRAM OF CURRENT CONSUMPTION

1500

1000

500

0

AV

V

= 5 V

AV

V

= 2.7 V

DD = ref

Reference Current Included

DD = ref

Reference Current Included

1000

500

0

600 625 650 675 700 725 750 775 800 825 850 875

725 750 775 800 825 850 875 900 925 950 975

(µA)

I

(µA)

DD

Figure 21.

Figure 22.

POWER SPECTRAL DENSITY

TOTAL HARMONIC DISTORTION

vs

OUTPUT FREQUENCY

−40

−50

−60

−70

−80

−90

−100

AV

V

= 5 V,

−10

AV

= V = 5 V,

ref

DD

= 4.096,

DD

−1 dB FSR Digital Input, F = 1 MSPS

s

Measurement Bandwidth = 20 kHz

ref

f

= 1 MSPS,

= 1 kHz,

clk

−30

−50

F

out

THD = 79 dB,

SNR = 96 dB

THD

−70

2nd Harmonic

−90

3rd Harmonic

−110

−130

0

5000

10000

15000

20000

0

1

2

3

4

5

Output Tone (kHz)

Frequency − Hz

Figure 23.

Figure 24.

9

DAC8554

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SLAS431A–JUNE 2005–REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, unless otherwise noted

FULL-SCALE SETTLING TIME: 5 V RISING EDGE

FULL-SCALE SETTLING TIME: 5 V FALLING EDGE

Trigger Pulse

5 V/div

Trigger Pulse

5 V/div

AV

ref

= 5 V,

DD

= 4.096 V,

AV

= 5 V,

DD

V = 4.096 V,

ref

V

From Code: 0000

To Code: FFFF

From Code: FFFF

To Code: 0000

Falling

Edge

1 V/div

Rising

Edge

1 V/div

Zoomed Falling Edge

1 mV/div

Zoomed Rising Edge

1 mV/div

Time (2 µs/div)

Figure 25.

Figure 26.

HALF-SCALE SETTLING TIME: 5 V FALLING EDGE

HALF-SCALE SETTLING TIME: 5 V RISING EDGE

Trigger Pulse

5 V/div

Trigger Pulse

5 V/div

Falling

Edge

1 V/div

AV

ref

= 5 V,

DD

= 4.096 V,

V

AV

V

= 5 V,

From Code: CFFF

To Code: 4000

DD

= 4.096 V,

ref

From Code: 4000

To Code: CFFF

Rising

Edge

1 V/div

Zoomed Rising Edge

1 mV/div

Zoomed Falling Edge

1 mV/div

Time (2 µs/div)

Figure 27.

Figure 28.

FULL-SCALE SETTLING TIME: 2.7 V RISING EDGE

FULL-SCALE SETTLING TIME: 2.7 V FALLING EDGE

Trigger Pulse

2.7 V/div

Trigger Pulse

2.7 V/div

Rising

AV

V

= 2.7 V,

AV

V

= 2.7 V,

DD

= 2.5 V,

DD

= 2.5 V,

Edge

ref

0.5 V/div

From Code: FFFF

To Code: 0000

From Code: 0000

To Code: FFFF

Zoomed Falling Edge

1 mV/div

Falling

Edge

0.5 V/div

Zoomed Rising Edge

1 mV/div

Time (2 µs/div)

Figure 29.

Figure 30.

10

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, unless otherwise noted

HALF-SCALE SETTLING TIME: 2.7 V RISING EDGE

HALF-SCALE SETTLING TIME: 2.7 V FALLING EDGE

Trigger Pulse

2.7 V/div

Trigger Pulse

2.7 V/div

AV

ref

= 2.7 V,

DD

= 2.5 V,

V

= 2.7 V

= 2.5 V

DD

V

From Code: CFFF

To Code: 4000

REF

From code; 4000

To code: CFFF

Falling

Edge

0.5 V/div

Rising

Edge

0.5 V/div

Zoomed Rising Edge

1 mV / div

Zoomed Falling Edge

1 mV/div

Time (2 µs/div)

Time − 2 ms/div

Figure 31.

Figure 32.

GLITCH ENERGY: 5 V, 1 LSB STEP, RISING EDGE

GLITCH ENERGY: 5 V, 1 LSB STEP, FALLING EDGE

AV

ref

= 5 V,

DD

= 4.096 V

V

From Code: 8000

To Code: 7FFF

Glitch: 0.16 nV-s

Measured Worst Case

AV

= 5 V,

DD

= 4.096 V

V

ref

From Code: 7FFF

To Code: 8000

Glitch: 0.08 nV-s

Time 400 ns/div

Figure 33.

Figure 34.

GLITCH ENERGY: 5 V, 16 LSB STEP, RISING EDGE

GLITCH ENERGY: 5 V, 16 LSB STEP, FALLING EDGE

AV

ref

= 5 V,

DD

= 4.096 V

V

From Code: 8010

To Code: 8000

Glitch: 0.08 nV-s

AV

ref

= 5 V,

DD

= 4.096 V

V

From Code: 8000

To Code: 8010

Glitch: 0.04 nV-s

Time 400 ns/div

Figure 35.

Figure 36.

11

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, unless otherwise noted

GLITCH ENERGY: 5 V, 256 LSB STEP, RISING EDGE

GLITCH ENERGY: 5 V, 256 LSB STEP, FALLING EDGE

AV

ref

= 5 V,

DD

= 4.096 V

V

From Code: 80FF

To Code: 8000

Glitch: Not Detected

Theoretical Worst Case

AV

ref

= 5 V,

DD

= 4.096 V

V

From Code: 8000

To Code: 80FF

Glitch: Not Detected

Theoretical Worst Case

Time 400 ns/div

Figure 37.

Figure 38.

GLITCH ENERGY:; 2.7 V, 1 LSB STEP, RISING EDGE

GLITCH ENERGY: 2.7 V, 1 LSB STEP, FALLING EDGE

AV

V

= 2,7 V,

DD

= 2.5 V

AV

V

= 2.7 V,

DD

= 2.5 V

ref

From Code: 7FFF

To Code: 8000

ref

From Code: 8000

To Code: 7FFF

Glitch: 0.08 nV-s

Glitch: 0.16 nV-s

Measured Worst Case

Time 400 ns/div

Figure 39.

Figure 40.

GLITCH ENERGY: 2.7 V, 16 LSB STEP, RISING EDGE

GLITCH ENERGY: 2.7 V, 16 LSB STEP, FALLING EDGE

AV

ref

= 2.7 V,

DD

= 2.5 V

V

From Code: 8010

To Code: 8000

Glitch: 0.12 nV-s

AV

ref

= 2.7 V,

DD

= 2.5 V

V

From Code: 8000

To Code: 8010

Glitch: 0.04 nV-s

Time 400 ns/div

Figure 41.

Figure 42.

12

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, unless otherwise noted

GLITCH ENERGY: 2.7 V, 16 LSB STEP, RISING EDGE

GLITCH ENERGY: 2.7 V, 16 LSB STEP, FALLING EDGE

AV

ref

= 2.7 V,

DD

= 2.5 V

V

From Code: 80FF

To Code: 8000

Glitch: Not Detected

Theoretical Worst Case

AV

V

= 2.7 V,

DD

= 2.5 V

ref

From Code: 8000

To Code: 80FF

Glitch: Not Detected

Theoretical Worst Case

Time 400 ns/div

Figure 43.

Figure 44.

OUTPUT NOISE DENSITY

SIGNAL-TO-NOISE RATIO

vs

OUTPUT FREQUENCY

98

96

94

92

90

88

86

84

350

300

250

200

150

100

AV

= V = 5 V,

ref

DD

AV

= 5 V,

= 4.096 V,

DD

−1 dB FSR Digital Inputs, F = 1 MSPS

s

V

ref

Measurement Bandwidth = 20 kHz

Code = 7FFF

No Load

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

100

1000

10000

Frequency − Hz

100000

Output Tone (kHz)

Figure 45.

Figure 46.

13

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

THEORY OF OPERATION

V_REF

H

DAC SECTION

The architecture of each channel of the DAC8554

consists of a resistor-string DAC followed by an

output buffer amplifier. Figure 47 shows a simplified

block diagram of the DAC architecture.

R_DIVIDER

V_REF

2

Ω

R

Ω

62

To Output

Amplifier

(2x Gain)

Figure 47. DAC8554 Architecture

The input coding for each device is unipolar straight

binary, so the ideal output voltage is given by:

D

IN

_{L )}ƪ_VREF

_Lƫ

REF

V

X + 2 V

H * V

R

OUT

REF

65536

where D_IN= decimal equivalent of the binary code

that is loaded to the DAC register; it can range from 0

to 65535.

RESISTOR STRING

The resistor string section is shown in Figure 48. It is

simply a divide-by-2 resistor followed by a string of

resistors. The code loaded into the DAC register

determines at which node on the string the voltage is

tapped off. This voltage is then applied to the output

amplifier by closing one of the switches connecting

the string to the amplifier.

V_REF

L

Figure 48. Resistor String

The write sequence begins by bringing the SYNC line

LOW. Data from the D_INline is clocked into the 24-bit

shift register on each falling edge of SCLK. The serial

clock frequency can be as high as 50 MHz, making

the DAC8554 compatible with high-speed DSPs. On

the 24th falling edge of the serial clock, the last data

bit is clocked into the shift register and the shift

register gets locked. Further clocking does not

change the shift register data. Once 24 bits are

locked into the shift register, the 8 MSBs are used as

control bits and the 16 LSBs are used as data. After

receiving the 24th falling clock edge, DAC8554 de-

codes the 8 control bits and 16 data bits to perform

the required function, without waiting for a SYNC

rising edge. A new SPI sequence starts at the next

falling edge of SYNC. A rising edge of SYNC before

the 24-bit sequence is complete resets the SPI

interface; no data transfer occurs.

OUTPUT AMPLIFIER

Each output buffer amplifier is capable of generating

rail-to-rail voltages on its output which approaches an

output range of 0 V to AV_DD(gain and offset errors

must be taken into account). Each buffer is capable

of driving a load of 2 kΩ in parallel with 1000 pF to

GND. The source and sink capabilities of the output

amplifier can be seen in the typical characteristics.

SERIAL INTERFACE

The DAC8554 uses a 3-wire serial interface ( SYNC,

SCLK, and D_IN), which is compatible with SPI™,

QSPI™, and Microwire™ interface standards, as well

as most DSPs. See the serial write operation timing

diagram for an example of a typical write sequence.

After the 24th falling edge of SCLK is received, the

SYNC line may be kept LOW or brought HIGH. In

either case, the minimum delay time from the 24th

falling SCLK edge to the next falling SYNC edge

must be met in order to properly begin the next cycle.

14

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

To assure the lowest power consumption of the

device, care should be taken that the levels are as

close to each rail as possible. (Refer to the Typical

Characteristics section for the Supply Current vs

Logic Input Voltage transfer characteristic curve.

Care bit which does not affect the operation of the

DAC8554 and can be 1 or 0. The DAC channel select

bits (DB18, DB17) control the destination of the data

(or power-down command) from DAC A through DAC

D. The final control bit, PD0 (DB16), selects the

power-down mode of the DAC8554 channels.

IOV_DDAND VOLTAGE TRANSLATORS

The DAC8554 also supports a number of different

load commands. The load commands include broad-

cast commands to address all the DAC8554s on an

SPI bus. The load commands can be summarized as

follows:

The IOV_DDpin powers the digital input structures of

the DAC8554. For single-supply operation, it can be

tied to AV_DD. For dual-supply operation, the IOV_DDpin

provides interface flexibility with various CMOS logic

families and it should be connected to the logic

supply of the system. Analog circuits and internal

logic of the DAC8554 use AV_DDas the supply

voltage. The external logic high inputs get translated

to AV_DDby level shifters. These level shifters use the

IOV_DDvoltage as a reference to shift the incoming

logic HIGH levels to AV_DD. IOV_DDis ensured to

operate from 2.7 V to 5.5 V regardless of the AV_DD

voltage, which ensures compatibility with various logic

families. Although specified down to 2.7 V, IOV_DDwill

operate at as low as 1.8 V with degraded timing and

temperature performance. For lowest power con-

sumption, logic V_IHlevels should be as close as

possible to IOV_DD, and logic V_ILlevels should be as

close as possible to GND voltages

DB21 = 0 and DB20 = 0: Single-channel store. The

temporary register (data buffer) corresponding to a

DAC selected by DB18 and DB17 is updated with the

contents of SR data (or power-down).

DB21 = 0 and DB20 = 1: Single-channel update. The

temporary register and DAC register corresponding to

a DAC selected by DB18 and DB17 are updated with

the contents of SR data (or power-down).

DB21 = 1 and DB20 = 0: Simultaneous update. A

channel selected by DB18 and DB17 gets updated

with the SR data, and simultaneously, all the other

channels get updated with previous stored data (or

power-down) from temporary registers.

DB21 = 1 and DB20 = 1: Broadcast update. All the

DAC8554s on the SPI bus respond, regardless of

address matching. If DB18 = 0, then SR data gets

ignored, all channels from all DAC8554s get updated

with previously stored data (or power-down). If DB18

= 1, then SR data (or power-down) updates all

channels of all DAC8554s in the system. This broad-

cast update feature allows the simultaneous update

of up to 16 channels.

INPUT SHIFT REGISTER

The input shift register (SR) of the DAC8554 is 24

bits wide, as shown in Figure 49, and is made up of 8

control bits (DB23–DB16) and 16 data bits

(DB15–DB0). The first two control bits (DB23 and

DB22) are the address match bits. The DAC8554

offers additional hardware-enabled addressing capa-

bility allowing a single host to talk to up to four

DAC8554s through a single SPI bus without any glue

logic, enabling up to 16-channel operation. The state

of DB23 should match the state of pin A1; similarly,

the state of DB22 should match the state of pin A0. If

there is no match, the control command and the data

(DB21...DB0) are ignored by the DAC8554. That is, if

there is no match, the DAC8554 is not addressed.

Address matching can be overridden by the broad-

cast update, as will be explained.

Power-down/data selection is as follows:

DB16 is a power-down flag. If this flag is set, then

DB15 and DB14 select one of the four power-down

modes of the device as described in Table 1. If DB16

= 1, DB15 and DB14 no longer represent the two

MSBs of data, they represent a power-down condition

described in Table 1. Similar to data, power-down

conditions can be stored at the temporary registers of

each DAC. It is possible to update DACs simul-

taneously either with data, power-down, or a combi-

nation of both.

LD1 (DB21) and LD0 (DB20) control the updating of

each analog output with the specified 16-bit data

value or power-down command. Bit DB19 is a Don't

Refer to Table 2 for more information.

15

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

Table 1. DAC8554 Power-Down Modes

PD0 (DB16)

PD1 (DB15)

PD2 (DB14)

OPERATING MODE

1

0

1

0

1

0

1

Output high impedance

Output typically 1 kΩ to GND

Output typically 100 kΩ to GND

Output high impedance

SYNC INTERRUPT

POWER-ON RESET

In a normal write sequence, the SYNC line is kept

LOW for at least 24 falling edges of SCLK and the

addressed DAC register is updated on the 24th falling

edge. However, if SYNC is brought HIGH before the

24th falling edge, it acts as an interrupt to the write

sequence; the shift register is reset and the write

sequence is discarded. Neither an update of the data

buffer contents, DAC register contents, nor a change

in the operating mode occurs (see Figure 50).

The DAC8554 contains a power-on reset circuit that

controls the output voltage during power-up. On

power-up, the DAC registers are filled with zeros and

the output voltages are set to zero-scale; they remain

there until a valid write sequence and load command

is made to the respective DAC channel. This is useful

in applications where it is important to know the state

of the output of each DAC while the device is in the

process of powering up. No device pin should be

brought high before power is applied to the device.

DB23

DB12

A1

DB11

D11

A0

LD1

D9

LD0

D8

X

DAC Select 1

D6

DAC Select 0

PD0

D15

D14

D2

D13

D1

D12

DB0

D0

D10

D7

D5

D4

D3

Figure 49. DAC8554 Data Input Register Format

Table 2. Control Matrix

DB23

A1

DB22

A0

DB21

DB20

LD 0

DB19

DB18

DB17

DB16

PD0

DB15

MSB

DB14

DB13-DB0

DESCRIPTION

LD 1

Don't

Care

DAC Sel 1

DAC Sel 0

MSB-1

MSB-2...LSB

(Address Select)

0/1 0/1

See Below

This address selects 1 of 4 possible devices on a

single SPI data bus based on each device's address

pin(s) state.

A0 and A1 should

correspond to the

package address

set via pins 13

and 14.

0

X

0

1

0

1

0

1

0

1

Data

Write to buffer A with data

Write to buffer B with data

Write to buffer C with data

Write to buffer D with data

Data

(00, 01, 10, or 11)

See Table 1

0

Write to buffer (selected by DB17 and DB18) with

power-down command

0

1

0

X

(00, 01, 10, or 11)

0

1

0

Data

Write to buffer with data and load DAC (selected by

DB17 and DB18)

See Table 1

Write to buffer with power-down command and load

DAC (selected by DB17 and DB18)

Write to buffer with data (selected by DB17 and DB18)

and then load all DACs simultaneously from their

corresponding buffers.

1

0

1

X

(00, 01, 10, or 11)

1

0

Write to buffer with power-down command (selected by

DB17 and DB18) and then load all DACs simul-

taneously from their corresponding buffers.

Broadcast Modes

X

0

X

Simultaneously update all channels of all DAC8554

devices in the system with data stored in each chan-

nels temporary register.

X

1

X

1

X

0

1

Data

Write to all devices and load all DACs with SR data

See Table 1

0

Write to all devices and load all DACs with power-down

command in SR.

16

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

24th Falling

Edge

24th Falling

Edge

SCLK

SYNC

1

2

1

2

Invalid Write-Sync Interrupt:

Valid Write-Buffer/DAC Update:

SYNC HIGH Before 24th Falling Edge

SYNC HIGH After 24th Falling Edge

D

DB23 DB22

DB0

DB23 DB22

DB1 DB0

IN

Figure 50. Interrupt and Valid SYNC Timing

Individual channels can separately be powered down,

POWER-DOWN MODES

reducing the total power consumption. When all

channels are powered down, the DAC8554 power

consumption drops below 2 µA. There is no power

-up command. When a channel is updated with data,

it automatically exits power-down. All channels exit

power-down simultaneously after a broadcast data

update. The time to exit power-down is approximately

5 µs. See Table 1 and Table 2 for power-down

operation details.

The DAC8554 utilizes four modes of operation. These

modes are accessed by setting three bits (PD2, PD1,

and PD0) in the shift register and performing a Load

action to the DACs. The DAC8554 offers a very

flexible power-down interface based on channel

register operation. A channel consists of a single

16-bit DAC with power-down circuitry, a temporary

storage register (TR), and a DAC register (DR). TR

and DR are both 18-bit wide. Two MSBs represent

power-down condition and 16 LSBs represent data

for TR and DR. By adding bits 17 and 18 to TR and

DR, a power-down condition can be temporarily

stored and used just like data. Internal circuits ensure

that DB15 and DB14 get transferred to TR17and

TR16 (DR17 and DR16), when DB16 = 1.

Resistor

String DAC

Amplifier

V_OUTX

Power-down

Circuitry

Resistor

Network

The DAC8554 treats the power-down condition like

data and all the operational modes are still valid for

power-down. It is possible to broadcast a power-down

condition to all the DAC8554s in a system, or it is

possible to simultaneously power-down a channel

while updating data on other channels.

Figure 51. Output Stage During Power-Down

(High-Impedance)

DB16, DB15, and DB14 = 100 (or 111) represent a

power-down condition with Hi-Z output impedance for

a selected channel. 101 represents a power-down

condition with 1k output impedance and 110 rep-

resents a power-down condition with 100k output

impedance.

17

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

OPERATION EXAMPLES

Example 1: Write to data buffer A; through buffer D; load DAC A through DAC D simultaneously

•

1st — Write to data buffer A:

A1

0

A0

0

LD1

0

LD0

0

DC

X

DAC Sel 1

0

DAC Sel 0

0

PD0

0

DB15

D15

—

DB1

D1

DB0

D0

2nd — Write to data buffer B:

A1

0

A0

0

LD1

0

LD0

0

DC

X

DAC Sel 1

0

DAC Sel 0

1

PD0

0

DB15

D15

—

DB1

D1

DB0

D0

3rd — Write to data buffer C:

A1

0

A0

0

LD1

0

LD0

0

DC

X

DAC Sel 1

1

DAC Sel 0

0

PD0

0

DB15

D15

—

DB1

D1

DB0

D0

4th — Write to data buffer D and simultaneously update all DACs:

A1

0

A0

0

LD1

1

LD0

0

DC

X

DAC Sel 1

1

DAC Sel 0

1

PD0

0

DB15

D15

—

DB1

D1

DB0

D0

The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon

completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge

of the 4th write cycle).

Example 2: Load New Data to DAC A through DAC D sequentially

•

1st — Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:

A1

0

A0

0

LD1

0

LD0

1

DC

X

DAC Sel 1

0

DAC Sel 0

0

PD0

0

DB15

D15

—

DB1

D1

DB0

D0

2nd — Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:

A1

0

A0

0

LD1

0

LD0

1

DC

X

DAC Sel 1

0

DAC Sel 0

1

PD0

0

DB15

D15

—

DB1

D1

DB0

D0

3rd — Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:

A1

0

A0

0

LD1

0

LD0

1

DC

X

DAC Sel 1

1

DAC Sel 0

0

PD0

0

DB15

D15

—

DB1

D1

DB0

D0

4th — Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:

A1

0

A0

0

LD1

0

LD0

1

DC

X

DAC Sel 1

1

DAC Sel 0

1

PD0

0

DB15

D15

—

DB1

D1

DB0

D0

After completion of each write cycle, DAC analog output settles to the voltage specified.

Example 3: Power-down DAC A and DAC B to 1 kΩ and Power-down DAC C and DAC D to 100 kΩ

simultaneously

•

Write power-down command to data buffer A: DAC A to 1 kΩ.

A1

0

A0

0

LD1

0

LD0

0

DC

X

DAC Sel 1

0

DAC Sel 0

0

PD0

1

DB15

0

DB14

1

DB13

X

—

Write power-down command to data buffer B: DAC B to 1 kΩ.

A1

0

A0

0

LD1

0

LD0

0

DC

X

DAC Sel 1

0

DAC Sel 0

1

PD0

1

DB15

0

DB14

1

DB13

X

—

Write power-down command to data buffer C: DAC C to 1 kΩ.

A1

0

A0

0

LD1

0

LD0

0

DC

X

DAC Sel 1

1

DAC Sel 0

0

PD0

1

DB15

1

DB14

0

DB13

X

—

18

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

•

Write power-down command to data buffer D: DAC D to 100 kΩ and simultaneously update all DACs.

A1

0

A0

0

LD1

1

LD0

0

DC

X

DAC Sel 1

1

DAC Sel 0

1

PD0

1

DB15

1

DB14

0

DB13

X

—

The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified

mode upon completion of the 4th write sequence.

Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially:

•

Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:

A1

0

A0

0

LD1

0

LD0

1

DC

X

DAC Sel 1

0

DAC Sel 0

0

PD0

1

DB15

1

DB14

1

DB13

X

—

Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:

A1

0

A0

0

LD1

0

LD0

1

DC

X

DAC Sel 1

0

DAC Sel 0

1

PD0

1

DB15

1

DB14

1

DB13

x

—

Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:

A1

0

A0

0

LD1

0

LD0

1

DC

X

DAC Sel 1

1

DAC Sel 0

0

PD0

1

DB15

1

DB14

1

DB13

X

—

Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:

A1

0

A0

0

LD1

0

LD0

1

DC

X

DAC Sel 1

1

DAC Sel 0

1

PD0

1

DB15

1

DB14

1

DB13

X

—

The DAC A, DAC B, DAC C, and DAC D analog

outputs sequentially power-down to high-impedance

upon completion of the 1st, 2nd, 3rd, and 4th write

sequences, respectively.

ENABLE PIN

For normal operation, the enable pin must be tied to

a logic low. If the enable pin is tied high, the

DAC8554 stops listening to the serial port. This can

be useful for applications that share the same serial

port.

LDAC FUNCTIONALITY

The DAC8554 offers both a software and hardware

simultaneous update function. The DAC8554

double-buffered architecture has been designed so

that new data can be entered for each DAC without

disturbing the analog outputs. The software simul-

taneous update capability is controlled by the load 1

(LD1) and load 0 (LD0) control bits. By setting load 1

equal to 1 all of the DAC registers will be updated on

the falling edge of the 24th clock signal. When the

new data has been entered into the device, all of the

DAC outputs can be updated simultaneously and

synchronously with the clock.

MICROPROCESSOR INTERFACING

DAC8554 TO 8051 Interface

See Figure 52 for a serial interface between the

DAC8554 and a typical 8051-type micro controller.

The setup for the interface is as follows: TXD of the

8051 drives SCLK of the DAC8554, while RXD drives

the serial data line of the device. The SYNC signal is

derived from a bit-programmable pin on the port of

the 8051. In this case, port line P3.3 is used. When

data is to be transmitted to the DAC8554, P3.3 is

taken LOW. The 8051 transmits data in 8-bit bytes;

thus only eight falling clock edges occur in the

transmit cycle. To load data to the DAC, P3.3 is left

LOW after the first eight bits are transmitted, then a

second and third write cycle is initiated to transmit the

remaining data. P3.3 is taken HIGH following the

completion of the third write cycle. The 8051 outputs

the serial data in a format which presents the LSB

first, while the DAC8554 requires its data with the

MSB as the first bit received. The 8051 transmit

routine must therefore take this into account, and

mirror the data as needed.

DAC8554 data updates are synchronized with the

falling edge of the 24th SCLK cycle, which follows a

falling edge of SYNC. For such synchronous updates,

the LDAC pin is not required and it must be connec-

ted to GND permanently. The LDAC pin is used as a

positive edge triggered timing signal for asynchro-

nous DAC updates. Data buffers of all channels must

be loaded with desired data before LDAC is triggered.

After a low-to-high LDAC transition, all DACs are

simultaneously updated with the contents of their

corresponding data buffers. If the content of a data

buffer is not changed by the serial interface, the

corresponding DAC output will remain unchanged

after the LDAC trigger.

19

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

causes data appearing on the MOSI output to be

valid on the falling edge of SCLK. When data is being

transmitted to the DAC, the SYNC line is held LOW

(PC7). Serial data from the 68HC11 is transmitted in

8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. (Data is transmitted

MSB first.) In order to load data to the DAC8554,

PC7 is left LOW after the first eight bits are trans-

ferred, then a second and third serial write operation

is performed to the DAC. PC7 is taken HIGH at the

end of this procedure.

80C51/80L51⁽¹⁾

P3.3

DAC8554

SYNC

TXD

RXD

SCLK

D_IN

(1) Additional pins omitted for clarity.

Figure 52. DAC8554 to 80C51/80L51 Interface

DAC8554 to Microwire Interface

DAC8554 to TMS320 DSP Interface

Figure 53 shows an interface between the DAC8554

and any Microwire compatible device. Serial data is

shifted out on the falling edge of the serial clock and

is clocked into the DAC8554 on the rising edge of the

CK signal.

Figure 55 shows the connections between the

DAC8554 and a TMS320 Digital Signal Processor

(DSP).

A Single DSP can control up to four

DAC8554s without any interface logic.

DAC8554

AV_DD

Positive Supply

Microwire^TM

DAC8554

SYNC

SCLK

D_IN

CS

SK

SO

0.1

F

10 F

TMS320 DSP

FSX

SYNC

V_OUT

V_REF

A

Output A

Output D

(1) Additional pins omitted for clarity.

DX

D_IN

D

H

Microwire is a registered trademark of National Semiconductor.

CLKX

SCLK

Reference

Input

Figure 53. DAC8554 to Microwire Interface

V_REFL

0.1

F

1 F to 10 F

GND

DAC8554 to 68HC11 Interface

Figure 54 shows a serial interface between the

DAC8554 and the 68HC11 micro controller. SCK of

the 68HC11 drives the SCLK of the DAC8554, while

the MOSI output drives the serial data line of the

DAC. The SYNC signal is derived from a port line

(PC7), similar to the 8051 diagram.

Figure 55. DAC8554 to TMS320 DSP

68HC11⁽¹⁾

DAC8554

PC7

SYNC

SCLK

D_IN

SCK

MOSI

(1) Additional pins omitted for clarity.

Figure 54. DAC8554 to 68HC11 Interface

The 68HC11 should be configured so that its CPOL

bit is 0 and its CPHA bit is 1. This configuration

20

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

APPLICATION INFORMATION

CURRENT CONSUMPTION

OUTPUT VOLTAGE STABILITY

The DAC8554 consumes a maximum of 250 µA at

AV_DD= 5 V and 240 µA at AV_DD= 3 V for each active

channel, including reference current consumption.

Additional current consumption can occur at the

digital inputs if V_IH<< IOV_DD. For most efficient power

operation, CMOS logic levels are recommended at

the digital inputs to the DAC.

The DAC8554 exhibits excellent temperature stability

of 5 ppm/°C typical output voltage drift over the

specified temperature range of the device. This en-

ables the output voltage of each channel to stay

within a ±25 µV window for a ±1°C ambient tempera-

ture change.

Good power-supply rejection ratio (PSRR) perform-

ance reduces supply noise present on AV_DDfrom

appearing at the outputs to well below 10 µV-s.

Combined with good dc noise performance and true

16-bit differential linearity, the DAC8554 becomes a

perfect choice for closed-loop control applications.

In power-down mode, typical current consumption is

200 nA per channel. A delay time of 10 ms to 20 ms

after a power-down command is issued to the DAC is

typically sufficient for the power-down current to drop

below 10 µA.

DRIVING RESISTIVE AND CAPACITIVE

LOADS

SETTLING TIME AND OUTPUT GLITCH PER-

FORMANCE

The DAC8554 output stage is capable of driving

loads of up to 1000 pF while remaining stable. Within

the offset and gain error margins, the DAC8554 can

operate rail-to-rail when driving a capacitive load.

Resistive loads of 2 kΩ can be driven by the

DAC8554 while achieving good load regulation.

When the outputs of the DAC are driven to the

positive rail under resistive loading, the PMOS tran-

sistor of each Class-AB output stage can enter into

the linear region. When this occurs, the added IR

voltage drop deteriorates the linearity performance of

the DAC. This only occurs within approximately the

top 100 mV of the DAC's output voltage character-

istic. Under resistive loading conditions, good linearity

is preserved as long as the output voltage is at least

100 mV below the AVDD voltage.

DAC8554 settles to ±0.003% of its full-scale range

within 10 µs, driving a 200 pF 2 KΩ load. For good

settling performance the outputs should not approach

the top and bottom rails. Small signal settling time is

under 1 µs, enabling data update rates exceeding 1

MSPS for small code changes.

Many applications are sensitive to undesired transient

signals such as glitch. DAC8554 has a proprietary,

ultra-low glitch architecture addressing such appli-

cations. Code-to-code glitches rarely exceed millivolt

and they last under 0.3 µs. Typical glitch energy is an

outstanding 0.15 nV-s. Theoretical worst cast glitch

should occur during a 256 LSB step, but it is so low, it

cannot be detected.

DIFFERENTIAL AND INTERGRAL

NONLINEARITY

CROSSTALK AND AC PERFORMANCE

DAC8554 uses precision thin film resistors to achieve

monotonicity and good linearity. Typical linearity error

is ±4 LSBs; ±0.3 mV error for a 5 V range. Differential

linearity is typically ±0.25 LSBs, ±19 µV error for a

consecutive code change.

The DAC8554 architecture uses separate resistor

strings for each DAC channel in order to achieve

ultra-low crosstalk performance. DC crosstalk seen at

one channel during a full-scale change on the

neighboring channel is typically less than 0.5LSBs.

The AC crosstalk measured (for a full-scale, 1 kHz

sine wave output generated at one channel, and

measured at the remaining output channel) is typi-

cally under –100 dB.

USING THE REF02 AS A POWER SUPPLY

FOR THE DAC8554

Due to the extremely low supply current required by

the DAC8554, a possible configuration is to use a

REF02 +5 V precision voltage reference to supply the

required voltage to the DAC8554s supply input as

well as the reference input, as shown in Figure 56.

This is especially useful if the power supply is quite

noisy or if the system supply voltages are at some

value other than 5 V. The REF02 will output a steady

supply voltage for the DAC8554. If the REF02 is

In addition, the DAC8554 can achieve typical AC

performance of 96 dB signal-to-noise ratio (SNR) and

85 dB total harmonic distortion (THD), making the

DAC8554 a solid choice for applications requiring

high SNR at output frequencies at or below 10 kHz.

21

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

used, the current it needs to supply to the DAC8554

is 0.85 mA typical for AV_DD= 5 V. When a DAC

output is loaded, the REF02 also needs to supply the

current to the load. The total typical current required

(with a 5 kΩ load on a given DAC output) is:

0.85 mA + (5V/5 kΩ) = 1.085 mA

DAC8554

-

Figure 57. Bipolar Operation With the DAC8554

LAYOUT

A precision analog component requires careful layout,

adequate bypassing, and clean, well-regulated power

supplies.

DAC8554

The DAC8554 offers single-supply operation, and it

will often be used in close proximity with digital logic,

micro controllers, microprocessors, and digital signal

processors. The more digital logic present in the

design and the higher the switching speed, the more

difficult it will be to keep digital noise from appearing

at the output.

Figure 56. REF02 as a Power Supply to the

DAC8554

BIPOLAR OPERATION USING THE DAC8554

Due to the single ground pin of the DAC8554, all

return currents, including digital and analog return

currents for the DAC, must flow through a single

point. Ideally, GND would be connected directly to an

analog ground plane. This plane would be separate

from the ground connection for the digital

components until they were connected at the

power-entry point of the system.

The DAC8554 has been designed for single-supply

operation, but a bipolar output range is also possible

using the circuit in Figure 57. The circuit shown will

give an output voltage range of ±V_ref. Rail-to-rail

operation at the amplifier output is achievable using

an amplifier such as the OPA703, as shown in

REFFigure 57.

The power applied to AV_DDshould be well regulated

and low noise. Switching power supplies and DC/DC

converters will often have high-frequency glitches or

spikes riding on the output voltage. In addition, digital

components can create similar high-frequency spikes

as their internal logic switches states. This noise can

easily couple into the DAC output voltage through

various paths between the power connections and

analog output.

The output voltage for any input code can be calcu-

lated as follows:

D

65536

R1 ) R2

R2

R1

_{X +}ƪ_Vref

ƫ

V

* V

OUT

ref

R1

where D represents the input code in decimal

(0–65535).

With V_ref= 5 V, R1 = R2 = 10 kΩ.

10 D

As with the GND connection, AV_DDshould be con-

nected to a positive power-supply plane or trace that

is separate from the connection for digital logic until

they are connected at the power-entry point. In

addition, a 1 µF to 10 µF capacitor in parallel with a

0.1 µF bypass capacitor is strongly recommended. In

some situations, additional bypassing may be re-

quired, such as a 100 µF electrolytic capacitor or

even a Pi filter made up of inductors and capacitors –

all designed to essentially low-pass filter the supply,

removing the high-frequency noise.

_{X *}+ ƪ_{)5 V}

V

OUT

65536

This is an output voltage range of ±5 V with 0000_H

corresponding to a –5 V output and FFFF_Hcorre-

sponding to a 5 V output. Similarly, using V_ref= 2.5 V

a ± 2.5 V output voltage range can be achieved.

22

DAC8554

www.ti.com

SLAS431A–JUNE 2005–REVISED AUGUST 2005

Up to four DAC8554 devices can be used on a single

SPI bus without any glue logic to create a high

channel count solution. Special attention is required

to avoid digital signal integrity problems when using

multiple DAC8554s on the same SPI bus. Signal

integrity of SYNC, SCLK, and D_INlines will not be an

issue as long as the rise times of these digital signals

are longer than six times the propagation delay

between any two DAC8554 devices. Propagation

speed is approximately six inches/ns on standard

PCBs. Therefore, if the digital signal rise time is 1 ns,

the distance between any two DAC8554s have to be

further apart on the PCB, the signal rise times should

be reduced by placing series resistors at the drivers

for SYNC, SCLK, and D_INlines. If the largest distance

between any two DAC8554s must to be six inches,

the rise time should be reduced to 6 ns with an RC

network formed by the series resistor at the digital

driver and the total trace and input capacitance on

the PCB.

23

PACKAGE OPTION ADDENDUM

www.ti.com

13-Sep-2005

PACKAGING INFORMATION

Orderable Device

DAC8554IPW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

16

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

DAC8554IPWG4

DAC8554IPWR

DAC8554IPWRG4

TSSOP

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	DAC8554IPW
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	TSSOP
包装说明：	TSSOP-16
针数：	16
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.08
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	4140
Samacsys Pin Count：	16
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	PW (R-PDSO-G16)
Samacsys Released Date：	2015-04-16 09:48:08
Is Samacsys：	N
最大模拟输出电压：	5.5 V
最小模拟输出电压：
转换器类型：	D/A CONVERTER
输入位码：	BINARY
输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4
长度：	5 mm
最大线性误差 (EL)：	0.0183%
湿度敏感等级：	1
位数：	16
功能数量：	1
端子数量：	16
最高工作温度：	105 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3/5 V
认证状态：	Not Qualified
采样速率：	0.2 MHz
座面最大高度：	1.2 mm
最大稳定时间：	10 µs
标称安定时间 (tstl)：	10 µs
子类别：	Other Converters
最大压摆率：	1.6 mA
标称供电电压：	3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
Base Number Matches：	1

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