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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 集好芯城

     该会员已使用本站13年以上
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     该会员已使用本站17年以上
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     该会员已使用本站13年以上
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量90 
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     该会员已使用本站11年以上
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     该会员已使用本站1年以上
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  • 数量5300 
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  • 全新原装正品,现货库存欢迎咨询
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  • 集好芯城

     该会员已使用本站13年以上
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  • 数量25875 
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     该会员已使用本站16年以上
  • DAC8812ICPW
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     该会员已使用本站16年以上
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  • 数量43976 
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     该会员已使用本站14年以上
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  • 数量25820 
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     该会员已使用本站11年以上
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  • 数量7052 
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     该会员已使用本站12年以上
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  • 数量12245 
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     该会员已使用本站8年以上
  • DAC8812ICPW
  • 数量45000 
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     该会员已使用本站14年以上
  • DAC8812ICPW
  • 数量11530 
  • 厂家Texas Instruments 
  • 封装16-TSSOP 
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     该会员已使用本站5年以上
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     该会员已使用本站11年以上
  • DAC8812ICPW
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • DAC8812ICPW
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • DAC8812ICPWR
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装TSSOP16 
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  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
  • DAC8812ICPW
  • 数量3463 
  • 厂家TI 
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  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • DAC8812ICPW
  • 数量865000 
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  • 封装SOIC 
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  • 一级代理,原装特价现货!
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • DAC8812ICPW
  • 数量6000 
  • 厂家TI 
  • 封装SSOP-16 
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  • 原装假一赔十!可提供正规渠道证明!
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  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
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  • 数量2368 
  • 厂家TI-德州仪器 
  • 封装TSSOP-16 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • DAC8812ICPW
  • 数量16334 
  • 厂家TexasInst 
  • 封装16-TSSOP 
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  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • DAC8812ICPWR
  • 数量2800 
  • 厂家TI/德州仪器 
  • 封装TSSOP16 
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  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • DAC8812ICPW
  • 数量5280 
  • 厂家TI(德州仪器) 
  • 封装TSSOP-16 
  • 批号23+ 
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  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • DAC8812ICPWR
  • 数量55000 
  • 厂家TI(德州仪器) 
  • 封装SSOP-28 
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     该会员已使用本站7年以上
  • DAC8812ICPWR
  • 数量8800 
  • 厂家TI/德州仪器 
  • 封装TSSOP16 
  • 批号新年份 
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     该会员已使用本站15年以上
  • DAC8812ICPWR.
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  • 厂家专营TI/BB 
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  • 批号10+ 
  • 长期收购此型号/专收TI/BB全系列
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  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • DAC8812ICPW
  • 数量38000 
  • 厂家BB 
  • 封装SMD 
  • 批号24+ 
  • 只做原装进口现货假一赔十!公司原装现货!
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     该会员已使用本站15年以上
  • DAC8812ICPW
  • 数量65000 
  • 厂家TI 
  • 封装N/A 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
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  • 深圳市惠诺德电子有限公司

     该会员已使用本站7年以上
  • DAC8812ICPW
  • 数量29500 
  • 厂家Texas Instruments 
  • 封装IC DAC 16BIT A-OUT 16TSSOP 
  • 批号21+ 
  • 只做原装现货代理
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • DAC8812ICPW
  • 数量4845 
  • 厂家TI 
  • 封装TSSOP16 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
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产品型号DAC8812ICPW的概述

DAC8812ICPW概述 DAC8812ICPW是一款高精度、双通道数模转换器(DAC),由德州仪器(Texas Instruments)公司制造。作为一款精密DAC,DAC8812ICPW被广泛应用于工业控制、仪器仪表及医疗设备等多个领域。其输出范围和精度使其适用于诸如数据采集、信号生成及调试等复杂应用。DAC8812采用超薄四方扁平封装,满足现代小型化的设计需求,同时提供高可靠性和广泛的工作温度范围。 详细参数 DAC8812的主要参数包括: - 分辨率:16位 - 输入接口:串行数据输入,兼容SPI及并行输入 - 输出电压范围:0V到VREF (可调整) - 总有效位数(INL/DNL):典型值为±1LSB - 最大转换速率:80kSPS - 供电电压:单电源:+2.7V至+5.5V;双电源:±2.5V至±5.5V - 功耗:典型工作电压下约为300µA - 工作温度范围:-4...

产品型号DAC8812ICPW的Datasheet PDF文件预览

DAC8812  
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
Dual, Serial Input 16-Bit Multiplying Digital-to-Analog Converter  
FEATURES  
DESCRIPTION  
Relative Accuracy: 1 LSB Max  
Differential Nonlinearity: 1 LSB Max  
2-mA Full-Scale Current ±20%,  
with VREF = ±10 V  
0.5 µs Settling Time  
Midscale or Zero-Scale Reset  
Separate 4Q Multiplying Reference Inputs  
Reference Bandwidth: 10 MHz  
Reference Dynamics: –105 dB THD  
SPI™-Compatible 3-Wire Interface:  
50 MHz  
Double Buffered Registers Enable  
Simultaneous Multichannel Change  
Internal Power On Reset  
The DAC8812 is  
digital-to-analog converter (DAC) designed to operate  
from a single +2.7 V to +5.5 V supply.  
a dual, 16-bit, current-output  
The applied external reference input voltage VREF  
determines the full-scale output current. An internal  
feedback resistor (RFB) provides temperature tracking  
for the full-scale output when combined with an  
external I-to-V precision amplifier.  
A
double-buffered, serial data interface offers  
high-speed, 3-wire, SPI and microcontroller  
compatible inputs using serial data in (SDI), clock  
(CLK), and  
a
chip-select (CS).  
A
common  
level-sensitive load DAC strobe (LDAC) input allows  
simultaneous update of all DAC outputs from  
previously loaded input registers. Additionally, an  
internal power-on reset forces the output voltage to  
zero at system turn-on. An MSB pin allows system  
reset assertion (RS) to force all registers to zero code  
when MSB = 0, or to half-scale code when MSB = 1.  
Industry-Standard Pin Configuration  
APPLICATIONS  
Automatic Test Equipment  
Instrumentation  
The DAC8812 is available in an TSSOP-16 package.  
Digitally Controlled Calibration  
V
REF  
A B  
D0  
D1  
D2  
R
A
FB  
D3  
Input  
DAC A  
D4  
I
A
DAC A  
OUT  
Register  
Register  
16  
D5  
R
R
D6  
A
A
GND  
D7  
D8  
D9  
D10  
D11  
D12  
D13  
D14  
D15  
R
B
FB  
Input  
DAC B  
DAC B  
I
B
OUT  
Register  
R
Register  
R
A
B
A0  
GND  
SDI  
A1  
CLK  
EN  
CS  
A
DAC  
Power-On  
Reset  
B
Decode  
DGND  
RS  
MSB  
LDAC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SPI is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005, Texas Instruments Incorporated  
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated  
circuits be handled with appropriate precautions. Failure to observe proper handling and installation  
procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision  
integrated circuits may be more susceptible to damage because very small parametric changes could  
cause the device not to meet its published specifications.  
PACKAGE/ORDERING INFORMATION(1)  
MINIMUM  
RELATIVE  
ACCURACY  
(LSB)  
DIFFERENTIAL  
NONLINEARITY  
(LSB)  
SPECIFIED  
TEMPERATURE  
RANGE  
TRANSPORT  
MEDIA,  
QUANTITY  
PACKAGE-  
LEAD  
PACKAGE  
DESIGNATOR  
ORDERING  
NUMBER  
PRODUCT  
DAC8812ICPW  
DAC8812ICPWR  
DAC8812IBPW  
DAC8812IBPWR  
Tube, 90  
DAC8812C  
±1  
±2  
±1  
±1  
–40°C to +85°C  
–40°C to +85°C  
TSSOP-16  
TSSOP-16  
PW  
PW  
Tape and Reel, 2500  
Tube, 90  
DAC8812B  
Tape and Reel, 2500  
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document, or  
see the TI website at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS(1)  
DAC8812  
– 0.3 to +8  
–18 to +18  
– 0.3 to +8  
– 0.3 to VDD +0.3  
–0.3 to +0.3  
±50  
UNIT  
V
VDD to GND  
VREF to GND  
V
Logic inputs and output to GND  
V(IOUT) to GND  
V
V
AGNDX to DGND  
V
Input current to any pin except supplies  
Package power dissipation  
Thermal resistance, θJA  
Maximum junction temperature (TJmax)  
Operating temperature range  
Storage temperature range  
mA  
W
(TJmax – TA)/θJA  
100  
°C/W  
°C  
°C  
°C  
+150  
– 40 to +85  
– 65 to +150  
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;  
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification  
is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.  
2
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
ELECTRICAL CHARACTERISTICS(1)  
VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless  
otherwise noted.  
DAC8812  
PARAMETER  
STATIC PERFORMANCE(2)  
Resolution  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
16  
±2  
±1  
±1  
10  
20  
±4  
Bits  
LSB  
LSB  
LSB  
nA  
DAC8812B  
DAC8812C  
Relative accuracy  
INL  
DNL  
Differential nonlinearity  
Output leakage current  
DAC8812  
Data = 0000h, TA = +25°C  
Data = 0000h, TA = TA max  
Data = FFFFh  
IOUT  
X
nA  
Full-scale gain error  
Full-scale tempco(3)  
Feedback resistor  
GFSE  
±0.75  
mV  
TCVFS  
1
5
ppm/°C  
kΩ  
RFB  
X
VDD = 5 V  
REFERENCE INPUT  
VREFX range  
VREF  
RREF  
RREF  
CREF  
X
X
X
X
–15  
4
15  
6
V
Input resistance  
5
1
5
kΩ  
%
Input resistance match  
Input capacitance(3)  
ANALOG OUTPUT  
Output current  
Channel-to-channel  
pF  
IOUT  
X
X
Data = FFFFh  
1.6  
2.5  
mA  
pF  
Output capacitance(3)  
COUT  
Code-dependent  
50  
LOGIC INPUTS AND OUTPUT  
VDD = +2.7 V  
VDD = +5 V  
VDD = +2.7 V  
VDD = +5 V  
0.6  
0.8  
V
V
Input low voltage  
Input high voltage  
VIL  
VIH  
2.1  
2.4  
V
V
Input leakage current  
Input capacitance(3)  
Logic output low voltage  
Logic output high voltage  
INTERFACE TIMING(3),(4)  
Clock width high  
IIL  
CIL  
1
10  
µA  
pF  
V
VOL  
VOH  
IOL = 1.6 mA  
0.4  
IOH = 100 µA  
4
V
tCH  
tCL  
25  
25  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock width low  
CS to Clock setup  
Clock to CS hold  
Clock to SDO prop delay  
Load DAC pulsewidth  
Data setup  
tCSS  
tCSH  
tPD  
25  
2
20  
tLDAC  
tDS  
25  
20  
20  
5
Data hold  
tDH  
Load setup  
tLDS  
tLDH  
Load hold  
25  
(1) Specifications subject to change without notice.  
(2) All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter  
amplifier. The DAC8812 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at +25°C.  
(3) These parameters are specified by design and not subject to production testing.  
(4) All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.  
3
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
ELECTRICAL CHARACTERISTICS (continued)  
VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless  
otherwise noted.  
DAC8812  
PARAMETER  
SUPPLY CHARACTERISTICS  
Power supply range  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VDD RANGE  
IDD  
2.7  
5.5  
5
V
µA  
µA  
mW  
%
Logic inputs = 0 V, VDD = +4.5 V to +5.5 V  
Logic inputs = 0 V, VDD = +2.7 V to +3.6 V  
Logic inputs = 0 V  
2
1
Positive supply current  
2.5  
Power dissipation  
PDISS  
PSS  
0.0275  
0.006  
Power supply sensitivity  
AC CHARACTERISTICS(5)  
VDD = ±5%  
To ±0.1% of full-scale,  
Data = 0000h to FFFFh to 0000h  
µs  
0.3  
0.5  
Output voltage settling time  
ts  
To ±0.0015% of full-scale,  
Data = 0000h to FFFFh to 0000h  
µs  
Reference multiplying BW  
DAC glitch impulse  
Feedthrough error  
Crosstalk error  
BW –3 dB VREFX = 100 mVRMS, Data = FFFFh, CFB = 3 pF  
10  
5
MHz  
nV/s  
dB  
Q
VREFX = 10 V, Data = 7FFFh to 8000h to 7FFFh  
Data = 0000h, VREFX = 100 mVRMS, f = 100 kHz  
VOUTX/VREF  
VOUTA/VREF  
X
B
–70  
Data = 0000h, VREFB = 100 mVRMS  
Adjacent channel, f = 100 kHz  
,
dB  
–100  
Digital feedthrough  
Q
THD  
en  
CS = 1 and fCLK = 1 MHz  
1
–105  
12  
nV/s  
dB  
Total harmonic distortion  
Output spot noise voltage  
VREF = 5 VPP, Data = FFFFh, f = 1 kHz  
f = 1 kHz, BW = 1 Hz  
nV/Hz  
(5) All ac characteristic tests are performed in a closed-loop system using an THS4011 I-to-V converter amplifier.  
PARAMETER MEASUREMENT INFORMATION  
SDI  
A1 A0 D15 D14 D13 D12 D11 D10 D9  
D1 D0  
CLK  
Input REG. LD  
t
t
csh  
CSS  
t
ds  
t
dh  
t
ch  
t
cl  
CS  
t
lds  
t
LDAC  
LDH  
t
LDAC  
Figure 1. DAC8812 Timing Diagram  
4
 
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
PIN CONFIGURATION  
DAC8812  
(TOP VIEW)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
RFB  
VREF  
IOUT  
A
A
A
CLK  
LDAC  
MSB  
VDD  
DGND  
CS  
AGND  
AGND  
IOUT  
A
B
B
B
B
11  
10  
9
VREF  
RFB  
RS  
SDI  
PIN DESCRIPTION  
PIN  
NAME  
RFB  
DESCRIPTION  
1
A
Establish voltage output for DAC A by connecting to external amplifier output.  
DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage. Can  
be tied to VDD pin.  
2
VREF  
A
3
4
5
6
IOUT  
A
DAC A Current output.  
DAC A Analog ground.  
DAC B Analog ground.  
DAC B Current output.  
AGND  
A
B
AGND  
IOUT  
B
DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage. Can  
be tied to VDD pin.  
7
VREF  
B
8
9
RFB  
B
Establish voltage output for DAC B by connecting to external amplifier output.  
Serial data input; data loads directly into the shift register.  
SDI  
Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale.  
Register data = 0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for  
DAC8812.  
10  
RS  
Chip-select; active low input. Disables shift register loading when high. Transfers serial  
register data to input register when CS goes high. Does not affect LDAC operation.  
11  
CS  
12  
13  
DGND  
VDD  
Digital ground.  
Positive power-supply input. Specified range of operation 2.7 V to 5.5 V.  
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system  
power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin  
14  
MSB  
can be permanently tied to ground or VDD  
.
Load DAC register strobe; level sensitive active low. Transfers all input register data to the  
DAC registers. Asynchronous active low input. See Table 2 for operation.  
15  
16  
LDAC  
CLK  
Clock input. Positive edge clocks data into shift register.  
5
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
TYPICAL CHARACTERISTICS: VDD = +5 V  
At TA = +25°C, +VDD = +5 V, unless otherwise noted.  
Channel A  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
1.0  
0.8  
T
A
= +25°C  
T
T
T
= +25°C  
A
A
A
0.8  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
0
0
0
8192 16384 24576 32768 40960 49152 57344 65535  
0
0
0
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 2.  
Figure 3.  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
0.8  
1.0  
0.8  
T
A
= -40°C  
= -40°C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
8192 16384 24576 32768 40960 49152 57344 65535  
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 4.  
Figure 5.  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
0.8  
1.0  
0.8  
T
A
= +85°C  
= +85°C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
8192 16384 24576 32768 40960 49152 57344 65535  
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 6.  
Figure 7.  
6
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)  
At TA = +25°C, +VDD = +5 V, unless otherwise noted.  
Channel B  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
1.0  
0.8  
T
T
T
= +25°C  
T
T
T
= +25°C  
A
A
A
A
A
A
0.8  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
0
0
0
8192 16384 24576 32768 40960 49152 57344 65535  
0
0
0
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 8.  
Figure 9.  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
0.8  
1.0  
0.8  
= -40°C  
= -40°C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
8192 16384 24576 32768 40960 49152 57344 65535  
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 10.  
Figure 11.  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
0.8  
1.0  
0.8  
= +85°C  
= +85°C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
8192 16384 24576 32768 40960 49152 57344 65535  
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 12.  
Figure 13.  
7
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)  
At TA = +25°C, +VDD = +5 V, unless otherwise noted.  
SUPPLY CURRENT  
vs LOGIC INPUT VOLTAGE  
REFERENCE MULTIPLYING BANDWIDTH  
180  
6
0
-6  
160  
-12  
-18  
-24  
-30  
-36  
-42  
-48  
-54  
-60  
-66  
-72  
-78  
-84  
-90  
-96  
-102  
-108  
-114  
V
= +5.0V  
DD  
140  
120  
100  
80  
60  
40  
V
= +2.7V  
DD  
20  
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
10  
100  
1k  
10k  
100k  
1M  
10M  
100M  
Logic Input Voltage (V)  
Bandwidth (Hz)  
Figure 14.  
Figure 15.  
DAC GLITCH  
DAC SETTLING TIME  
Voltage Output Settling  
Code: 7FFFh to 8000h  
Trigger Pulse  
LDAC Pulse  
Time (0.2ms/div)  
Time (0.1ms/div)  
Figure 16.  
Figure 17.  
8
 
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
TYPICAL CHARACTERISTICS: VDD = +2.7 V  
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.  
Channel A  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
1.0  
0.8  
T
T
T
= +25°C  
T
T
T
= +25°C  
A
A
A
A
A
A
0.8  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
0
0
0
8192 16384 24576 32768 40960 49152 57344 65535  
0
0
0
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 18.  
Figure 19.  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
0.8  
1.0  
0.8  
= -40°C  
= -40°C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
8192 16384 24576 32768 40960 49152 57344 65535  
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 20.  
Figure 21.  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
0.8  
1.0  
0.8  
= +85°C  
= +85°C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
8192 16384 24576 32768 40960 49152 57344 65535  
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 22.  
Figure 23.  
9
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)  
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.  
Channel B  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
1.0  
0.8  
T
T
T
= +25°C  
T
T
T
= +25°C  
A
A
A
A
A
A
0.8  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
0
0
0
8192 16384 24576 32768 40960 49152 57344 65535  
0
0
0
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 24.  
Figure 25.  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
0.8  
1.0  
0.8  
= -40°C  
= -40°C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
8192 16384 24576 32768 40960 49152 57344 65535  
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 26.  
Figure 27.  
LINEARITY ERROR  
vs DIGITAL INPUT CODE  
DIFFERENTIAL LINEARITY ERROR  
vs DIGITAL INPUT CODE  
1.0  
0.8  
1.0  
0.8  
= +85°C  
= +85°C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
8192 16384 24576 32768 40960 49152 57344 65535  
8192 16384 24576 32768 40960 49152 57344 65535  
Code  
Code  
Figure 28.  
Figure 29.  
10  
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
THEORY OF OPERATION  
CIRCUIT OPERATION  
The DAC8812 contains two 16-bit, current-output, digital-to-analog converters (DACs). Each DAC has its own  
independent multiplying reference input. The DAC8812 uses a 3-wire, SPI-compatible serial data interface, with a  
configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDAC  
strobe enables two channel simultaneous updates for hardware synchronized output voltage changes.  
Digital-to-Analog Converters  
The DAC8812 contains two current-steering R-2R ladder DACs. Figure 30 shows a typical equivalent DAC. Each  
DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin is  
connected to the output of the external amplifier. The IOUTX terminal is connected to the inverting input of the  
external amplifier. The AGNDX pin should be Kelvin-connected to the load point in the circuit requiring the full  
16-bit accuracy.  
V
DD  
R
R
R
V
X
REF  
R
X
FB  
2R  
2R  
2R  
R
5 kW  
S2  
S1  
I
X
OUT  
A
X
GND  
DGND  
Digital interface connections omitted for clarity.  
Switches S1 and S2 are closed, V must be powered.  
DD  
Figure 30. Typical Equivalent DAC Channel  
The DAC is designed to operate with both negative or positive reference voltages. The VDD power pin is only  
used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the  
internal 5 kfeedback resistor. If users are attempting to measure the value of RFB, power must be applied to  
VDD in order to achieve continuity. The DAC output voltage is determined by VREF and the digital data (D)  
according to Equation 1:  
D
65536  
VOUT + *VREF  
 
(1)  
Note that the output polarity is opposite of the VREF polarity for dc reference voltages.  
The DAC is also designed to accommodate ac reference input signals. The DAC8812 accommodates input  
reference voltages in the range of –15 V to +15 V. The reference voltage inputs exhibit a constant nominal input  
resistance of 5 k, ±20%. On the other hand, DAC outputs IOUTA and B are code-dependent and produce  
various output resistances and capacitances.  
The choice of external amplifier should take into account the variation in impedance generated by the DAC8812  
on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,  
dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor  
(CFB) may be needed to provide a critically damped output response for step changes in reference input  
voltages.  
11  
 
 
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
Figure 15 shows the gain vs frequency performance at various attenuation settings using a 3 pF external  
feedback capacitor connected across the IOUTX and RFBX terminals. In order to maintain good analog  
performance, power-supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions,  
clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not  
suitable for this application due to the higher ripple voltage and PSS frequency-dependent characteristics. It is  
best to derive the DAC8812 5-V supply from the system analog supply voltages (do not use the digital 5-V  
supply); see Figure 31.  
15 V  
Analog  
Power  
2R  
Supply  
5 V  
+
R
V
DD  
R
R
R
R
X
FB  
V
X
REF  
2R  
2R  
2R  
R
5 kW  
15 V  
S2  
S1  
I
X
OUT  
V
CC  
V
A1  
OUT  
+
A
X
GND  
V
EE  
Load  
DGND  
DGND  
Digital interface connections omitted for clarity.  
Switches S1 and S2 are closed, V must be powered.  
DD  
Figure 31. Recommended Kelvin-Sensed Hookup  
V
A B  
REF  
CS  
EN  
V
DD  
CLK  
R
B
FB  
SDI  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
16  
DAC A  
Input  
DAC A  
I
A
Register  
OUT  
Register  
R
R
A
A
GND  
R
B
FB  
D10  
D11  
D12  
D13  
D14  
D15  
A0  
DAC B  
Input  
I
B
DAC B  
OUT  
Register  
Register  
R
R
A
B
GND  
DAC  
A
B
Set  
MSB  
Set  
MSB  
Decode  
A1  
Power-  
on  
Reset  
DGND  
MSB  
LDAC  
RS  
Figure 32. System Level Digital Interfacing  
12  
 
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
SERIAL DATA INTERFACE  
The DAC8812 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8812 is  
clocked into the serial input register in an 18-bit data-word format. MSB bits are loaded first. Table 1 defines the  
18 data-word bits for the DAC8812.  
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data  
setup and data hold time requirements specified in the Interface Timing specifications of the Electrical  
Characteristics. Data can only be clocked in while the CS chip select pin is active low. For the DAC8812, only  
the last 18 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state.  
Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the  
DAC8812. Keeping the CS line low between the first, second, and third byte transfers will result in a successful  
serial register update.  
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new  
data to the target DAC register, determined by the decoding of address bits A1 and A0. For the DAC8812,  
Table 1, Table 2, Table 3, and Figure 1 define the characteristics of the software serial interface.  
Table 1. Serial Input Register Data Format, Data Loaded MSB First(1)  
B17  
B0  
Bit  
(MSB)  
B16  
A0  
B15  
D15  
B14  
D14  
B13  
D13  
B12  
D12  
B11  
D11  
B10  
D10  
B9  
D9  
B8  
D8  
B7  
D7  
B6  
D6  
B5  
D5  
B4  
D4  
B3  
D3  
B2  
D2  
B1  
D1  
(LSB)  
Data  
A1  
D0  
(1) Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns to  
logic high. At this point an internally-generated load strobe transfers the serial register data contents (bits D15-D0) to the decoded  
DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8812 shift register are ignored; only the  
last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.  
Table 2. Control Logic Truth Table(1)  
CS  
H
L
CLK  
X
LDAC  
H
RS  
H
H
H
H
H
H
H
H
L
MSB  
X
SERIAL SHIFT REGISTER  
No effect  
INPUT REGISTER  
DAC REGISTER  
Latched  
Latched  
Latched  
Latched  
Latched  
L
H
X
No effect  
Latched  
Latched  
Latched  
L
+  
H
H
X
Shift register data advanced one bit  
L
H
X
No effect  
No effect  
No effect  
No effect  
No effect  
No effect  
No effect  
+  
H
H
H
H
H
L
H
X
Selected DAC updated with current SR contents Latched  
X
L
X
Latched  
Transparent  
X
H
X
Latched  
Latched  
X
+  
H
X
Latched  
Latched  
X
0
Latched data = 0000h  
Latched data = 8000h  
Latched data = 0000h  
Latched data = 8000h  
X
H
L
H
(1) + = Positive logic transition; X = Do not care  
Table 3. Address Decode  
A1  
0
A0  
0
DAC DECODE  
None  
0
1
DAC A  
1
0
DAC B  
1
1
DAC A and DAC B  
13  
 
 
 
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
Figure 33 shows the equivalent logic interface for the key digital control pins for the DAC8812.  
To Input Register  
A
Address  
CS  
Decoder  
B
EN  
Shift Register  
CLK  
SDI  
Figure 33. DAC8812 Equivalent Logic Interface  
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If  
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all  
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).  
POWER ON RESET  
When the VDD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the  
zero-code state or half-scale, depending on the MSB pin voltage. The VDD power supply should have a smooth  
positive ramp without drooping, in order to have consistent results, especially in the region of VDD = 1.5 V to  
2.3 V. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place.  
ESD Protection Circuits  
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and VDD as  
shown in Figure 34.  
V
DD  
250 W  
DIGITAL  
INPUTS  
DGND  
Figure 34. Equivalent ESD Protection Circuits  
PCB LAYOUT  
The DAC8812 is a high-accuracy DAC that can have its performance compromised by grounding and printed  
circuit board (PCB) lead trace resistance. The 16-bit DAC8812 with a 10-V full-scale range has an LSB value of  
153 mV. The ladder and associated reference and analog ground currents for a given channel can be as high as  
2 mA. With this 2-mA current level, a series wiring and connector resistance of only 76 mwill cause 1 LSB of  
voltage drop. The preferred PCB layout for the DAC8812 is to have all AGNDX pins connected directly to an  
analog ground plane at the unit. The noninverting input of each channel I/V converter should also either connect  
directly to the analog ground plane or have an individual sense trace back to the AGNDX pin connection. The  
feedback resistor trace to the I/V converter should also be kept short and have low resistance in order to prevent  
IR drops from contributing to gain error. This attention to wiring ensures the optimal performance of the  
DAC8812.  
14  
 
 
DAC8812  
www.ti.com  
SBAS349AAUGUST 2005REVISED DECEMBER 2005  
APPLICATION INFORMATION  
The DAC8812, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the  
full-scale output IOUT is the inverse of the input reference voltage at VREF  
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing, as shown in Figure 35.  
An additional external op amp (A2) is added as a summing amp. In this circuit, the first and second amps (A1  
and A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented  
by using a 10-V offset of the reference voltage to bias A2. According to the following circuit transfer equation  
(Equation 2), input data (D) from code 0 to full scale produces output voltages of VOUT = –10 V to VOUT = 10 V.  
D
VOUT  
+
* 1   VREF  
32, 768  
(2)  
10 kW  
10 kW  
10 V  
5 kW  
OPA277  
V
OUT  
V
REF  
-10 V < V  
< +10 V  
OUT  
V
DD  
V
X
R
X
FB  
REF  
I
X
OUT  
One Channel  
DAC8812  
OPA277  
A
X
GND  
Digital interface connections omitted for clarity.  
Figure 35. Four-Quadrant Multiplying Application Circuit  
Cross-Reference  
The DAC8812 has an industry-standard pinout. Table 4 provides the cross-reference information.  
Table 4. Cross-Reference  
SPECIFIED  
INL  
(LSB)  
DNL  
(LSB)  
TEMPERATURE  
RANGE  
PACKAGE  
DESCRIPTION  
PACKAGE  
OPTION  
CROSS-REFERENCE  
PRODUCT  
PART NUMBER  
16-Lead Thin Shrink  
Small-Outline Package  
DAC8812ICPW  
±1  
±2  
±1  
±1  
–40°C to +85°C  
–40°C to +85°C  
TSSOP-16  
TSSOP-16  
N/A  
16-Lead Thin Shrink  
Small-Outline Package  
DAC8812IBPW  
AD5545BRU  
15  
 
 
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Feb-2006  
PACKAGING INFORMATION  
Orderable Device  
DAC8812IBPW  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
PW  
16  
16  
16  
16  
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
DAC8812IBPWG4  
DAC8812IBPWR  
DAC8812IBPWRG4  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
DAC8812IBPWT  
DAC8812ICPW  
PREVIEW  
ACTIVE  
TSSOP  
TSSOP  
PW  
PW  
16  
16  
250  
TBD  
Call TI  
Call TI  
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
DAC8812ICPWG4  
DAC8812ICPWR  
DAC8812ICPWRG4  
DAC8812ICPWT  
ACTIVE  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
PW  
16  
16  
16  
16  
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ACTIVE  
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
PREVIEW  
250  
TBD  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
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and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
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Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
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Post Office Box 655303 Dallas, Texas 75265  
Copyright 2006, Texas Instruments Incorporated  
配单直通车
DAC8812ICPW产品参数
型号:DAC8812ICPW
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:TSSOP
包装说明:TSSOP-16
针数:16
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:6 weeks
风险等级:1.69
Samacsys Confidence:
Samacsys Status:Released
Samacsys PartID:414178
Samacsys Pin Count:16
Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Other
Samacsys Footprint Name:SOP65P640X120-16N
Samacsys Released Date:2017-01-12 12:59:53
Is Samacsys:N
转换器类型:D/A CONVERTER
输入位码:BINARY
输入格式:SERIAL
JESD-30 代码:R-PDSO-G16
JESD-609代码:e4
长度:5 mm
最大线性误差 (EL):0.0015%
湿度敏感等级:2
位数:16
功能数量:1
端子数量:16
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:3/5 V
认证状态:Not Qualified
采样速率:2 MHz
座面最大高度:1.2 mm
最大稳定时间:0.5 µs
标称安定时间 (tstl):0.5 µs
子类别:Other Converters
最大压摆率:0.005 mA
标称供电电压:5 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm
Base Number Matches:1
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