DPL12VN24A20FB全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

PRELIMINARY DATA SHEET

DPL 3520A,

MICRONAS

DPL 3519A,

DPL 3518A

Dolby Pro Logic

Processor Family

Edition July 31, 1997

6251-423-1PD

MICRONAS

DPL 35xxA

PRELIMINARY DATA SHEET

Contents

Page

4

Section

1.

Title

Introduction

6

7

2.

Functional Description

2.1.

2.2.

2.3.

2.4.

Features of the Analog Input Section

Features of the DSP-Section

Features of the Analog Output Section

SCART Switches

8

3.

Specifications

8

3.1.

Outline Dimensions

9

3.2.

Pin Connections and Short Descriptions

Pin Configurations

12

15

17

18

21

26

3.3.

3.4.

Pin Circuits

3.5.

Electrical Characteristics

Absolute Maximum Ratings

Recommended Operating Conditions

Characteristics

3.5.1.

3.5.2.

3.5.3.

3.5.4.

Measurements according to Dolby specifications, typical values

2

27

28

4.

I C-Bus Interface

4.1.

Protocol Description

2

4.2.

Proposal for DPL I C-Telegrams

4.2.1.

4.2.2.

4.2.3.

4.2.4.

4.3.

Symbols

Write Telegrams

Read Telegrams

Examples

Start-Up Sequence

29

5.

Audio PLL and Crystal Specifications

Operation with Crystal

5.1.

5.2.

Operation without Crystal

2

29

6.

I S-Bus Interface

2

30

6.1.

I S Bus Timing Diagram

31

32

7.

8.

Power-up Sequence

Programming the Mode Register

33

35

36

37

38

39

40

9.

Programming the DSP Part

Summary of the DSP Control Registers

Volume Channel 1 and Channel 2

Balance Channel 1 and Channel 2

Bass Channel 1 and Channel 2

Treble Channel 1 and Channel 2

Loudness Channel 1 and Channel 2

Spatial Effects Channel 1

9.1.

9.1.1.

9.1.2.

9.1.3.

9.1.4.

9.1.5.

9.1.6.

9.1.7.

9.1.8.

9.1.9.

9.1.10.

Volume SCART Channel

Channel Source Modes

Channel Matrix Modes

SCART Prescale

2

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Contents, continued

Page

Section

Title

2

40

41

42

43

44

45

9.1.11.

9.1.12.

9.1.13.

9.1.14.

9.1.15.

9.1.16.

9.1.17.

9.1.18.

9.1.19.

9.1.20.

9.1.21.

9.1.22.

9.1.23.

9.1.24.

9.1.25.

9.2.

I S1 and I S2 Prescale

ACB Register, Definition of the SCART-Switches and DIG_CTR_OUT Pins

Beeper

Mode Tone Control

Equalizer Channel 1

Surround Decoder Modes

Surround Reproduction Modes

Surround Source Modes

Surround Source Matrix Modes

Surround Delay

Surround Manual Input Balance

Surround Input Balance Mode

Surround Spatial Effect

Panorama Sound Effect

Surround Reverberation

Summary of Readable Registers

Quasi Peak Detector

9.2.1.

9.2.2.

Digital Input Level Register

46

47

48

49

50

10.

Further Explanations and Application Hints

Overview of the Surround Decoder and Reproduction Modes

Useful Combinations of the Surround Decoder and Reproduction Modes

Useful Combinations with the ADAPTIVE Surround Decoder Mode

Useful Combinations with the PASSIVE Surround Decoder Mode

Useful Combinations with the EFFECT Surround Decoder Mode

Further Notes

10.1.

10.2.

10.2.1.

10.2.2.

10.2.3.

10.3.

10.4.

10.5.

10.6.

10.7.

Input and Output Levels for Dolby Pro Logic Operation

Dolby Qualification

Phase Relationship of Outputs

Minimum Control Transmissions for DPL 3520A

51

52

11.

12.

Application Principle of the DPL 3520A

Application Circuit Diagram of the DPL 3520A

53

54

13.

Dolby Pro Logic Processor Family

13.1.

13.2.

DPL 3518A: Basic Dolby Pro Logic Coprocessor for the MSP Family

DPL 3519A: Advanced Dolby Pro Logic Coprocessor for the MSP Family

56

14.

15.

IC Failure Report

Data Sheet History

)

DPL 3520A Dolby* Pro Logic Processor

Note: This document contains information on a new product.

Specifications and information herein are subject to change without notice.

)

* “Dolby”, the double-D symbol and “Pro Logic” are trademarks of Dolby Laboratories Licensing Corporation.

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Dolby Pro Logic Processor Family

1. Introduction

The DPL 35xxA processor family is designed to decode

Dolby encoded surround sound. The ICs integrate the

complete Dolby Surround Pro Logic decoding on chip

without any necessary external circuitry. This data sheet

describesthefeaturesandspecificationsofallmembers

of the IC family.

The DPL 3518A is designed as a coprocessor to one of

the TV sound processing ICs of the MSP 34xx family. It

onlyhasdigitalinterfaces. Noanaloginputandoutputin-

terfaces are supported.

TheDPL3519Aisalsodesignedasacoprocessortothe

MSP family but has analog output channels in addition

tothefeaturesoftheDPL3518A. TogetherwiththeMSP,

a TV set with up to six outputs (L, R, C, SUB, S , S ) can

L

R

be developed together with headphones and several

line outputs.

TheDPL3520Aisdesignedasastand-aloneDolbySur-

round Pro Logic decoder. An on-chip A/D converter digi-

tizes analog inputs. The DPL 3520A can also be used as

a coprocessor to the MSP 34xx single-chip Multistan-

dard Sound Processor family. This gives another A/D in-

put pair to the system.

The ICs of the DPL family are pin-compatible to the MSP

ICs. This speeds up PCB development for customers

using MSPs.

The software interface is largely the same as for the

MSP 3400C. Volume, tone controls, matrixes and

switches use the same registers and values. Thus, the

standard MSP 3400C controlling software can be used

to control the DPL 3520A. Little overhead is needed to

control the Dolby Pro Logic part of the IC.

4

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DPL 3518A Integrated Functions:

– Full Dolby Surround Pro Logic Adaptive Matrix

– Pseudo-surround mode for signals not encoded in Dolby Surround

– PANORAMA sound mode (3-D Surround sound via 2 loudspeakers)

– Noise sequencer

– Automatic input balance control

– 7 kHz low-pass filter

– 100 Hz low-pass filter for subwoofer

– Modified Dolby B-type NR decoder

– 30 ms surround delay according to table created by Dolby Laboratories (1 ms steps)

2

– 2 I S input channels (e.g. MSP and DRPA)

2

– 2 I S output channels, freely programmable with sound channels L/R (resp. L)C/R)C), C/S, Sub or I S input

– Mode control: normal/phantom/wide/three channel/center off/panorama sound/stereo bypass

– Surround matrix mode control: adaptive/passive/effect

– Additional surround basewidth effect

– Reverberation of surround signals

– 2 digital input/output pins

– 1 digital input pin

DPL 3519A Integrated Functions (in Addition to all DPL 3518A Functions):

– Master volume control in dB units

– Level Trim for L, C, R, S in dB units, $12 dB

– Identical treble/bass/loudness function for L, C, R, S

– 5-band equalizer for C channel

– Separate volume control for two surround outputs

– Additional line output for HIFI receiver connection (SCART output). Volume for this output is in dB units.

– 3 pairs of D/A converters

– Scart switches

DPL 3520A Integrated Functions (in Addition to all DPL 3518A and DPL 3519A Functions)

– 1 pair of A/D converters

– Note: the 5-band equalizer for C channel can only be used in coprocessor mode. No parallel AD input possible.

DPL 3520/19/18A Applications:

Dolby Pro Logic Surround System

in television sets

in satellite receivers

in video recorders

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2. Functional Description

Power Consumption:

– typical: 450 mW at 5V

– typical: 120 mW at 8V

In the following, the functional description of the

DPL 3520A is given. See section 13 for the modified

block diagrams of the DPL 3518A and DPL 3519A.

2.1. Features of the Analog Input Section

Block diagram: DPL 3520A consists of three blocks:

– three selectable analog pairs of audio baseband

inputs (+ three SCART inputs)

Input level: v2V RMS;

– analog input section containing channel selection and

2 high-quality A/D converters

input impedance: w25 kΩ

– DSP section performing audio baseband

processing

– one selectable analog mono input;

Input level: v2V RMS;

input impedance: w10 kΩ

– analogoutputsectioncontaining6D/Aconverterswith

4-fold oversampling

– 20 Hz to 20 kHz Bandwidth for SCART-to-SCART-

copy facilities

Control-bus:

– two high-quality A/D converters

2

– The IC is controlled by I C-bus. The I C-bus device

addresses are 80 /81 84 /85 and

,

hex

2.2. Features of the DSP-Section

88 /89

.

hex

– flexible selection of audio sources to be processed

2

– 4-channel digital input via I S-Bus and 4-channel digi-

tal output via I S-Bus.

Clock System:

2

– Single crystal clock system

(18.432 MHz), alternatively external clock.

– digital baseband processing: volume, bass, treble,

loudness on output channels 1 and 2.

– Dolby Pro Logic processing

– 100 Hz low-pass for subwoofer

– 30 ms delay line

Packages:

– 68-pin PLCC package

– 64-pin Shrink DIP package

– 52-pin Shrink DIP package

A block diagram of the DSP software is shown in

Fig. 2–2.

I2S_CL

I2S_DA_OUT1 I2S_DA_OUT2

I2S_WS

I2S_DA_IN1

I2S_DA_IN2

2

I S Interface

2

I S1/2L/R

OUT1_L

OUT1_R

OUT1_L

OUT1_R

D/A

Channel 1

Output

Mono

MONO_IN

D/A

DSP

D/A

OUT2_L

OUT2_R

OUT2_L

OUT2_R

SC1_IN_L

SC1_IN_R

Channel 2

Output

SCART1

A/D

D/A

SCART_L

SCART_R

SCART_L

SCART_R

SC1_OUT_L

SC1_OUT_R

SC2_IN_L

SC2_IN_R

SCART 1

SCART 2

SCART2

SCART3

SC2_OUT_L

SC2_OUT_R

SC3_IN_L

SC3_IN_R

SCART Switching Facilities

Fig. 2–1: Block diagram of the DPL 3520A

6

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Equalizer or

Bass/Treble

Loudness

Volume

Balance

Spatial Effects

OUT1L

Channel1

Matrix

Channel 1

Output

Prescale

Bass,Treble

Loudness

SCARTL

SCARTR

OUT1R

Spatial Effects

Beeper

Analog

Inputs

OUT2L

Volume

Balance

Bass,Treble

Loudness

Channel 2

Output

Channel2

Matrix

OUT2R

2

Prescale

I S1L

SCARTL

Volume

SCART

Channel

Matrix

SCART

Output

2

I S1R

2

I S Bus

SCARTR

Inputs

2

I S2L

2

I S1L

2

I S1

2

I S2R

I S1

Channel

Matrix

Output

2

I S1R

2

I S2L

2

L/L+C/PSL

I S2

2

I S2

Channel

Matrix

R/R)C/PSR

Output

2

I S2R

Dolby

Pro Logic

or

Passive

or

Surround

Source

Matrix

C

S

Effect

Quasi peak readout L

Quasi peak readout R

Quasi-Peak

Channel

Matrix

Quasi-Peak

Detector

Noise

Generator

C

SUB

2

I S1L

Internal signal lines

Fig. 2–2: Firmware block diagram

SCART_IN

ACB[1:0]

2.3. Features of the Analog Output Section

SC1_IN_L/R

MONO

2

00

01

to Audio Baseband

Processing (DFP)

– channel 1 and 2: two pairs of 4-fold oversampled D/A-

converters

A

D

2

SC2_IN_L/R

Output level per channel: max. 1.4 V

RMS

SCARTL/R

10

11

Output resistance: max. 5 kΩ

S/N-Ratio: w85 dB at maximum volume; max. noise

voltage in mute mode: v3 µV (BW: 20 Hz...16 kHz)

SC3_IN_L/R

S1

ACB[3:2]

– one pair of four-fold oversampled D/A-converters sup-

plying two selectable pairs of SCART-Outputs.

2

00

01

SCART_OUT

Output level per channel: max. 2 V

RMS

2

from Audio Baseband

Processing (DFP)

SC1_OUT_L/R

Output resistance: max. 0.5 kΩ

S/N-Ratio: w85 dB (20 Hz ... 16 kHz)

10

D

SCARTL/R

2

A

11

S2

ACB[5:4]

2.4. SCART Switches

00

01

2

The analog input and output sections offer a wide range

of switching facilities, which are shown in Fig. 2–3.

2

SC2_OUT_L/R

S3

10

The switches are controlled by the ACB bits defined in

the audio processing interface (see section 9. Program-

ming the DSP Part).

Fig. 2–3: SCART-Switching Facilities

Bold lines determine the default configuration

If the DPL is switched off by first pulling STANDBYQlow,

and then disconnecting the 5 V, but keeping the 8 V pow-

er supply (‘Standby’-mode), the switches S1, S2, and

S3 maintain their position and function. This facilitates

the copying from selected SCART-inputs to SCART-out-

puts in the TV-sets standby mode.

In case of power-on start or starting from standby, the IC

switches automatically to the default configuration,

shown in Fig. 2–3. This takes place after the first I C

transmission into the DFP part. By transmitting the ACB

register first, the default setting mode can be changed.

2

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3. Specifications

3.1. Outline Dimensions

2.4

±0.1

16 x 1.27

= 20.32

+0.2

1

x 45 °

±0.1

1.27

1.2 x 45°

9

1

61

10

60

2

9

15

9

26

44

1.9 1.5

4.05

27

43

+0.25

0.1

±0.1

24.2

25

±0.15

4.75

Fig. 3–1:

SPGS7004-3/4E

68-Pin Plastic Leaded Chip Carrier Package

(PLCC68)

Weight approximately 4.8 g

Dimensions in mm

SPGS0016-4/2E

SPGS0015-1/2E

64

1

33

32

52

27

26

1

±0.1

19.3

±0.1

15.6

±0.1

18

57.7

±0.1

14

47

±0.06

0.27

±0.06

0.27

0°...15°

±0.6

±0.1

20.1

1

±0.1

1

0.457

±0.05

1.778

31 x 1.778 = 55.118

±0.05

1.778

±0.1

1.29

25 x 1.778 = 44.47

Fig. 3–2:

Fig. 3–3:

64-Pin Plastic Shrink Dual-Inline-Package

(PSDIP64)

Weight approximately 9.0 g

Dimensions in mm

52-Pin Plastic Shrink Dual-Inline-Package

(PSDIP52)

Weight approximately 5.5 g

Dimensions in mm

8

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3.2. Pin Connections and Short Descriptions

X = obligatory; connect as described in circuit diagram

AHVSS: connect to AHVSS

NC = not connected; leave vacant

LV = if not used, leave vacant

20/19: pin description valid for DPL 3520A and

DPL 3519A

DVSS: if not used, connect to DVSS

18: pin description valid for DPL 3518A

Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

1

16

–

14

–

NC

LV

X

Not connected

2

NC

3

15

14

13

12

11

10

9

13

12

11

10

9

NC

2

4

I2S_DA_IN1

I2S_DA_OUT1

I2S_WS

I2S_CL

I2C_DA

I2C_CL

NC

IN

I S1 data input

2

5

OUT

IN/OUT

IN

I S1 data output

2

6

I S wordstrobe

2

7

I S clock

2

8

I C data

2

9

7

X

I C clock

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

8

–

IN

X

Not connected

7

6

STANDBYQ

ADR_SEL

D_CTR_IO0

D_CTR_IO1

NC

IN

X

Standby (low-active)

2

6

5

IN

X

I C-Bus address select

5

4

IN/OUT

LV

X

Digital control IO 0

Digital control IO 1

Not connected

Audio clock output

Digital control input

Crystal oscillator

Test pin

4

3

–

2

–

NC

–

NC

1

2

AUD_CL_OUT

D_CTR_IN

XTAL_OUT

XTAL_IN

TESTEN

NC

OUT

IN

64

63

62

61

60

59

58

57

56

55

1

52

51

50

49

48

47

46

45

44

OUT

IN

X

IN

X

LV

X

Not connected

Analog power supply +5 V

Analog ground

Mono input

NC

AVSUP

AVSS

X

20/19: MONO_IN

18: NC

IN

LV

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PRELIMINARY DATA SHEET

Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

29

30

54

53

43

42

VREFTOP

X

Reference voltage

20/19: SC1_IN_R

18: NC

IN

LV

Scart input 1 in, right

31

32

33

34

35

36

37

38

52

51

50

49

48

47

46

–

41

–

20/19: SC1_IN_L

18: NC

LV

Scart input 1 in, left

20/19: ASG1

18: NC

AHVSS

LV

Analog Shield Ground 1

Scart input 2 in, right

Scart input 2 in, left

40

39

–

20/19: SC2_IN_R

18: NC

IN

20/19: SC2_IN_L

18: NC

LV

20/19: ASG2

18: NC

AHVSS

LV

Analog Shield Ground 2

Scart input 3 in, right

Scart input 3 in, left

38

37

–

20/19: SC3_IN_R

18: NC

IN

20/19: SC3_IN_L

18: NC

LV

20/19: ASG4

18: NC

AHVSS

Analog Shield Ground 4

39

40

41

42

45

44

43

42

–

NC

LV

X

Not connected

–

36

20/19: AGNDC

18: NC

Analog reference voltage

high voltage part

43

44

45

46

47

48

49

50

41

40

39

38

37

36

35

34

35

34

33

32

31

30

29

28

20/19: AHVSS

18: NC

X

Analog ground

20/19: CAPL_C1

18: NC

X

Volume capacitor

Channel1

20/19: AHVSUP

18: NC

X

Analog power supply 8.0 V

20/19: CAPL_C2

18: NC

X

Volume capacitor

Channel 2

20/19: SC1_OUT_L

18: NC

OUT

LV

X

Scart output 1, left

20/19: SC1_OUT_R

18: NC

Scart output 1, right

20/19:VREF1

18: NC

Reference ground 1 high

voltage part

20/19: SC2_OUT_L

18: NC

OUT

LV

Scart output 2, left

10

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Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

51

33

27

20/19: SC2_OUT_R

18: NC

OUT

LV

Scart output 2, right

–

32

31

30

–

NC

LV

Not connected

–

LV

Not connected

52

20/19: ASG3

18: NC

AHVSS

Analog Shield Ground 3

53

54

55

56

–

NC

LV

Not connected

–

29

25

20/19: DACC1_L

18: NC

OUT

Analog output

Channel 1, left

57

58

59

60

28

27

26

25

24

23

22

21

20/19: DACC1_R

18: NC

LV

X

Analog output

Channel 1, right

20/19:VREF2

18: NC

Reference ground 2 high

voltage part

20/19: DACC2_L

18: NC

OUT

IN

LV

Analog output

Channel 2, left

20/19: DACC2_R

18: NC

Analog output

Channel 2, right

61

62

63

64

65

66

67

68

24

23

22

21

20

19

18

17

20

–

RESETQ

NC

X

Power-on-reset

Not connected

LV

X

–

NC

2

19

18

17

16

15

I2S_DA_OUT2

I2S_DA_IN2

DVSS

OUT

IN

I S2-data output

2

I S2-data input

Digital ground

DVSUP

NC

X

Digital power supply +5 V

Not connected

LV

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3.3. Pin Configurations

NC

DVSUP

DVSS

I2S_DA_IN2

I2S_DA_OUT2

NC

I2S_DA_IN1

I2S_DA_OUT1

I2S_WS

I2S_CL

I2C_DA

I2C_CL

NC

RESETQ

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

DACC2_R

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

STANDBYQ

DACC2_L

ADR_SEL

D_CTR_IO0

D_CTR_IO1

NC

VREF2

DACC1_R

DACC1_L

NC

AUD_CL_OUT

ASG3

DPL 3520A

DPL 3519A

D_CTR_IN

XTAL_OUT

SC2_OUT_R

SC2_OUT_L

VREF1

XTAL_IN

TESTEN

SC1_OUT_R

SC1_OUT_L

NC

CAPL_C2

AHVSUP

CAPL_C1

NC

AVSUP

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

AVSS

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

ASG1

SC2_IN_R

SC2_IN_L

AHVSS

AGNDC

NC

ASG4

SC3_IN_L

SC3_IN_R

ASG2

Fig. 3–4: 68-pin PLCC package of the DPL 3519A and DPL 3520A

12

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NC

DVSUP

DVSS

I2S_DA_IN2

I2S_DA_OUT2

NC

I2S_DA_IN1

I2S_DA_OUT1

I2S_WS

I2S_CL

I2C_DA

NC

I2C_CL

RESETQ

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

NC

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

STANDBYQ

ADR_SEL

D_CTR_IO0

D_CTR_IO1

NC

AUD_CL_OUT

DPL 3518A

D_CTR_IN

XTAL_OUT

NC

XTAL_IN

TESTEN

NC

AVSUP

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

AVSS

NC

VREFTOP

NC

Fig. 3–5: 68-pin PLCC package of the DPL 3518A

Micronas

13

DPL 35xxA

PRELIMINARY DATA SHEET

1

AUD_CL_OUT

NC

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

D_CTR_IN

XTAL_OUT

XTAL_IN

TESTEN

NC

AUD_CL_OUT

NC

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

D_CTR_IN

XTAL_OUT

XTAL_IN

TESTEN

NC

2

3

NC

D_CTR_IO1

D_CTR_IO0

ADR_SEL

STANDBYQ

NC

4

D_CTR_IO1

D_CTR_IO0

ADR_SEL

STANDBYQ

NC

4

5

6

NC

6

NC

7

NC

7

NC

AVSUP

AVSS

AVSUP

AVSS

NC

8

I2C_CL

9

I2C_CL

9

I2C_DA

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

ASG1

I2C_DA

10

11

12

13

14

15

16

10

11

12

13

14

15

16

I2S_CL

VREFTOP

NC

I2S_WS

I2S_DA_OUT1

I2S_DA_IN1

I2S_DA_OUT1

I2S_DA_IN1

NC

SC2_IN_R

SC2_IN_L

ASG2

NC

48

47

46

45

48

47

46

45

NC

17

18

19

20

NC

17

18

19

20

DVSUP

DVSS

SC3_IN_R

SC3_IN_L

NC

DVSUP

DVSS

I2S_DA_IN2

44

43

42

41

40

39

38

37

36

35

34

33

NC

44

43

42

41

40

39

38

37

36

35

34

33

21

22

23

24

25

26

27

28

29

30

31

32

21

22

23

24

25

26

27

28

29

30

31

32

I2S_DA_OUT2

NC

I2S_DA_OUT2

NC

AGNDC

AHVSS

NC

RESETQ

CAPL_C1

NC

DACC2_R

DACC2_L

VREF2

NC

AHVSUP

CAPL_C2

SC1_OUT_L

SC1_OUT_R

VREF1

DACC1_R

DACC1_L

ASG3

SC2_OUT_L

SC2_OUT_R

NC

Fig. 3–6: 64-pin PSDIP package of the DPL 3519A

Fig. 3–7: 64-pin PSDIP package of the DPL 3518A

and DPL 3520A

14

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

D_CTR_IN

AUD_CL_OUT

D_CTR_IO0

D_CTR_IO1

ADR_SEL

1

D_CTR_IN

AUD_CL_OUT

D_CTR_IO0

D_CTR_IO1

ADR_SEL

1

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

XTAL_OUT

XTAL_IN

TESTEN

NC

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

XTAL_OUT

2

XTAL_IN

TESTEN

NC

3

4

5

NC

5

NC

STANDBYQ

I2C_CL

NC

STANDBYQ

I2C_CL

NC

6

7

AVSUP

AVSS

7

AVSUP

AVSS

NC

I2C_DA

8

I2S_CL

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

9

I2S_WS

VREFTOP

NC

10

11

12

13

14

15

16

10

11

12

13

14

15

16

I2S_DA_OUT1

I2S_DA_IN1

I2S_DA_OUT1

I2S_DA_IN1

NC

SC2_IN_R

SC2_IN_L

SC3_IN_R

SC3_IN_L

AGNDC

NC

DVSUP

DVSS

36

35

34

33

DVSS

36

35

34

33

17

18

19

20

17

18

19

20

I2S_DA_IN2

I2S_DA_OUT2

AHVSS

I2S_DA_IN2

I2S_DA_OUT2

CAPL_C1

AHVSUP

RESETQ

DACC2_R

DACC2_L

VREF2

RESETQ

NC

CAPL_C2

SC1_OUT_L

SC1_OUT_R

VREF1

32

31

30

29

28

27

32

31

30

29

28

27

21

22

23

24

25

26

21

22

23

24

25

26

NC

DACC1_R

DACC1_L

NC

SC2_OUT_L

SC2_OUT_R

NC

Fig. 3–8: 52-pin PSDIP package of the

Fig. 3–9: 52-pin PSDIP package of the

DPL 3519A and DPL 3520A

DPL 3518A

3.4. Pin Circuits (pin numbers refer to PLCC68 package)

DV

SUP

P

N

Fig. 3–12: Input Pins 4, 11, 12, 19, 61, 62, and 65

(I S_DA_IN1/2, STANDBYQ, ADR_SEL, D_CTR_IN,

2

RESETQ, TESTEN)

GND

Fig. 3–10: Output Pins 5 and 64

2

(I S_DA_OUT1/2)

DV

SUP

P

N

GND

Fig. 3–13: Input/Output Pins 6, 7, 13, and 14

(I S_WS, I S_CL, D_CTR_IO0/1)

Fig. 3–11: Input/Output Pins 8 and 9

(I C_DA, I C_CL)

2

Micronas

15

DPL 35xxA

PRELIMINARY DATA SHEET

40 K

P

N

≈ 3.75 V

Fig. 3–18: Input Pins 30, 31, 33, 34, 36, and 37

(SC1–3_IN_L/R)

500 k

3–30 pF

2.5 V

AHV

SUP

0...1.2 mA

Fig. 3–14: Output/Input Pins 18, 20, and 21

(AUD_CL_OUT, XTALIN/OUT)

3.3 K

Fig. 3–19: Output Pins 56, 57, 59, and 60

(DACC1_L/R, DACC2_L/R)

VREFTOP

Fig. 3–15: Pin 29 (VREFTOP)

125 K

≈ 3.75 V

Fig. 3–20: Pin 42 (AGNDC)

16 K

≈ 3.75 V

40 pF

80 K

Fig. 3–16: Input Pin 28 (MONO_IN)

300

≈ 3.75 V

0...2 V

Fig. 3–17: Capacitor Pins 44 and 46

Fig. 3–21: Output Pins 47, 48, 50 and 51

(CAPL_C1, CAPL_C2)

(SC_1/2_OUT_L/R)

16

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

3.5. Electrical Characteristics

3.5.1. Absolute Maximum Ratings

Symbol

Parameter

Pin Name

–

Min.

0

Max.

Unit

°C

V

T

A

Ambient Operating Temperature

Storage Temperature

First Supply Voltage

Second Supply Voltage

Third Supply Voltage

70

T

–

–40

–0.3

–0.5

125

9.0

6.0

0.5

S

V

SUP1

V

SUP2

V

SUP3

AHVSUP

DVSUP

AVSUP

V

dV

Voltage between AVSUP

and DVSUP

AVSUP,

DVSUP

V

SUP23

P

V

Chip Power Dissipation

PLCC68 without Heat Spreader

AHVSUP,

DVSUP, AVSUP

TOT

1100

mW

V

Input Voltage, all Digital Inputs

Input Current, all Digital Pins

Input Voltage, all Analog Inputs

–0.3

–20

V

SUP2

+0.3

Idig

1)

I

–

+20

mA

Idig

2)

V

Iana

SCn_IN_s,

–0.3

V

SUP1

V

MONO_IN

2)

1)

I

Input Current, all Analog Inputs

SCn_IN_s,

–5

+5

mA

Iana

MONO_IN

2)

3) 4)

I

Output Current, all SCART Outputs

SCn_OUT_s

,

Oana

2)

3)

Output Current, all Analog Outputs

except SCART Outputs

DACp_s

Oana

2)

I

Output Current, other pins

connected to capacitors

CAPL_p,

Cana

AGNDC

1)

2)

3)

4)

positive value means current flowing into the circuit

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “C1” or “C2”

The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground.

Total chip power dissipation must not exceed absolute maximum rating.

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the

“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi-

mum ratings conditions for extended periods may affect device reliability.

Micronas

17

DPL 35xxA

PRELIMINARY DATA SHEET

3.5.2. Recommended Operating Conditions

at T = 0 to 70 °C

A

Symbol

Parameter

Min.

Typ.

8.0

Max.

Unit

Pin Name

AHVSUP

DVSUP

V

SUP1

V

SUP2

V

SUP3

First Supply Voltage

Second Supply Voltage

Third Supply Voltage

7.6

8.4

V

4.75

5.0

5.25

AVSUP

V

RESET Input Low Voltage

RESET Input High Voltage

RESETQ

0.45

0.25

V

REIL

REIH

REIL

SUP2

0.8

5

SUP2

t

RESET Low Time after DVSUP

Stable and Oscillator Startup

µs

V

Digital Input Low Voltage

STANDBYQ,

ADR_SEL,

TESTEN,

D_CTR_IN,

D_CTR_IO_0/1

V

DIGIL

DIGIH

SUP2

V

Digital Input High Voltage

0.75

1

V

t

STANDBYQ Setup Time before

Turn-off of Second Supply Voltage

STANDBYQ,

DVSUP

µs

STBYQ1

2

I C-Bus Recommendations

2

V

I C-BUS Input Low Voltage

I C_CL,

0.3

1.0

V

IMIL

IMIH

SUP2

2

I C_DA

2

I C-BUS Input High Voltage

0.6

SUP2

2

f

t

I C-BUS Frequency

I C_CL

MHz

ns

IM

2

I C START Condition Setup Time

I C_CL,

120

500

55

I2C1

I2C2

I2C3

I2C4

I2C5

2

I C_DA

2

I C STOP Condition Setup Time

ns

2

I C-Clock Low Pulse Time

I C_CL

ns

2

I C-Clock High Pulse Time

ns

2

I C-Data Setup Time Before

I C_CL,

ns

2

Rising Edge of Clock

I C_DA

2

t

I C-Data Hold Time after Falling

55

ns

I2C6

Edge of Clock

2

V

I S-Data Input Low Voltage

I2S_DA_IN1/2

0.25

V

I2SIL

I2SIH

I2S1

SUP2

2

I S-Data Input High Voltage

0.75

20

SUP2

2

t

I S-Data Input Setup Time

I2S_DA_IN1/2,

I2S_CL

ns

before Rising Edge of Clock

2

t

I S-Data Input Hold Time

0

ns

I2S2

after Falling Edge of Clock

18

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

Symbol

Parameter

Min.

Typ.

1.024

32.0

Max.

Unit

Pin Name

2

V

I S-Input Low Voltage when DPL

I2S_CL,

I2S_WS

0.25

V

I2SIDL

I2SIDH

I2SCL

SUP2

3520/19/18A in I2S-Slave-Mode

2

V

I S-Input High Voltage when DPL

0.75

V

3520/19/18A in I2S-Slave-Mode

2

f

I S-Clock Input Frequency when

I2S_CL

MHz

kHz

ns

DPL 3520/19/18A in I2S-Slave-

Mode

2

R

I S-Clock Input Ratio when

0.9

1.1

I2SCL

I2SWS

I2SWS1

DPL 3520/19/18A in I2S-Slave-

Mode

2

f

t

I S-Wordstrobe Input Frequency

I2S_WS

when DPL 3520/19/18A in I2S-

Slave-Mode

2

I S-Wordstrobe Input Setup Time

I2S_WS,

I2S_CL

60

0

before Rising Edge of Clock when

DPL 3520/19/18A in I2S-Slave-

Mode

2

t

I S-Wordstrobe Input Hold Time

ns

I2SWS2

after Falling Edge of Clock when

DPL 3520/19/18A in I2S-Slave-

Mode

Crystal Recommendations for Master-Slave Application

f

P

Parallel Resonance Frequency at

12 pF Load Capacitance

18.432

MHz

f

Accuracy of Adjustment

–20

+20

ppm

TOL

D

Frequency Variation versus

Temperature

TEM

R

C

0

C

1

Series Resistance

8

25

Ω

Shunt (Parallel) Capacitance

Motional (Dynamic) Capacitance

6.2

24

7.0

pF

fF

19

Load Capacitance Recommendations for Master-Slave Applications

2)

C

L

External Load Capacitance

XTAL_IN,

XTAL_OUT

PSDIP

PLCC

1.5

3.3

pF

f

CL

Required Open Loop Clock

18.431

18.433

MHz

Frequency (T

= 25°C)

amb

Micronas

19

DPL 35xxA

PRELIMINARY DATA SHEET

Symbol

Parameter

Min.

Typ.

Max.

Unit

Pin Name

Crystal Recommendations for Stand Alone Application (No Master-Slave Mode possible)

f

Parallel Resonance Frequency at

12 pF Load Capacitance

18.432

MHz

P

Accuracy of Adjustment

–100

–50

+100

+50

ppm

TOL

D

Frequency Variation versus

Temperature

TEM

R

C

Series Resistance

8

25

Ω

R

Shunt (Parallel) Capacitance

6.2

7.0

pF

0

Load Capacitance Recommendations for Stand Alone Application (No Master-Slave Mode possible)

2)

C

L

External Load Capacitance

XTAL_IN,

XTAL_OUT

PSDIP

PLCC

1.5

3.3

pF

Amplitude Recommendation for Operation with External Clock Input (C

after reset = 22 pF)

load

V

XCA

External Clock Amplitude

XTAL_IN

0.7

V

pp

Analog Input and Output Recommendations

C

AGNDC-Filter-Capacitor

AGNDC

–20% 3.3

–20% 100

µF

AGNDC

Ceramic Capacitor in Parallel

nF

1)

DC-Decoupling Capacitor in front

of SCART Inputs

SCn_IN_s

–20% 330

+20%

nF

inSC

V

SCART Input Level

2.0

V

inSC

RMS

Input Level, Mono Input

SCART Load Resistance

SCART Load Capacitance

Channel1/2 Volume Capacitor

Channel1/2 Filter Capacitor

MONO_IN

inMONO

RMS

1)

R

C

SCn_OUT_s

10

kΩ

nF

µF

nF

LSC

VMA

FMA

7.5

1)

CAPL_s

10

1)

DACp_s

–10%

1

+10%

C

VREFTOP-Filter-Capacitor

VREFTOP

–20% 10

µF

VREFTOP

1)

2)

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “C1” or “C2”

External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-

quency of the internal PLL and to stabilize the frequency in closed-loop operation. The higher the capacitors,

the lower the clock frequency results. The nominal free running frequency should match 18.432 MHz as closely

as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the

application. The suggested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.

20

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

3.5.3. Characteristics

at T = 0 to 70 °C, f

= 18.432 MHz, V

= 7.6 to 8.4 V, V

= 4.75 to 5.25 V for min./max. values

SUP2,3

A

CLOCK

SUP1

(Typical values are measured at T = 25 °C, AHVSUP = 8 V, DVSUP = 5 V, AVSUP = 5 V.)

A

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

DCO

f

Clock Input Frequency

Clock High to Low Ratio

XTAL_IN

18.432

MHz

%

CLOCK

D

45

55

50

CLOCK

JITTER

t

Clock Jitter (verification not

provided in production test)

ps

V

DC-Voltage Oscillator

2.5

0.4

V

xtalDC

t

Oscillator Startup Time at

XTAL_IN,

1.0

ms

Startup

VDD Slew-rate of 1 V / 1 µs

XTAL_OUT

Power Supply

I

First Supply Current (active)

Analog Volume for channel1/2 at 0dB

Analog Volume for channel1/2 at –30dB

AHVSUP

f = 18.432 MHz

AHVSUP = 8 V

DVSUP = 5 V

AVSUP = 5 V

SUP1A

8.2

5.6

14.8

10.0

22.0

15.0

mA

at T = 27 °C

j

I

Second Supply Current (active)

Third Supply Current (active)

First Supply Current

DVSUP

AVSUP

AHVSUP

60

65

25

5.0

70

mA

f = 18.432 MHz

DVSUP = 5 V

SUP2A

SUP3A

SUP1S

f = 18.432 MHz

AVSUP = 5 V

2.8

7.2

STANDBYQ = low

VSUP = 8 V

(standby mode) at T = 27 °C

j

Audio Clock Output

V

Audio Clock Output AC Voltage

Audio Clock Output DC Voltage

AUD_CL_OUT

1.2

0.4

V

40 pF load

APUAC

pp

V

0.6

0.4

APUDC

SUP1

Digital Output

V

Digital Output Low Voltage

Digital Output High Voltage

D_CTR_IO0

D_CTR_IO1

V

I

= 1 mA

DCTROL

DCTROH

DDCTR

V

4.0

= –1 mA

DDCTR

2

I C Bus

2

V

I C-Data Output Low Voltage

I C_DA

0.4

1

V

I

= 3 mA

IMOL

IMOH

IMOL1

IMOL

2

I

t

I C-Data Output High Current

µA

V

= 5 V

IMOH

2

I C-Data Output Hold Time after

I C_DA,

15

ns

2

Falling Edge of Clock

I C_CL

2

t

I C-Data Output Setup Time

100

ns

f

IM

= 1 MHz

IMOL2

before Rising Edge of Clock

DVSUP = 5 V

2

I S Bus

2

V

I S Output Low Voltage

I2S_WS,

I2S_CL,

I2S_DA_OUT

0.4

V

I

= 1 mA

I2SOL

I2SOH

I2SCL

I2SWS

I2SOL

2

V

I S Output High Voltage

4.0

V

= –1 mA

I2SOH

2

f

I S-Clock Output Frequency

I2S_CL

I2S_WS

1204

32.0

kHz

DVSUP = 5 V

2

I S-WordstrobeOutputFrequency

Micronas

21

DPL 35xxA

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

0.9

Typ.

Max.

Unit

Test Conditions

2

t

I S-Clock High/Low-Ratio

I2S_CL

1.0

1.1

I2S1/I2S2

I2S3

2

I S-Data Setup Time

I2S_CL,

I2S_DA_OUT

200

ns

DVSUP = 4.75 V

DVSUP = 5.25 V

DVSUP = 4.75 V

DVSUP = 5.25 V

before Rising Edge of Clock

2

t

I S-Data Hold Time after Falling

12

I2S4

I2S5

I2S6

Edge of Clock

2

I S-Wordstrobe Setup Time

I2S_CL,

I2S_WS

100

50

before Rising Edge of Clock

2

I S-Wordstrobe Hold Time after

Falling Edge of Clock

Analog Ground

V

AGNDC Open Circuit Voltage

AGNDC Output Resistance

AGNDC

3.64

3.73

125

3.84

V

R

≥ 10 MΩ

load

AGNDC0

R

3 V ≤ V

≤ 4 V

outAGN

AGNDC

at T = 27 °C

70

180

kΩ

j

from T = 0 to 70 °C

A

Analog Input Resistance

1)

R

SCART Input Resistance

at T = 27 °C

SCn_IN_s

f

= 1 kHz,

inSC

signal

25

40

16

58

kΩ

I ≤ 0.05 mA

j

from T = 0 to 70 °C

A

R

MONO Input Resistance

MONO_IN

f

= 1 kHz,

inMONO

signal

at T = 27 °C

10

23

kΩ

I ≤ 0.1 mA

j

from T = 0 to 70 °C

A

Audio Analog-to-Digital-Converter

1)

V

Analog Input Clipping Level for

Analog-to-Digital-Conversion

SCn_IN_s,

MONO_IN

2.00

2.12

0.33

2.25

V

f

= 1 kHz

AICL

RMS

signal

SCART Outputs

1)

R

SCART Output Resistance

SCn_OUT_s

= 1 kHz, I = 0.1 mA

outSC

signal

at T = 27 °C

0.20

0.46

0.5

kΩ

j

from T = 0 to 70 °C

A

dV

OUTSC

Deviation of DC-Level at SCART

Output from AGNDC Voltage

–70

+70

mV

1)

A

Gain from Analog Input to SCART

Output

SCn_IN_s

f

= 1kHz

SCtoSC

signal

MONO_IN

→

SCn_OUT_s

–1.0

–0.5

1.8

0

+0.5

2.0

dB

1)

f

Frequency Response from Analog

Input to SCART Output

bandwidth: 0 to 20000 Hz

with respect to 1 kHz

rSCtoSC

0

V

outSC

Signal Level at SCART-Output

during full-scale digital input signal

from DSP

SCn_OUT_s

1.9

V

RMS

f

= 1 kHz

signal

1)

“n” means “1”, “2” or “3”,

“s” means “L” or “R”, “p” means “C1” or “C2”

22

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Channel 1 and 2 Outputs

1)

R

Channel1/2 Output Resistance

at T = 27 °C

DACp_s

f

= 1 kHz, I = 0.1 mA

outMA

signal

2.1

3.3

4.6

5.0

kΩ

j

from T = 0 to 70 °C

A

V

DC-Level at Channel1/2-Output

for Analog Volume at 0 dB

outDCMA

1.74

–

1.94

61

2.28

–

V

mV

for Analog Volume at –30 dB

V

outMA

SignalLevelatChannel1/2-Output

during full-scale digital input signal

from DSP for Analog Volume at

0 dB

1.23

1.37

1.51

V

RMS

f

= 1 kHz

signal

Analog Performance

SNR Signal-to-Noise Ratio

from Analog Input to DSP

MONO_IN,

SCn_IN_s

85

93

85

88

96

88

dB

Input Level = –20 dB with

resp. to V , f = 1

1)

AICL sig

kHz, equally weighted

2)

20 Hz...16 kHz

from Analog Input to

SCART Output

MONO_IN,

Input Level = –20 dB,

1)

SCn_IN_s

→

f

sig

= 1 kHz,

equally weighted

20 Hz...20 kHz

1)

SCn_OUT_s

from DSP to SCART Output

SCn_OUT_s

Input Level = –20 dB,

f

sig

= 1 kHz,

equally weighted

3)

20 Hz...15 kHz

1)

from DSP to Channel1/2-Output

for Analog Volume at 0 dB

DACp_s

Input Level = –20 dB,

f

sig

= 1 kHz,

for Analog Volume at –30 dB

85

78

88

83

dB

equally weighted

20 Hz...15 kHz

3)

THD

Total Harmonic Distortion

from Analog Input to DSP

MONO_IN,

SCn_IN_s

0.05

%

Input Level = –3 dBr with

1)

resp. to V , f =1kHz,

AICL sig

equally weighted

20 Hz...16 kHz,

2)

R

= 30 kΩ

Load

from Analog Input to

SCART Output

MONO_IN,

SCn_IN_s

→

0.01

0.03

%

Input Level = –3 dBr,

= 1 kHz, equally

weighted 20 Hz...20 kHz,

R = 30 kΩ

Load

f

sig

1)

SCn_OUT_s

from DSP to SCART Output

SCn_OUT_s

Input Level = –3 dBr,

= 1 kHz, equally

f

sig

weighted 20 Hz...16 kHz,

3)

R

= 30 kΩ

Load

1)

from DSP to Channel1/2 Output

DACp_s

Input Level = –3 dBr,

= 1 kHz, equally

f

sig

weighted 20 Hz...16 kHz,

3)

R

= 30 kΩ

Load

1)

“n” means “1”, “2” or “3”,

“s” means “L” or “R”, “p” means “C1” or “C2”

2)

3)

2

DSP measured at I S-Output

2

DSP Input at I S-Input

Micronas

23

DPL 35xxA

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

XTALK

Crosstalk attenuation

– PLCC68

Input Level = –3 dB,

f

sig

= 1 kHz, unused ana-

– PSDIP64

log inputs connected to

ground by Z<1 kΩ

betweenleftandrightchannelwithinSCARTInput/Out-

put pair (L→R, R→L)

equally weighted

20 Hz...20 kHz

1)

2)

SCn_IN → SCn_OUT

PLCC68

PSDIP64

80

dB

1)

SCn_IN → DSP

PLCC68

PSDIP64

80

dB

1)

3)

DSP → SCn_OUT

PLCC68

PSDIP64

80

dB

between left and right channel within channel1/2

Output pair

equally weighted

20 Hz...16 kHz

1)

3)

DSP → DACp

PLCC68

PSDIP64

80

75

dB

1)

between SCART Input/Output pairs

(equally weighted

20 Hz...20 kHz)

same signal source on

left and right disturbing

channel, effect on each

observed output channel

D = disturbing program

O = observed program

D: MONO/SCn_IN → SCn_OUT

O: MONO/SCn_IN → SCn_OUT

PLCC68

PSDIP64

100

dB

1)

2)

3)

D: MONO/SCn_IN → SCn_OUT

O: or unsel. MONO/SCn_IN → DSP

PLCC68

PSDIP64

95

dB

1)

D: MONO/SCn_IN → SC1_OUT

PLCC68

PSDIP64

100

dB

1)

O: DSP → SCn_OUT

D: MONO/SCn_IN → unselected

PLCC68

PSDIP64

100

dB

1)

O: DSP → SC1_OUT

Crosstalk between channel 1 and channel 2 Output

(equally weighted

20 Hz...16 kHz)

same signal source on

left and right disturbing

channel, effect on each

observed output channel

3)

pairs

DSP → DACp

95

90

dB

1)

PLCC68

PSDIP64

Crosstalk from channel 1 and channel 2 to SCART Out-

put and vice versa

(equally weighted

20 Hz...20 kHz)

same signal source on

left and right disturbing

channel, effect on each

observed output channel

D = disturbing program

O = observed program

D: MONO/SCn_IN/DSP → SCn_OUT

O: DSP → DACp

PLCC68

PSDIP64

90

85

dB

SCART output load resis-

tance 10 kΩ

1)

D: MONO/SCn_IN/DSP → SCn_OUT

O: DSP → DACp

PLCC68

PSDIP64

95

85

dB

SCART output load resis-

tance 30 kΩ

1)

3)

D: DSP → DACp

O: MONO/SCn_IN → SCn_OUT

PLCC68

PSDIP64

100

95

dB

1)

D: DSP → DACp

O: DSP → SCn_OUT

PLCC68

PSDIP64

100

95

dB

1)

“n” means “1”, “2” or “3”,

“s” means “L” or “R”, “p” means “C1” or “C2”

2)

3)

2

DSP measured at I S-Output

2

DSP Input at I S-Input

24

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

PSRR: rejection of noise on AHVSUP at 1 kHz

PSRR

AGNDC

80

69

dB

From analog Input to DSP

MONO_IN

SCn_IN_s

1)

From analog Input to

SCART Output

MONO_IN

SCn_IN_s,

SCn_OUT_s

74

dB

1)

From DSP to SCART Output

SCn_OUT_s

70

80

dB

1)

From DSP to channel1/2 Output

DACp_s

1)

“n” means “1”, “2” or “3”,

“s” means “L” or “R”, “p” means “C1” or “C2”

Micronas

25

DPL 35xxA

PRELIMINARY DATA SHEET

3.5.4. Measurements According to Dolby Specifications, Typical Values

(Typical values are measured at T = 25 °C, AHVSUP = 8 V, DVSUP = 5 V, AVSUP = 5 V.)

A

Crosstalk at cardinal point at High Level Input

(+15 dB @ 1 kHz = 0 dB Full Scale = 2 Vrms)

Channel

Left:

L

C

R

S

+0.17

–53

–68

–56

–60

0.0

–62

–70

–68

–53

+0.03

–56

–57

–63

–60

+0.02

Center:

Right:

Surround:

Crosstalk at cardinal point at Low Level Input (–20dB @ 1kHz = –35dBdB Full

Scale)

Channel

Left:

L

C

R

S

+0.08

–45

–39

–44

0.0

–44

–46

0.05

–44

–41

–2.58

Center:

Right:

Surround:

Frequency Response Characteristics

Mode

L

C

R

S

Normal

Wide

20/15.4k

100/15.4k

20/15.4k

––––––––––

20/15.4k

20/7k

Phantom

SNR Measurements

L

C

R

S

Weighted

–69dB

Measured on the Dolby Stand Alone Board.

Conditions: 355 mVrms @ SCART1IN with 2 kHz

Scart Prescale = 20 h,

Vol = –9 dB

100 mVrms output @DAC1out

measured with CCIR/ARM (System One: CCIR–2k, AVG)

26

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

2

4. I C-Bus Interface

done by sending the device read address (81 hex,

85 hex, or 89 hex) and reading two bytes of data. Refer

2

to Fig. 4–1: I C-Bus Protocol and section 4.2.: Proposal

2

As a slave receiver, the DPL can be controlled via I C-

bus. Access to internal memory locations is achieved by

subaddressing. TheMODE_REG, theCONTROLregis-

ter and the DFP processor have separate subaddres-

sing register banks.

2

for DPL I C-Telegrams.

Due to the internal architecture of the DPL, the IC cannot

2

react immediately to an I C request. The typical re-

sponsetimeisabout0.3ms. Ifthereceiver(DPL)cannot

receive another complete byte of data until it has per-

formed some other function, it can hold the clock line

I2C_CL LOW to force the transmitter into a wait state.

The positions within a transmission where this may hap-

pen are indicated by ‘Wait’ in section 4.1. The maximum

wait period of the DPL during normal operation mode is

less than 1 ms.

In order to allow for more DPL or MSP ICs to be con-

nected to the control bus, an ADR_SEL pin was imple-

mented. With ADR_SEL pulled to high, low, or left open,

the DPL responds to changed device addresses. Thus,

three identical devices can be selected.

By means of the RESET bit in the CONTROL register,

all devices with the same device address are reset.

2

I C-Bus error conditions:

If an internal error occurs, the DPLs wait period is ex-

tended to a maximum of 1.8 ms. Afterwards, the DPL

does not acknowledge (NAK) the device address. The

data line will be left HIGH by the DPL and the clock line

will be released. The master can then generate a STOP

condition to abort the transfer.

The IC is selected by asserting a special device address

in the address part of an I C-transmission. A device ad-

2

dress pair is defined as a write address (80 hex, 84 hex,

or 88 hex) and a read address (81 hex, 85 hex, or

89 hex). Writing is done by sending the device write ad-

dress first, followed by the subaddress byte, two ad-

dress bytes, and two data bytes. For reading, the read

address has to be transmitted first by sending the device

writeaddress(80hex, 84hex, or88hex), followedbythe

subaddress byte and two address bytes. Without send-

ing a stop condition, reading of the addressed data is

By means of NAK, the master is able to recognize the er-

2

ror state and to reset the IC via I C-Bus. While transmit-

ting the reset protocol (see 4.1.) to ‘CONTROL’, the

master must ignore the ‘Not Acknowledge Bits’ (NAK) of

the DPL.

2

Table 4–1: I C-Bus Device and Subaddresses

Name

Binary

Value

Hex

Value

Hex

Value

Hex

Value

Mode

Function

ADR_SEL=

high

low

left open

88/89

DPL

1000 xx0x

0000 0000

0001 0000

80/81

84/85

00

R/W

W

DPL device address

CONTROL

WR_MR

software reset

10

W

write address

MODE_REG

RD_MD

0001 0001

11

W

read address

MODE_REG

WR_DFP

RD_DFP

0001 0010

0001 0011

12

13

W

write address DFP

read address DFP

Table 4–2: Control Register

Name

MSB

14

13..1

LSB

CONTROL

RESET

0

Micronas

27

DPL 35xxA

PRELIMINARY DATA SHEET

4.1. Protocol Description

Write to DFP or MODE_REG

S

hex 80

Wait ACK

sub-addr

ACK

addr-byte

high

ACK addr-byte low ACK data-byte high ACK data-byte low ACK

P

Read from DFP or MODE_REG

S

hex 80

Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK

high low

S

hex 81

Wait ACK data-byte ACK data-byte NAK

high low

P

Write to the Control Register

S

hex 80

Wait ACK

sub-addr

ACK

data-byte high

ACK

data-byte low

ACK

P

2

Note: S =

I C-Bus Start Condition from master

2

P =

I C-Bus Stop Condition from master

2

ACK =

Acknowledge-Bit: LOW on I C_DA from slave (=DPL, grey)

or master (=CCU, hatched)

Not Acknowledge-Bit: HIGH on I C_DA from master (=CCU, hatched) to indicate ‘End of Read’

2

NAK =

Wait =

or from DPL indicating internal error state

I C-Clock line held low by the slave (=DPL) while interrupt is serviced (<1 ms)

2

1

0

2

I C_DA

S

P

2

I C_CL

2

Fig. 4–1: I C-bus protocol

(MSB first; data must be stable while clock is high)

2

4.2. Proposal for DPL I C-Telegrams

4.2.3. Read Telegrams

<daw 11 aa aa <dar dd dd> read data from MODE_REG

register

<daw 13 aa aa <dar dd dd> read data from DFP register

4.2.1. Symbols

daw Write Device Address

dar Read Device Address

4.2.4. Examples

<

Start Condition

Stop Condition

Address Byte

Data Byte

<80 00 80 00>

RESET DPL statically

clear RESET

set channel source 1

to DOLBYLR and Matrix to

STEREO

>

<80 00 00 00>

aa

dd

<80 12 00 08 03 20>

4.2.2. Write Telegrams

4.3. Start-Up Sequence

software RESET

write data into MODE_REG

register

write data into DFP register

After power on or RESET, the IC is in an inactive state.

The CCU has to transmit the required coefficient set for

a given operation via the I C-bus.

2

28

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

2

5. Audio PLL and Crystal Specifications

5.1. Operation with Crystal

6. I S-Bus Interface

By means of this standardized interface, additional fea-

ture processors can be connected to the DPL. Two pos-

sible formats are supported: The standard mode

(MODE_REG[4]=0) selects the SONY format, where

theI2S_WSsignalchangesatthewordboundaries. The

so-called PHILIPS format, which is characterized by a

change of the I2S_WS signal one I2S_CL period before

the word boundaries, is selected by setting

MODE_REG[4]=1.

The DPL requires a 18.432 MHz (12 pF, parallel) crystal.

The clock supply of the whole system depends on the

DPL operation mode:

1. Stand-Alone

The system clock runs free on the crystal’s 18.432 MHz.

2

2. I S slave operation:

In this case, the system clock is locked to a synchroniz-

ing signal (I2S_WS) supplied by the coprocessor chip.

2

The DPL normally serves as the slave on the I S inter-

2

face (default setting after power-up). I S-clock and word

strobe lines are input to the DPL and the master clock is

synchronized to 576 times the I2S_WS rate (32 kHz). By

settingMODE_REG[3]=0, theDPLisswitchedtoMaster

Mode. Now, these lines are input to the DPL and the

master clock is synchronized to 576 times the I2S_WS

rate (32 kHz).

Remark on using the crystal:

External capacitors are required at each crystal pin to

ground. Theyarenecessaryfortuningtheopen-loopfre-

quency of the internal PLL and for stabilizing the fre-

quency in closed-loop operation. The higher the capaci-

tors, the lower the clock frequency results. The nominal

free running frequency should match the center of the

tolerance range between 18.433 and 18.431 MHz as

closely as possible.

2

The I S-bus interface consists of six pins:

1. I2S_DA_IN1, I2S_DA_IN2:

For input, four channels (two channels per line, 2 16

bits) per sampling cycle (32 kHz) are transmitted.

5.2. Operation without Crystal

2. I2S_DA_OUT1, I2S_DA_OUT2:

For output, four channels (two channels per line, 2 16

bits) per sampling cycle (32 kHz) are transmitted.

When used together with a member of the MSP family,

the DPL can be driven by the 18.432 MHz clock supplied

by the MSP. The clock input is: XTAL_IN (connection via

coupling capacitor (C>1nF)). No crystal is used in this

mode.

3. I2S_CL:

2

Gives the timing for the transmission of I S serial data

(1.024 MHz).

4. I2S_WS:

The I2S_WS word strobe line defines the left and right

sample.

Micronas

29

DPL 35xxA

PRELIMINARY DATA SHEET

2

6.1. I S Bus Timing Diagram

F

I2SWS

2

I S_WS

SONY Mode

PHILIPS Mode

SONY Mode

PHILIPS Mode

PHILIPS/SONY Mode programmable by MODE_REG[4]

Detail C

2

I S_CL

Detail A

Detail B

2

I S_DAIN

R LSB L MSB

L LSB R MSB

R LSB L LSB

16 bit left channel

16 bit right channel

2

I S_DAOUT

R LSB L MSB

L LSB R MSB

R LSB L LSB

16 bit right channel

Detail C

F

I2SCL

2

I S_CL

T

I2SWS2

I2SWS1

2

I S_WS as INPUT

T

I2S6

I2S5

2

I S_WS as OUTPUT

Detail A,B

2

I S_CL

T

I2S2

I2S1

I2S3

2

I S_DA_IN

T

I2S4

2

I S_DA_OUT

30

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

7. Power-up Sequence

The reset pin should not be high (>0.45 DVSUP, see recommended operation conditions) before the 5 Volt digital pow-

ersupply (DVSUP) is >4.75 Volt and the DPL-Clock is running (Delay: 1 ms max, 0.5 ms typ.).

This means, if the reset low-high edge starts with a delay of 2 ms after DVSUP>4.75 Volt, even under worst case condi-

tions, the reset is ok.

First Supply Voltage

DVSUP/V

4.75

time / ms

Oscillator

max. 1

time / ms

RESETQ

min. 2

0.45 * DVSUP

time / ms

Fig. 7–1: Power-up sequence

Micronas

31

DPL 35xxA

PRELIMINARY DATA SHEET

8. Programming the Mode Register

All transmissions on the control bus are 16 bits wide.

Table 8–1: DPL mode register

Register

Write

Function

Address

(hex)

MODE_REG

0083

mode register

The register ‘MODE_REG’ contains the control bits de-

termining the operation mode of the DPL; Table 8–2 ex-

plains all bit positions.

Table 8–2: Control word ‘MODE_REG’

MODE_REG 0083

hex

Bit

Function

Comment

Definition

Reset

condition

Recom-

menda-

tion

[0]

[1]

not used

0

1

0

DCTR_TRI

Digital control IO 0/1

tristate

0 : active

1 : tristate

2

[2]

I2S_TRI

I S outputs tristate

0 : active

1 : tristate

1

0

(I2S_CL, I2S_WS,

I2S_DA_OUT)

[3]

I2S_MODE

Master/Slave mode of the

I S-bus

0 : Master

1 : Slave

1

0

X

0

2

[4]

I2S_WS_MODE

AUDIO_CL_OUT

not used

WS due to the Sony or

Philips-Format

0 : Sony

1 : Philips

[5]

Switch Audio_Clock_Out-

put to tristate

0 : on

1 : tristate

[15:6]

32

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

9. Programming the DSP Part

9.1. Summary of the DSP Control Registers

2

Control registers are 16 bits wide. Transmissions via I C-bus have to take place in 16-bit words. Single data entries

are 8-bit. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities.

All control registers are readable.

Note: Unused parts of the 16-bit registers must be zero.

Table 9–1: Summary of the DSP Control Registers

Name

I²C Bus

Address

High Adjustable Range, Operational

/Low Modes

Reset Mode

Valid

for

Standard MSP like Control Registers

Volume channel 1

0000_hex

H

L

[+12 dB ... –114 dB, MUTE]

MUTE

00_hex

19/20

Volume / Mode channel 1

1/8 dB Steps, Reduce Volume / Tone

Control

100%/100%

Balance channel 1 [L/R]

0001_hex

H

[0..100 / 100 % and vv][–127..0 / 0 dB

19/20

and vv]

Balance Mode channel 1

Bass channel 1

L

[Linear mode / logarithmic mode]

[+20 dB ... –12 dB]

linear mode

0 dB

19/20

0002_hex

0003_hex

0004_hex

H

L

Treble channel 1

[+15 dB ... –12 dB]

0 dB

Loudness channel 1

Loudness Filter Characteristic

[0 dB ... +17 dB]

0 dB

[NORMAL, SUPER_BASS]

[–100%...OFF...+100%]

[SBE, SBE+PSE]

NORMAL

OFF

Spatial effect strength channel 1 0005_hex

Spatial effect mode/customize

H

L

SBE+PSE

MUTE

00_hex

Volume channel 2

0006_hex

0007_hex

0008_hex

H

L

[+12 dB ... –114 dB, MUTE]

Volume / Mode channel 2

1/8 dB Steps, Reduce Volume / Tone

Control

Volume SCART channel

H

[00_hex... 7F_hex],[+12 dB ... –114 dB,

MUTE]

00_hex

19/20

Volume / Mode SCART channel

Channel 1 source

L

[Linear mode / logarithmic mode]

linear mode

19/20

H

[SCART, DOLBYLR, DOLBYCS,

DOLBYCSUB, I2S1, I2S2]

00_hex

(undefined source)

Channel 1 matrix

L

[SOUNDA, SOUNDB, STEREO,

MONO...]

SOUNDA

19/20

all

Channel 2 source

0009_hex

000a_hex

000b_hex

000c_hex

H

L

[SCART, DOLBYLR, DOLBYCS,

DOLBYCSUB, I2S1, I2S2]

00_hex

(undefined source)

Channel 2 matrix

[SOUNDA, SOUNDB, STEREO,

MONO...]

SOUNDA

SCART channel source

SCART channel matrix

I²S1 channel source

I²S1 channel matrix

Quasi-peak detector source

H

L

[SCART, DOLBYLR, DOLBYCS,

DOLBYCSUB, I2S1, I2S2]

00_hex

(undefined source)

[SOUNDA, SOUNDB, STEREO,

MONO...]

SOUNDA

H

L

[SCART, DOLBYLR, DOLBYCS,

DOLBYCSUB, I2S1, I2S2]

00_hex

(undefined source)

[SOUNDA, SOUNDB, STEREO,

MONO...]

SOUNDA

all

H

[SCART, DOLBYLR, DOLBYCS,

DOLBYCSUB, I2S1, I2S2]

00_hex

(undefined source)

all

Micronas

33

DPL 35xxA

PRELIMINARY DATA SHEET

Name

I²C Bus

Address

High Adjustable Range, Operational

/Low Modes

Reset Mode

Valid

for

Quasi-peak detector matrix

L

[SOUNDA, SOUNDB, STEREO,

MONO...]

SOUNDA

all

Prescale SCART

Prescale I²S2

000d_hex

0012_hex

0013_hex

H

[00_hex... 7F_hex

Bits [7..0]

]

00_hex

10_hex

00_hex

20

all

ACB Register (SCART

19/20

Switches and DIG_OUT Pins)

Beeper

0014_hex

0016_hex

0020_hex

0021_hex

0022_hex

0023_hex

0024_hex

0025_hex

0030_hex

H/L

H

[00_hex... 7F_hex]/[00_hex... 7F_hex

[00_hex... 7F_hex

]

0/0

19/20

Prescale I²S1

]

10_hex

BASS/TREB

0dB

all

Mode Tone Control^*)

H

[BASS/TREBLE, EQUALIZER]

[)12 dB ... *12 dB]

19(/20)^*)

19/20

Equalizer channel 1 band 1^*)

Equalizer channel 1 band 2^*)

Equalizer channel 1 band 3^*)

Equalizer channel 1 band 4^*)

Equalizer channel 1 band 5^*)

Balance channel 2 [L/R]

H

0dB

H

0dB

H

0dB

H

0dB

100%/100%

H

[0...100 / 100% and vv][–127...0 / 0 dB

and vv]

Balance Mode channel 2

Bass channel 2

L

[Linear mode / logarithmic mode]

[+20 dB ... –12 dB]

linear mode

0 dB

19/20

all

0031_hex

0032_hex

0033_hex

H

L

Treble channel 2

[+15 dB ... –12 dB]

0 dB

Loudness channel 2

Loudness filter characteristic

I²S2 channel source

[0 dB ... +17 dB]

0 dB

[NORMAL, SUPER_BASS]

NORMAL

0038_hex

H

[SCART, DOLBYLR, DOLBYCS,

DOLBYCSUB, I2S1, I2S2]

00_hex

(undefined source)

I²S2 channel matrix

L

[SOUNDA, SOUNDB, STEREO,

MONO...]

SOUNDA

all

Surround Processing Control Registers

Surround decoder mode

0040_hex

H

L

[ADAPTIVE, PASSIVE, EFFECT]

ADAPTIVE

NORMAL

all

Surround reproduction mode

[NORMAL, PHANTOM, WIDE,

DOLBY_3_STEREO, CENTER_OFF,

PANORAMA]

Surround source

0041_hex

H

L

[SCART, I2S1, I2S2, NOISE]

00_hex

(undefined source)

all

Surround source matrix

[SOUNDA, SOUNDB, STEREO,

SOUNDA

NOISEL, NOISER, NOISEC, NOISES]

Surround delay

0042_hex

0043_hex

0044_hex

0045_hex

0046_hex

H

L

[0..31 ms]

0

all

Surround input balance control

Input balance mode

[*12..)12 dB]

[AUTOMATIC, MANUAL]

[0..100%]

0

AUTOMATIC

00_hex

Surround spatial effect

Panorama sound effect

Surround reverberation

H

[0..100%]

00_hex

[0..100%]

00_hex

^*)Equalizing function only for SOUNDA (=Center) possible. Equalizer and AD input cannot work simultaneously. In the DPL 3520A

the equalizer can only be used in coprocessor mode (input via I²C and not via AD converter).

34

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.1. Volume Channel 1 and Channel 2

If the clipping mode is set to “Reduce Volume”, the fol-

lowing clipping procedure is used: To prevent severe

clippingeffectswithbass, treble, orequalizerboosts, the

internal volume is automatically limited to a level where,

in combination with either bass, treble, or equalizer set-

ting, the amplification does not exceed 12 dB.

Volume

Channel 1

0000

(DPL 3519/20)

11 MSBs

hex

Volume

0006

11 MSBs

hex

Channel 2

(DPL 3519/20)

If the clipping mode is “Reduce Tone Control”, the bass

or treble value is reduced if amplification exceeds 12 dB.

If the equalizer is switched on, the gain of those bands

isreduced, whereamplificationtogetherwithvolumeex-

ceeds 12 dB.

+12 dB

0111 1111 000x 7F0

hex

+11.875 dB

0111 1110 111x 7EE

hex

+0.125 dB

0 dB

0111 0011 001x 732

0111 0011 000x 730

hex

If the clipping mode is “Compromise Mode”, the bass or

treble value and volume are both reduced by half, if am-

plification exceeds 12 dB. If the equalizer is switched on,

thegainofthosebandsisreducedbyhalf, whereamplifi-

cation together with volume exceeds 12 dB.

hex

–0.125 dB

0111 0010 111x 72E

hex

–114.125 dB

–114 dB

Mute

0000 0001 001x 012

0000 0001 000x 010

hex

Example:

Vol.:

+6 dB

Bass:

+9 dB

Treble:

+5 dB

0000 0000 xxxx 00x

RESET

Reduce Volume

3

6

9

6

5

Fast Mute

1111 1111 111x FFE

hex

Reduce Tone

Control

The highest given positive 11-bit number (7F0 ) yields

hex

Compromise

4.5

7.5

5

in a maximum possible gain of 12 dB. Decreasing the

volume register by 1 LSB decreases the volume by

0.125 dB. Volume settings lower than the given mini-

mum mute the output. With large scale input signals,

positive volume settings may lead to signal clipping.

9.1.2. Balance Channel 1 and Channel 2

With Fast Mute, volume is reduced to mute position by

digital volume only. Analog volume is not changed. This

reduces any audible DC plops. Going back from Fast

Mute should be done to the volume step before Fast

Mute was activated.

Positivebalance settings reduce the left channel without

affecting the right channel; negative settings reduce the

right channel leaving the left channel unaffected. In lin-

ear mode, a step by 1 LSB decreases or increases the

balance by about 0.8% (exact figure: 100/127). In loga-

rithmic mode, a step by 1 LSB decreases or increases

the balance by 1 dB.

Clipping Mode

Channel 1

0000

(DPL 3519/20)

3 LSBs

hex

Balance Mode

Channel 1

0001

(DPL 3519/20)

LSB

hex

Clipping Mode

Channel 2

0006 3 LSBs

hex

(DPL 3519/20)

Balance Mode

Channel 2

0030

hex

Reduce Volume

x000

RESET

0

hex

(DPL 3519/20)

linear

xxx0

RESET

0

hex

Reduce Tone Control

Compromise Mode

x001

x010

1

2

hex

logarithmic

xxx1

1

hex

Micronas

35

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.3. Bass Channel 1 and Channel 2

Balance Channel 1

[L/R]

0001

(DPL 3519/20)

H

hex

Bass Channel 1

Bass Channel 2

0002

(DPL 3519/20)

H

hex

Balance Channel 2

[L/R]

0030

hex

(DPL 3519/20)

0031

hex

Left muted, Right 100%

Left 0.8%, Right 100%

0111 1111

7F

7E

hex

(DPL 3519/20)

0111 1110

hex

+20 dB

+18 dB

+16 dB

+14 dB

+12 dB

+11 dB

0111 1111

7F

78

70

68

60

58

hex

Left 99.2%, Right 100%

Left 100%, Right 100%

0000 0001

01

00

hex

0111 1000

0111 0000

0110 1000

0110 0000

0101 1000

0000 0000

RESET

hex

Left 100%, Right 99.2%

1111 1111

FF

hex

Left 100%, Right 0.8%

Left 100%, Right muted

1000 0010

1000 0001

82

81

hex

+1 dB

0000 1000

0000 0001

08

hex

+1/8 dB

0 dB

01

00

hex

Balance Channel 1

[L/R]

0001

(DPL 3519/20)

H

0000 0000

RESET

hex

Balance Channel 2

[L/R]

0030

–1/8 dB

–1 dB

1111 1111

1111 1000

FF

F8

hex

(DPL 3519/20)

hex

Left –127 dB, Right 0 dB

Left –126 dB, Right 0 dB

0111 1111

7F

hex

–11 dB

–12 dB

1010 1000

1010 0000

A8

A0

hex

0111 1110

7E

hex

Left –1 dB, Right 0 dB

0000 0001

01

00

hex

Left 0 dB, Right 0 dB

0000 0000

RESET

hex

With positive bass settings, internal overflow may occur

even with overall volume less than 0 dB. This will lead to

a clipped output signal. Therefore, it is not recom-

mended to set bass to a value that, in conjunction with

volume, would result in an overall positive gain.

Left 0 dB, Right –1 dB

1111 1111

FF

hex

Left 0 dB, Right –127 dB

Left 0 dB, Right –128 dB

1000 0001

1000 0000

81

80

hex

Loudspeaker channel: Bass and Equalizer cannot work

simultaneously (see Table: Mode Tone Control). If

Equalizer is used, Bass and Treble coefficients must be

set to zero and vice versa.

hex

36

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.4. Treble Channel 1 and Channel 2

9.1.5. Loudness Channel 1 and Channel 2

Treble Channel 1

Treble Channel 2

0003

(DPL 3519/20)

H

Loudness

Channel 1

0004

(DPL 3519/20)

H

hex

0032

Loudness

Channel 2

0033

hex

(DPL 3519/20)

+15 dB

+14 dB

0111 1000

78

70

+17 dB

+16 dB

0100 0100

44

40

hex

0111 0000

0100 0000

hex

+1 dB

0000 1000

0000 0001

08

+1 dB

0 dB

0000 0100

04

00

hex

0000 0000

RESET

+1/8 dB

0 dB

01

00

hex

0000 0000

RESET

hex

Mode Loudness

Channel 1

0004

(DPL 3519/20)

L

hex

–1/8 dB

–1 dB

1111 1111

1111 1000

FF

F8

hex

Mode Loudness

Channel 2

0033

L

hex

(DPL 3519/20)

–11 dB

–12 dB

1010 1000

1010 0000

A8

A0

hex

Normal (constant

volume at 1 kHz)

0000 0000

RESET

00

04

hex

Super Bass (constant

volume at 2 kHz)

0000 0100

hex

Withpositivetreblesettings, internaloverflowmayoccur

even with overall volume less than 0 dB. This will lead to

a clipped output signal. Therefore, it is not recom-

mended to set treble to a value that, in conjunction with

volume, would result in an overall positive gain.

Loudnessincreasesthevolumeoflowandhighfrequen-

cy signals, while keeping the amplitude of the 1 kHz ref-

erence frequency constant. The intended loudness has

to be set according to the actual volume setting. Be-

cause loudness introduces gain, it is not recommended

to set loudness to a value that, in conjunction with vol-

ume, would result in an overall positive gain.

Loudspeaker channel: Treble and Equalizer cannot

work simultaneously (see Table: Mode Tone Control). If

Equalizer is used, Bass and Treble coefficients must be

set to zero and vice versa.

By means of ‘Mode Loudness’, the corner frequency for

bass amplification can be set to two different values. In

Super Bass mode, the corner frequency is shifted up.

The point of constant volume is shifted from 1 kHz to

2 kHz.

Micronas

37

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.6. Spatial Effects Channel 1

There are several spatial effect modes available:

Mode A (low byte = 00 ) is compatible to the formerly

hex

Spatial Effect

0005

H

hex

used spatial effect. Here, the kind of spatial effect de-

pends on the source mode. If the incoming signal is in

mono mode, Pseudo Stereo Effect is active; for stereo

signals, Pseudo Stereo Effect and Stereo Basewidth

Enlargement is effective. The strength of the effect is

controllable by the upper byte. A negative value reduces

the stereo image. A rather strong spatial effect is recom-

mended for small TV sets where loudspeaker spacing is

rather close. For large-screen TV sets, a more moderate

spatial effect is recommended. In mode A, even in case

of stereo input signals, Pseudo Stereo Effect is active,

which reduces the center image.

Strength Channel 1

(DPL 3519/20)

Enlargement 100%

Enlargement 50%

0111 1111

0011 1111

7F

3F

hex

Enlargement 1.5%

Effect off

0000 0001

01

00

hex

0000 0000

RESET

hex

Reduction 1.5%

Reduction 50%

Reduction 100%

1111 1111

1100 0000

1000 0000

FF

C0

hex

In Mode B, only Stereo Basewidth Enlargement is effec-

tive. For mono input signals, the Pseudo Stereo Effect

has to be switched on.

80

It is worth mentioning that all spatial effects affect ampli-

tude and phase response. With the lower 4 bits, the fre-

Spatial Effect Mode

Channel 1

0005

(H nibble)

(DPL 3519/20)

L

hex

quency response can be customized. A value of 0000

bin

yields a flat response for center signals (L = R) but a high

pass function of L or R only signals. A value of 0110

bin

has a flat response for L or R only signals but a lowpass

Stereo Basewidth En-

largement (SBE) and

Pseudo Stereo Effect

(PSE). (Mode A)

0000

RESET

0000

0

hex

function for center signals. By using 1000 , the fre-

bin

quency response is automatically adapted to the sound

material by choosing an optimal high pass gain.

hex

Stereo Basewidth

Enlargement (SBE)

only. (Mode B)

0010

2

hex

Spatial Effect Cus-

tomize Coefficient

Channel 1

0005

(L nibble)

(DPL 3519/20)

L

hex

max high pass gain

0000

RESET

0

hex

2/3 high pass gain

1/3 high pass gain

min. high pass gain

automatic

0010

0100

0110

1000

2

hex

4

hex

6

hex

8

hex

38

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.7. Volume SCART Channel

Linear Mode

9.1.8. Channel Source Modes

Channel 1 source

Channel 2 source

SCART source

0008

(DPL 3519/20)

H

hex

Volume SCART

0007

(DPL 3519/20)

H

hex

0009

(DPL 3519/20)

hex

OFF

0000 0000

RESET

00

40

hex

000a

(DPL 3519/20)

hex

0 dB gain

0100 0000

hex

2

I S1 source

000b

(digital full scale (FS)

hex

(DPL 3518/19/20)

to 2 V

output)

RMS

2

I S2 source

0038

(DPL 3518/19/20)

H

+6 dB gain (–6 dBFS

to 2 V output)

0111 1111

7F

hex

RMS

Quasi-peak detector

source

000c

(DPL 3518/19/20)

H

hex

Logarithmic Mode

Volume SCART

SCART

DOLBYLR

DOLBYCS

I2S1

(20)

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

02

03

04

05

06

07

hex

0007

(DPL 3519/20)

11 MSBs

hex

(18/19/20)

+12 dB

0111 1111 000x 7F0

hex

+11.875 dB

0111 1110 111x 7EE

hex

I2S2

+0.125 dB

0 dB

0111 0011 001x 732

0111 0011 000x 730

hex

DOLBYCSUB (18/19/20)

hex

–0.125 dB

0111 0010 111x 72E

hex

DOLBYLR denotes a signal pair consisting of surround

decoder output for the left and right loudspeakers. The

signal content depends on the used surround reproduc-

tion mode. DOLBYCS is the signal pair for the center

and surround information (if there is any, depending on

the surround reproduction mode). DOLBYCSUB is a

signal pair consisting of the center information and a

subwoofer channel. The subwoofer channel is the sum

of all low frequency components (fg=100Hz) of the L, R

and C channels.

–114.125 dB

–114 dB

Mute

0000 0001 001x 012

0000 0001 000x 010

hex

0000 0000 0000 000

RESET

Volume Mode SCART

linear

0007

(DPL 3519/20)

LSB

hex

2

The I S2 source must not be 00 . It should be one

hex

of the mentioned values, otherwise the SCART

source will not work properly.

xxx0

RESET

0

hex

If the equalizer is switched on, SCART as source is

no longer valid, i.e. AD input is no longer possible.

logarithmic

xxx1

1

hex

Micronas

39

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.9. Channel Matrix Modes

Channel 1 matrix

The sum/difference mode can be used together with the

quasi-peak detector to determine the sound material

mode. If the difference signal on channel B (right) is near

to zero, and the sum signal on channel A (left) is high,

theincomingaudiosignalismono. Ifthereisasignificant

level on the difference signal, the incoming audio is ste-

reo.

0008

L

hex

(DPL 3519/20)

Channel 2 matrix

SCART matrix

0009

(DPL 3519/20)

hex

000a

(DPL 3519/20)

hex

The inv_stereo mode can be used to phase invert out-

2

puts via the I S interfaces. This gives the option to cor-

rect phase relations with outputs of attached proces-

sors.

2

I S1 matrix

000b

hex

(DPL 3518/19/20)

2

I S2 matrix

0038

L

hex

(DPL 3518/19/20)

9.1.10. SCART Prescale

Quasi-peak detector

matrix

000c

(DPL 3518/19/20)

L

hex

Volume Prescale

SCART

000d

(DPL 3520)

H

hex

SOUNDA, LEFT or

CENTER

0000 0000

RESET

00

hex

OFF

0000 0000

RESET

00

19

7F

hex

SOUNDB, RIGHT,

SURROUND or SUB-

WOOFER

0001 0000

10

0 dB gain (2 V

in-

0001 1001

RMS

put to digital full scale)

STEREO

0010 0000

0011 0000

0100 0000

0101 0000

0110 0000

0111 0000

1000 0000

1001 0000

1111 0000

20

30

40

50

60

70

80

90

F0

+14 dB gain

0111 1111

hex

(400 mV

input to

RMS

MONO

digital full scale)

SUM/DIFF

AB_XCHANGE

PHASE_CHANGE_B

PHASE_CHANGE_A

A_ONLY

2

9.1.11. I S1 and I S2 Prescale

Volume Prescale

0016

H

hex

2

I S1

(DPL 3518/19/20)

Volume Prescale

0012

H

hex

2

B_ONLY

I S2

(DPL 3518/19/20)

INV_STEREO

OFF

00

hex

0 dB gain

10

hex

RESET

7F

+18 dB gain

hex

40

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.12. ACB Register, Definition of the SCART-

Switches and DIG_CTR_OUT Pins

9.1.13. Beeper

Beeper Volume

0014

H

hex

(DPL 3519/20)

ACB Register

0013

H

hex

(DPL 3519/20)

OFF

0000 0000

RESET

00

hex

DFP In Selection

SCART1_IN

MONO_IN

xxxx xx00

xxxx xx01

xxxx xx10

xxxx xx11

RESET

Maximum Volume (full

digital scale FDS)

0111 1111

7F

SCART2_IN

SCART3_IN

SCART1_OUT

Selection

Beeper Frequency

0014

L

hex

(DPL 3519/20)

0000 0001

0100 0000

1111 1111

SCART3_IN

SCART2_IN

MONO_IN

xxxx 00xx

xxxx 01xx

xxxx 10xx

xxxx 11xx

16 Hz (lowest)

1 kHz

01

40

hex

DA_SCART

4 kHz (highest)

FF

hex

SCART2_OUT

Selection

DA_SCART

SCART1_IN

MONO_IN

xx00 xxxx

xx01 xxxx

xx10 xxxx

A squarewave beeper can be added to the loudspeaker

channel and the headphone channel. The addition point

is just before loudness and volume adjustment.

DIG_CTR_OUT1

low

high

x0xx xxxx

x1xx xxxx

RESET

9.1.14. Mode Tone Control

DIG_CTR_OUT2

Mode Tone Control

Bass and Treble

Equalizer

00020

(DPL 3519/20)

H

hex

low

high

0xxx xxxx

1xxx xxxx

0000 0000

RESET

00

hex

RESET: The RESET state is taken at the time of

the first write transmission on the control bus to

the audio processing part (DFP). By writing to the

ACB register first, the RESET state can be rede-

fined.

1111 1111

FF

hex

By means of ‘Mode Tone Control’, Bass/Treble or Equal-

izer may be activated.

The Equalizer must also not be used simultaneously

with AD input (Source mode = SCART).

Micronas

41

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.15. Equalizer Channel 1

9.1.16. Surround Decoder Modes

Band 1 1

(below 120 Hz)

00021

(DPL 3519)

H

Surround Decoder

Modes

0040

(DPL 3518/19/20)

H

hex

Band 2

(center: 500 Hz)

00022

ADAPTIVE

(Dolby Pro Logic)

0000 0000

RESET

00

hex

(DPL 3519)

Band 3

(center: 1500 Hz)

00023

PASSIVE

EFFECT

0001 0000

0010 0000

10

20

hex

(DPL 3519)

hex

Band 4

(center: 5000 Hz)

00024

hex

(DPL 3519)

The surround decoder mode specifies which method is

being used to create four output channels out of two in-

put channels. For Dolby Pro Logic operation the matrix

must be switched to ADAPTIVE. Even sound material

not encoded in Dolby Surround will produce good sur-

round effects in this mode. All surround reproduction

modes can be used together with the ADAPTIVE mode.

The PASSIVE mode should only be used together with

WIDE mode. The EFFECT mode is intended to get sur-

round effects even in case of mono transmissions (Note:

For mono signals, Dolby Pro Logic will only reproduce

signals via the center channel. All other channels will be

muted). For a more detailed description see section

10.2. “Useful combinations of the surround decoder and

reproduction modes”.

Band 5

(above 10000 Hz)

00025

hex

(DPL 3519)

0110 0000

0101 1000

+12 dB

+11 dB

60

58

hex

+1 dB

0000 1000

0000 0001

08

hex

+1/8 dB

0 dB

01

00

hex

0000 0000

RESET

hex

–1/8 dB

–1 dB

1111 1111

1111 1000

FF

F8

hex

–11dB

1010 1000

1010 0000

A8

A0

hex

–12 dB

hex

With positive equalizer settings, internal overflow may

occur even with overall volume less than 0 dB. This will

leadtoaclippedoutputsignal. Therefore, itisnotrecom-

mended to set Equalizer bands to a value that, in con-

junction with volume, would result in an overall positive

gain.

The Equalizer must not be used simultaneously with

Bass and Treble (Mode Tone Control must be set to FF

to use the Equalizer). If Bass and Treble are used,

Equalizer coefficients must be set to zero.

The Equalizer must also not be used simultaneously

with AD input (Source mode = SCART).

42

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.17. Surround Reproduction Modes

9.1.18. Surround Source Modes

Surround Reproduc-

tion Modes

0040

(DPL 3518/19/20)

L

Surround Source

Modes

0041

(DPL 3518/19/20)

H

hex

NORMAL

0000 0000

RESET

00

NOISE

SCART

I2S1

(18/19/20)

0000 0001

0000 0010

0000 0101

0000 0110

01

02

05

06

hex

(20)

PHANTOM

0001 0000

0010 0000

0011 0000

0100 0000

0101 0000

10

20

30

40

50

hex

(18/19/20)

WIDE

I2S2

THREE_CHANNEL

CENTER_OFF

PANORAMA

Select the source to be fed to the surround decoder

block. The NOISE mode selects a built-in noise genera-

tor. If the equalizer is switched on, SCART as source is

no longer valid, i.e. AD input is no longer possible.

The standard mode to reproduce Dolby Pro Logic Sur-

round is NORMAL. All four channels L, C, R, S are in

operation. Low Frequency signals of the C channel are

distributed to the L and R loudspeakers. This enables

the center speaker to be a smaller model than the L and

R speaker. If all three front speakers are identical and

capable of reproducing low bass information, and if

equal power is available in the L, C and R amplifiers,

then it may be beneficial to use the WIDE mode. The

center channel will then contain the full frequency range

signal. The NORMAL and WIDE modes using 4 or 5

loudspeakers give the optimum solution for surround re-

production. Other modes using less loudspeakers

create inferior surround effects.

9.1.19. Surround Source Matrix Modes

Surround Source Ma-

trix (Sound Source)

0041

(DPL 3518/19/20)

L

hex

SOUNDA

0000 0000

RESET

00

hex

SOUNDB

STEREO

MONO

0001 0000

0010 0000

0011 0000

10

20

30

L

hex

Surround Source Ma-

trix (Noise Source)

0041

hex

(DPL 3518/19/20)

If no center speaker is available, the PHANTOM mode

prevents loss of the center information by splitting it up

equally to the L and R speakers.

NOISE_L

NOISE_C

NOISE_R

NOISE_S

1010 0000

1011 0000

1100 0000

1101 0000

a0

b0

hex

If no surround speaker is available the THREE_CHAN-

NEL mode can be used. This mode will confine the

sound to the front speakers.

c0

d0

hex

The CENTER_OFF mode provides a simple way to opti-

mize the manual input balance. While switched off, the

balance control can be adjusted for minimum dialogue

level.

Select the mode of the sound source. Real Dolby Pro

Logic Surround sound can only be displayed in the

STEREO mode. Mono modes such as SOUNDA,

SOUNDB and MONO will not produce a surround effect

unless the surround decoder mode is switched to

EFFECT.

Surround sound can be reproduced to a certain extent

even with two loudspeakers. The PANORAMA mode

mixes all four surround decoder outputs to the L and R

output channel without any loss of information.

If the equalizer is switched on, the SCART source mode

is no longer valid.

The modes NOISE_L, NOISE_C, NOISE_R and

NOISE_S create an input signal to the decoder that will

result in a noise signal on the L, C, R and S outputs.

Micronas

43

DPL 35xxA

PRELIMINARY DATA SHEET

9.1.20. Surround Delay

Surround Delay

Increases the perceived basewidth of the reproduced

left and right front channels. Recommended value: 50%

= 40 . In contrast to the spatial effect for channel 1, the

hex

0042

(DPL 3518/19/20)

H

hex

surround spatial effect is optimized for Dolby Pro Logic.

The difference is most obvious for the Phantom and

Panorama reproduction modes.

5 ms (lowest)

6 ms

0000 0101

0000 0110

05

hex

06

9.1.24. Panorama Sound Effect

31 ms (highest)

0001 1111

1F

hex

Panorama Sound

Effect

0045

(DPL 3518/19/20)

H

hex

For Dolby Pro Logic designs, only 20 ms fixed or

15–30 ms variable delay must be used.

OFF

0000 0000

RESET

00

hex

9.1.21. Surround Manual Input Balance

0.8%

0000 0001

01

Surround Manual

Input Balance

0043

(DPL 3518/19/20)

H

hex

99.2%

100%

0111 1110

0111 1111

7E

7F

hex

Left muted, Right 100%

Left 0.8%, Right 100%

0111 1111

0111 1110

7F

hex

7E

01

Strength of the surround effect in PANORAMA mode.

Recommended value: 66% = 54 . Delay should be set

tothemax. value:31msandreverberationshouldbeoff.

This register only has the correct effect in PANORAMA

mode (Surround Reproduction Mode is set to PANORA-

MA). It must be zero (OFF) in non PANORAMA modes)

Left 99.2%, Right 100%

Left 100%, Right 100%

0000 0001

hex

0000 0000

RESET

00

Left 100%, Right 99.2%

1111 1111

FF

hex

Left 100%, Right 0.8%

Left 100%, Right muted

1000 0010

1000 0001

82

81

hex

9.1.25. Surround Reverberation

hex

Surround

Reverberation

0046

(DPL 3518/19/20)

H

hex

In automatic balance mode this register has no effect.

OFF

0000 0000

RESET

00

9.1.22. Surround Input Balance Mode

hex

Surround Input

Balance Mode

0043

(DPL 3518/19/20)

L

0.8%

0000 0001

01

hex

99.2%

100%

0111 1110

0111 1111

7E

7F

hex

Automatic balance

Manual balance

0000 0000

0100 0000

00

hex

40

Automatic balance mode is recommended.

Reverberation will be added to the surround channel.

Due to the maximally implemented 31 ms only dry

sounds will be affected. The effect will be rather weak for

sourcematerialwhichalreadycontainsacertainamount

of reverberation. It can be used to create a more rever-

berant sound when using the EFFECT decoder mode

for mono signals. Recommended value: not more than

9.1.23. Surround Spatial Effect

Surround Spatial

Effect

0044

(DPL 3518/19/20)

H

hex

OFF

0000 0000

RESET

00

66%= 54 . Delay should be set to the maximumvalue:

31 ms.

hex

0.8%

0000 0001

01

99.2%

100%

0111 1110

1111 1111

7E

7F

hex

44

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

9.2. Summary of Readable Registers

All readable registers are 16-bit wide. Transmissions via

2

I C-bus have to take place in 16-bit words.

These registers are not writable.

Name

Address

High/Low

H

Output Range

Digital input level register

Quasi peak readout left

Quasi peak readout right

0018

0019

001a

single bits

hex

H&L

[00

... 7FFF

]

16-bit two’s complement

hex

H&L

hex

9.2.1. Quasi Peak Detector

9.2.2. Digital Input Level Register

Used to read back the input level of certain digital input

pins:

Quasi peak readout

left

0019

(DPL 3518/19/20)

H+L

hex

Quasi peak readout

right

001a

(DPL 3518/19/20)

H+L

hex

Bit

D_CTR_IN

D_CTR_IO1

D_CTR_IO0

X––– ––––

–X–– ––––

––X– ––––

Quasi peak readout

[0 ... 7FFF

values are 16-bit two’s

complement

]

hex

The quasi peak readout register can be used to read out

the quasi peak level of any input source, in order to ad-

just all inputs to the same normal listening level. The re-

fresh rate is 32 kHz. The feature is based on a filter time

constant:

Ahigh levelonthe inputpins gives a“1”, alowlevelgives

“0”.

attack-time: 1.3 ms

decay-time: 37 ms

Micronas

45

DPL 35xxA

PRELIMINARY DATA SHEET

10. Further Explanations and Application Hints

10.1. Overview of the Surround Decoder and Repro-

ductions Modes

The register 0040hex H ”surround decoder modes”

define which method should be used to create a

multichannel signal out of an stereo input.

The register 0040hex L ”sound reproduction modes”

define which method should be used to mix the

multichannel output to the actually used loudspeakers

(or final output channels).

L

Lt

R

Surround

Reproduction

Mode

Surround

Decoder

Mode

R

C

S

R

C

R

C

S

Rt

S

All outputs used

No center speaker used

No surround speaker used

Only Left/Right speaker used

Fig. 10–1: Surround Decoder and Reproduction Mode Principle

The PANORAMA sound reproduction mode mixes all 4

channels into 2 output channels. Fig 10–2 gives the in-

ternal processing of this mode. All other reproduction

modes are according to the Dolby specification.

L

L’

L’’

R

C

R’

R’’

2

–3dB

S

L

S

PANORAMA

Sound

Algorithm

R

Panorama Sound Effect

(Register 45

)

hex

Fig. 10–2: Surround Spatial Effect and PANORAMA Sound Processing

46

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

10.2. Useful Combinations of the Surround Decod-

er and Reproduction Modes

10.2.2. Useful Combinations with the PASSIVE Sur-

round Decoder Mode

The passive surround decoder (which is defined by

Dolby) uses no center speaker! In no cases, a center

speaker should be connected to the output (or if, the

center speaker should be muted). Only two modes are

useful (all other modes give inferior results!):

In principle, the ”surround decoder modes” and the

”sound reproduction modes” modes could be

orthogonal (all ”surround decoder modes” can be used

with all ”sound reproduction modes”) but there are some

combinations that do not create ”good” sound.

WIDE

L, R and S speakers used. Do not

connect speakers to the center

channel

10.2.1. Useful Combinations with the ADAPTIVE

Surround Decoder Mode

PANORAMA

only L and R speaker used (creates

a surround like effect with only 2

speakers, result is inferior to the

combination with the ADAPTIVE

mode)

NORMAL

all output channels used, L and R

speakers have better bass

capability

WIDE

all output channels used, L,R and C

speakers all have good

bass capability

10.2.3. Useful Combinations with the EFFECT Sur-

round Decoder Mode

PHANTOM

no center speaker used (note: the

center output channel C is muted

automatically)

The EFFECT surround decoder mode is intended for

MONO sources. MONO sources give no surround effect

in the ADAPTIVE and PASSIVE modes. In order to give

the customer means to create surround sound even in

presence of mono signals, the EFFECT mode can be

used.

THREE_CHANNEL

no surround speaker used

(creates a STEREO like effect, but

with better center stage

reproduction) (Note: the surround

output channel is not automatically

muted)

NORMAL

all output channels used, L and R

speakers have better bass

capability. The center channel may

need a lower volume to compensate

for the dominant center.

CENTER_OFF

PANORAMA

systems with center speaker, only

for adjustment of manual input

balance. (Note: Dolby suggests to

use the adaptive input balance

always)

WIDE

all output channels used, L,R and C

speakers all have better bass

capability. The center channel may

need a lower volume to compensate

for the dominant center.

only L and R speaker used (creates

a surround like effect with only 2

speakers) (Note: the left and right

output channels L&R are not muted

automatically)

or:

no center speaker used (no center

speaker connected)

PANORAMA

only L and R speaker used (creates

a surround like effect with only 2

speakers, result is inferior to the

combination with the ADAPTIVE

mode)

Micronas

47

DPL 35xxA

PRELIMINARY DATA SHEET

10.3. Further Notes

With higher prescale values lower input sensitivities can

be accommodated. A higher input sensitivity is not pos-

sible, because at least 15 dB headroom is required for

every input according to the Dolby specifications.

1. The ADAPTIVE mode seems to get better results

compared to the PASSIVE in all cases, even for source

signals that are not encoded in Dolby Surround.

A full-scale left only input (2 Vrms) will produce a full-

scale left only output with 0 dB volume. The typical out-

put levels are 1.37 Vrms for channel 1 and 2 and

2. Using the EFFECT mode for mono signals creates a

very dry surround signal. This can be somewhat

compensatedwiththeSurroundReverberationRegister

(0046hex H).

2

1.9 Vrms for SCART outputs. The I S-channels yield

0 dBFS. Thesameholdstrueforrightonlysignals. Afull-

scale input level on both inputs (Lin=Rin=2 Vrms) will

give a center only output with maximum level. The typi-

cal output levels are 1.37 Vrms for channel 1 and 2 out-

3. For small speaker spacing the perceived basewidth

can be increased by using Surround Spatial Effect

(Register 0044hex H). This also works best for the

ADAPTIVE mode.

2

putsand1.9VrmsforSCARToutputs. TheI S-channels

yield 0 dBFS. A full-scale input level on both inputs (but

Lin and Rin with inverted phases) will give a surround-

only signal with maximum level.

4. Surround Spatial Effect can be used in combination

with PANORAMA. This also works best for the

ADAPTIVE mode.

For reproducing Dolby Pro Logic according to its specifi-

cations, the center and surround outputs must be ampli-

fied by 3 dB with respect to the L and R output signals.

This can be done in two ways:

5. The adaptive input balance is recommended for the

ADAPTIVE mode. In PASSIVE or EFFECT mode, the

input balance can be switched to manual in middle

position.

1. By implementing 3 dB more amplification for center

and surround loudspeaker outputs.

6. In PANORAMA mode, the strength of the surround

signal can be controlled by the Panorama Sound Effect

Register (0045hex H). In other modes, this register has

no effect and should be set to 0.

2. By always selecting volume for L and R 3 dB lower

than center and surround. Method 1 is preferable, as

method 2 lowers the achievable SNR for left and right

signals by 3 dB.

10.4. Input and Output Levels for Dolby Pro Logic

Operation

10.5. Dolby Qualification

The analog inputs are able to accept 2 Vrms input level

without overloading any stage before the volume con-

trol. The nominal input level (input sensitivity) is 350 mV.

This gives 15 dB headroom. The scart prescale value

Qualification testing for Dolby approval requires the de-

vice to be switched to plain Dolby Pro Logic without any

sound effects. Effects, such as PANORAMA, Surround

Spatial Effect or Surround Reverberations must be

switched off.

should be set to 0 dB (25 ).

dec

2

I S-inputs should have the same headroom when enter-

ing the DPL. The nominal input level is –15 dBFS. The

The surround decoder must be switched to ADAPTIVE.

highest possible input level of 0 dBFS is accepted with-

2

out internal overflow. The I S-prescale value should be

For Dolby Pro Logic designs only 20 ms fixed or

set to 0 dB (25 ).

15–30 ms variable delay must be used.

dec

48

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

10.6. Phase Relationship of Outputs

The analog output signals channel 1, channel 2 and

SCART2 of the DPL all have the same phases. The user

does not need to correct output phases when using

these analog outputs directly. The SCART1 output has

opposite phase.

2

Using the I S-outputs for other DSPs or D/A converters,

care has to be taken to adjust for the correct phase. If the

attached coprocessor is one of the MSP family, the fol-

lowing schematics help to determine the phase relation-

ship:

2

I Sin I Sout

Channel1 & 2,

Main, Aux

DFP

SCART2

SCART1

–

MONO

SCART1 & 2 & 3

–

SCART1 & 2

Fig. 10–3: Phase Diagram of DPL, MSPB, MSPC (>c6) and MSPD

2

I Sin I Sout

–

Channel1 & 2,

Main, Aux

–

DFP

SCART2

SCART1

MONO

SCART1 & 2 & 3

–

SCART1 & 2

Fig. 10–4: Phase Diagram of MSPC (xc6)

Micronas

49

DPL 35xxA

PRELIMINARY DATA SHEET

10.7. Minimum Control Transmissions for the

DPL 3520A

16, 131, 0, 38

! 131=83hex = MODE_REG:

! dig_out, i2s and audioclock out set

! to tristate, i2s master, i2s sony

! mode

The following listing contains the minimum data transfer

for setting up the DPL in stand alone mode. The file

resets registers even though these registers are already

reset by the hardware reset. This is to ensure, that even

without external reset, the original state is restored.

Note: the trap is the transmission to register

56dez=38hex. This register must not be 0 (which it is

after reset). This is mentioned in the data sheet on page

39 (9.1.8. channel source modes). The format of the list-

ing is the same as the log format of our demo software

(without the comments). You can create a file with these

transmission codes and execute it via our demo soft-

ware. Use the I2C –> Init from File – menu.

18, 0, 103, 0

18, 1, 0, 0

18, 2, 0, 0

18, 3, 0, 0

18, 4, 0, 0

18, 5, 0, 0

18, 6, 103, 0

18, 7, 103, 1

18, 8, 3, 32

! volume channel1 = –12dB

! balance channel1 = 0dB/0dB

! bass channel1 = 0dB

! treble channel1 = 0dB

! loudness channel1 = 0dB

! spat effect channel1 off

! volume channel2 = –12dB

! volume SCART = –12dB

! channel1 source = DOLBYLR,

! matrix = STEREO

! channel2 source = DOLBYCS,

! matrix = STEREO

! SCART source = DOLBYCSUB,

! matrix = SOUNDB (=subwoofer)

! prescale SCART = 29dez

! ACB: SCART2_OUT,

18, 9, 4, 32

18, 10, 7, 16

18, 13, 29, 0

18, 19, 12, 0

! SCART1_OUT=DA_SCART

! (=subwoofer), DFPin=SCART1_IN

! (=Lt, Rt input to SCART1)

! Tone control = bass/treble

! balance channel2 = 0dB/0dB

! bass channel2 = 0dB

18, 32, 0, 0

18, 48, 0, 0

18, 49, 0, 0

18, 50, 0, 0

18, 51, 0, 0

18, 56, 2, 0

! treble channel2 = 0dB

! loudness channel2 = 0dB

! I2S2 source = SCART !

! although this is not used it must be

! set !

18, 64, 0, 0

! surround decoder mode =

! ADAPTIVE, Surround

! reproduction mode = NORMAL

! Surround Source = SCART,

! surround source mode = STEREO

! surround delay = 24ms

! surround input balance mode =

! AUTOMATIC

18, 65, 2, 32

18, 66, 18, 0

18, 67, 0, 0

18, 68, 0, 0

18, 69, 0, 0

18, 70, 0, 0

! surround spatial effect = off

! panorama sound effect = off

! surround reverberation = off

format:

<16|18>, <adr>, <high byte>, <low byte>

16 means: write transmission to MODEREG

18 means: write transmission to DFP

all values in decimal

50

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

11. Application Principle of the DPL 3520A

L or L+C or PSL

2

R or R+C or PSR

SCART1

2

Line

Inputs

DPL 3520A

SCART2

SCART3

C

S

2

Dolby Pro Logic

Line

Outputs

2

SCART

Fig. 11–1: Standard configuration

Micronas

51

DPL 35xxA

PRELIMINARY DATA SHEET

12. Application Circuit Diagram of the DPL 3520A

18.432 MHz Clock

0:10 pF

>1nF

10

µF

+8.0 V

-

+

3.3 100

µF nF

18.432

MHz

+

10 µF 10 µF

+

Alternative circuit for external clock input

28 (55) MONO_IN

52 (30) ASG3

330 nF

1µF

AHVSS

DACC1_L (29) 56

30 (53) SC1_IN_R

31 (52) SC1_IN_L

330 nF

1µF

1 nF

DACC1_R (28) 57

32 (51) ASG1

1µF

33 (50) SC2_IN_R

330 nF

DACC2_L (26) 59

DACC2_R (25) 60

34 (49) SC2_IN_L

35 (48) ASG2

1 nF

36 (47) SC3_IN_R

37 (46) SC3_IN_L

330 nF

DPL 3520A

100Ω

22 µF

SC1_OUT_L (37) 47

SC1_OUT_R (36) 48

5V

+

100Ω

11 (7) STANDBY Q

12 (6) ADR_SEL

22 µF

5V

+

DVSS

100Ω

22 µF

SC2_OUT_L (34) 50

SC2_OUT_R (33) 51

+

DVSS

2

9 (9) I C-CL

100Ω

2

8 (10) I C-DA

+

D_CTR_IN (64) 19

D_CTR_IO0 (5) 13

D_CTR_IO1 (4) 14

AUD_CL_OUT (1) 18

2

6 (12) I S_WS

2

7 (11) I S_CL

2

4 (14) I S_DA_IN1

2

65 (20) I S_DA_IN2

2

5 (13) I S_DA_OUT

2

64 (21) I S_DA_OUT2

TESTEN (61) 22

DVSS

100

nF

100

nF

100

nF

+

10 µF

5 V

8.0 V

Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package.

52

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

13. Dolby Pro Logic Processor Family

13.1. DPL 3518A: Basic Dolby Pro Logic Coprocessor for the MSP Family

DPL 3518A

Dolby Pro Logic

2

I S

Tuner

L or L+C or PSL

R or R+C or PSR

MSP 3400 C

or

MSP 3410 D

C

S

2

SCART1

2

Line

Inputs

SCART2

SCART3

SCART1

SCART2

Line

Outputs

Fig. 13–1: Standard configuration

2

I S_DA_OUT1

I S_DA_OUT2 I S_CL

2

I S_WS

I S_DA_IN1

I S_DA_IN2

2

I S-Interface

2

I S1/2L/R

DSP

Fig. 13–2: Architecture of the DPL 3518A

2

Prescale

I S1L

2

I S1

2

I S1

Channel

Matrix

Output

2

I S1R

2

I S-Bus

Inputs

2

Prescale

I S2L

2

I S2L

2

I S2

I S2R

2

I S2

Channel

Matrix

Output

2

I S2R

L/L + C/PSL

Quasi peak readout L

Quasi-Peak

Channel

Matrix

Quasi-Peak

Detector

R/R + C/PSR

Dolby

Pro Logic

Quasi peak readout R

Surround

Source

Matrix

C

Passive

Effect

2

SR

I S1L

Internal signal lines

Noise

Generator

C

SUB

Fig. 13–3: Baseband processing of the DPL 3518A

Micronas

53

DPL 35xxA

PRELIMINARY DATA SHEET

13.2. DPL 3519A: Advanced Dolby Pro Logic Coprocessor for the MSP Family

C

SUB

DPL 3519A

S

L

Dolby Pro Logic

R

2

I S

Tuner

L or L+C or PSL

R or R+C or PSR

MSP 3410 B

or

MSP 3400 B

or

MSP 3400 C

or

MSP 3410 D

Headphone

2

SCART1

2

Line

Inputs

SCART2

SCART3

SCART1

SCART2

Line

Outputs

Fig. 13–4: Standard configuration

2

I S_DA_OUT1 I S_DA_OUT2 I S_CL

2

I S_WS

I S_DA_IN1

I S_DA_IN2

2

I S-Interface

2

I S1/2L/R I S1/2L/R

FM1

OUT1_L

OUT1_R

OUT1_L

OUT1_R

D/A

Channel 1

Output

D/A

OUT2_L

OUT2_R

OUT2_L

OUT2_R

Mono MONO_IN

Channel 2

Output

SC1_IN_L

SCART1

DSP

SC1_IN_R

D/A

SCART_L

SCART_R

SC1_OUT_L

SCART 1

SC1_OUT_R

SC2_IN_L

SCART2

SC2_IN_R

SC2_OUT_L

SC2_OUT_R

SCART 2

SC3_IN_L

SCART3

SCART Switching Facilities

SC3_IN_R

Fig. 13–5: Architecture of the DPL 3519A

54

Micronas

DPL 35xxA

PRELIMINARY DATA SHEET

Equalizer or

Bass/Treble

Loudness

Volume

Balance

OUT1L

Spatial Effects

Channel1

Matrix

Channel 1

Output

OUT1R

Bass,Treble

Loudness

Spatial Effects

2

I S1L

Prescale

2

I S1R

OUT2L

2

Volume

Balance

I S-Bus

Channel 2

Output

Bass,Treble

Loudness

Channel2

Matrix

Inputs

2

I S2L

OUT2R

2

I S2R

SCARTL

SCART

Volume

SCART

Channel

Matrix

Output

SCARTR

L/L + C/PSL

2

I S1L

2

I S1

2

I S1

Channel

Matrix

R/R + C/PSR

Output

2

Dolby

Pro Logic

or

Passive

or

I S1R

C

Surround

Source

Matrix

SR

Effect

2

I S2L

2

I S2

2

I S2

Noise

Generator

C

Channel

Output

Matrix

2

SUB

I S2R

Quasi peak readout L

Quasi peak readout R

Quasi-

Peak

Channel

Matrix

Quasi-Peak

Detector

2

I S1L

Internal signal lines

Fig. 13–6: Baseband processing of the DPL 3519A

Micronas

55

DPL 35xxA

PRELIMINARY DATA SHEET

14. IC Failure Report

15. Data Sheet History

1. Preliminary Data Sheet: “DPL 3520A, DPL 3519A,

DPL 3518A Dolby Pro Logic Processor Family”, July 31,

1997, 6251-423-1PD. First release of the preliminary

data sheet.

Three errors have been detected on the A1 versions of

following ICs: DPL 3518A, DPL 3519A, and DPL 3520A.

2

1. The register for the I S2 channel source does not

work. Instead of using register 38 , register 0c

(Quasi peak detector source) is used. So, the I S2

hex

2

source is always the same as the source for the Qua-

si peak detector. Nevertheless 38

must be pro-

hex

grammed to a value other than the reset state of

00 (See note in chapter 9.1.8.).

hex

2. If the DPL is used with manual input balance, the low-

er 4 bits in register 43 must be zero. Only the upper

4 bits can be programmed.

3. The fast mute feature (registers 00hex and 06hex)

does not work. Use normal mute instead.

These errors will be corrected with version A2.

All information and data contained in this data sheet are without any

commitment, are not to be considered as an offer for conclusion of a

contract, nor shall they be construed as to create any liability. Any new

issueofthisdatasheetinvalidatespreviousissues.Productavailability

and delivery are exclusively subject to our respective order confirma-

tion form; the same applies to orders based on development samples

delivered. By this publication, Micronas GmbH does not assume re-

sponsibility for patent infringements or other rights of third parties

which may result from its use.

Further, Micronas GmbH reserves the right to revise this publication

and to make changes to its content, at any time, without obligation to

notify any person or entity of such revisions or changes.

No part of this publication may be reproduced, photocopied, stored on

a retrieval system, or transmitted without the express written consent

of Micronas GmbH.

Micronas GmbH

Hans-Bunte-Strasse 19

D-79108 Freiburg (Germany)

P.O. Box 840

D-79008 Freiburg (Germany)

Tel. +49-761-517-0

Fax +49-761-517-2174

E-mail: docservice@micronas.com

Internet: www.micronas.com

Printed in Germany

Order No. 6251-423-1PD

56

Micronas

型号:	DPL2018D
生命周期：	Obsolete
IHS 制造商：	MICA MICROWAVE
Reach Compliance Code：	unknown
风险等级：	5.84
射频/微波设备类型：	LIMITER
Base Number Matches：	1

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