DRV594VFPR原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

±3−A HIGH−EFFICIENCY PWM POWER DRIVER

FEATURES

DESCRIPTION

The DRV593 and DRV594 are high-efficiency,

high-current power amplifiers ideal for driving a wide

variety of thermoelectric cooler elements in systems

powered from 2.8 V to 5.5 V. The operation of the device

requires only one inductor and capacitor for the output

filter, saving significant printed-circuit board area.

Pulse-width modulation (PWM) operation and low output

stage on-resistance significantly decrease power

dissipation in the amplifier.

D

Operation Reduces Output Filter Size and

Cost by 50% Compared to DRV591

D

±3-A Maximum Output Current

Low Supply Voltage Operation: 2.8 V to 5.5 V

High Efficiency Generates Less Heat

Overcurrent and Thermal Protection

Fault Indicators for Overcurrent, Thermal and

Undervoltage Conditions

The DRV593 and DRV594 are internally protected against

thermal and current overloads. Logic-level fault indicators

signal when the junction temperature has reached

approximately 115°C to allow for system-level shutdown

before the amplifier’s internal thermal shutdown circuitry

activates. The fault indicators also signal when an

overcurrent event has occurred. If the overcurrent circuitry

is tripped, the devices automatically reset (see application

information section for more details).

D

Two Selectable Switching Frequencies

Internal or External Clock Sync

PWM Scheme Optimized for EMI

9×9 mm PowerPAD Quad Flatpack Package

APPLICATIONS

The PWM switching frequency may be set to 500 kHz or

100 kHz depending on system requirements. To eliminate

external components, the gain is fixed at 2.3 V/V for the

DRV593. For the DRV594, the gain is fixed at 14.5 V/V.

D

Thermoelectric Cooler (TEC) Driver

Laser Diode Biasing

V

DD

1 µF

10 µF

10 µH

1 µF

To TEC or Laser

PWM

AVDD

Diode Anode

AGND (Connect to PowerPAD)

PGND

H/C

120 kΩ

ROSC

COSC

220 pF

DC Control

Voltage

DRV593

DRV594

AREF

1 µF

IN+

10 µF

1 kΩ

IN-

SHUTDOWN

Shutdown Control

FAULT1

FAULT0

To TEC or Laser

Diode Cathode

1 µF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

Copyright  2002, Texas Instruments Incorporated

DRV593

DRV594

www.ti.com

SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

ORDERING INFORMATION

handledwith appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage.

PowerPAD QUAD FLATPACK

(VFP)

T

A

(1)

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

DRV593VFP

-40°C to 85°C

(1)

DRV594VFP

(1)

This package is available taped and reeled. To order this

packaging option, add an R suffix to the part number (e.g.,

DRV593VFPR or DRV594VFPR).

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

DRV593, DRV594

Supply voltage, AVDD, PVDD

-0.3 V to 5.5 V

Input voltage, V

-0.3 V to V + 0.3 V

I

DD

Output current, I (FAULT0, FAULT1)

1 mA

See Dissipation Rating Table

-40°C to 85°C

O

Continuous total power dissipation

Operating free-air temperature range, T

A

Operating junction temperature range, T

-40°C to 150°C

J

Storage temperature range, T

-65°C to 165°C

stg

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Supply voltage, AVDD PVDD

2.8

2

5.5

V

,

High-level input voltage, V

FREQ, INT/EXT, SHUTDOWN, COSC

IH

Low-level input voltage, V

0.8

85

V

IL

Operating free-air temperature, T

- 40

°C

A

PACKAGE DISSIPATION RATINGS

(1)

Θ

JA

Θ

JC

T = 25°C

A

PACKAGE

(°C/W)

POWER RATING

VFP

29.4

1.2

4.1 W

(1)

This data was taken using 2 oz trace and copper pad that is

soldered directly to a JEDEC standard 4-layer 3 in × 3 in PCB.

2

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER

TEST CONDITIONS

= 0 A

MIN

TYP

MAX

100

1

UNIT

mV

µA

|V

|

Output offset voltage (measured differentially)

High-level input current

V = V /2,

I

O

14

OO

I

DD

|I

|

IH

V

DD

V

DD

= 5.5V,

V = V

I DD

|I |

IL

Low-level input current

= 5.5V,

V = 0 V

I

1

µA

V_n

Integrated output noise voltage

f = <1 Hz to 10 kHz

40

µV

V

= 5 V

1.2

3.8

2.1

DD

V

Common-mode voltage range

V

ICM

v

= 3.3 V

DRV593

DRV594

2.1

2.3

14.5

60

2.6

V/V

kHz

A

Closed-loop voltage gain

Full power bandwidth

13.7

15.3

I

= ±1 A, r

= ±3 A, r

= 65 mΩ,

V = 5 V

DD

4.87

4.61

60

O

ds(on)

V

Voltage output (measured differentially)

V

O

= 65 mΩ, V = 5 V

O

ds(on)

DD

High side

Low side

High side

Low side

25

95

V

= 5 V, I = 4 A,

O

DD

mΩ

T = 25°C

65

A

r

Drain-source on-state resistance

Maximum continuous current output

DS(on)

80

140

V

= 3.3 V, I = 4 A,

O

DD

mΩ

A

T = 25°C

90

A

3

Status flag output pins (FAULT0, FAULT1)

Fault active (open drain output)

Sinking 200 µA

0.1

V

For 500 kHz operation

For 100 kHz operation

225

45

250

50

4

300

55

12

8

External clock frequency range

Quiescent current

kHz

mA

V

DD

V

DD

V

DD

= 5 V, No load or filter

= 3.3 V, No load or filter

I

q

2.5

40

2

Quiescent current in shutdown mode

Output resistance in shutdown

Power-on threshold

= 5 V, SHUTDOWN = 0.8 V

0

1

80

µA

kΩ

V

q(SD)

SHUTDOWN = 0.8 V

1.7

1.6

2.8

2.6

Power-off threshold

V

Thermal trip point

FAULT0 active

Power off

115

150

100

°C

kΩ

Thermal shutdown

Z

I

Input impedance (IN+, IN-)

3

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

PIN ASSIGNMENTS

VFP PACKAGE

(TOP VIEW)

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

AVDD

AGND

ROSC

PWM

24

23

PGND

22 PGND

21

20

19

18

17

COSC

AREF

PGND

H/C

PowerPAD

IN+

IN-

SHUTDOWN

9 10 11 12 13 14 15 16

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

AGND

NO.

2

Analog ground

AREF

AVDD

COSC

5

1

4

O

I

Connect 1 µF capacitor to ground for AREF voltage filtering

Analog power supply

I

Connect capacitor to ground to set oscillation frequency (220 pF for 500 kHz, 1 nF for 100 kHz) when the internal

oscillator is selected; connect clock signal when an external oscillator is used

FAULT0

FAULT1

10

9

O

Fault flag 0, low when active open drain output (see application information)

Fault flag 1, low when active open drain output (see application information)

Selects 500 kHz switching frequency when a TTL logic low is applied to this terminal; selects 100 kHz switching

frequency when a TTL logic high is applied

FREQ

IN-

32

7

I

Negative differential input

Positive differential input

IN+

6

INT/EXT

31

Selects the internal oscillator when a TTL logic high is applied to this terminal; selects the use of an external oscil-

lator when a TTL logic low is applied to this terminal

H/C

14, 15,

16, 17

O

Direction control output for heat and cool modes (4 pins)

PWM output for voltage magnitude (4 pins)

High-current ground (6 pins)

PWM

PGND

24, 25,

26, 27

18, 19,

20, 21,

22, 23

PVDD

11, 12,

13, 28,

29, 30

I

High-current power supply (6 pins)

ROSC

3

I

Connect 120-kΩ resistor to AGND to set oscillation frequency (either 500 kHz or 100 kHz). Not needed if an

external clock is used.

SHUTDOWN

8

Places the amplifier in shutdown mode when a TTL logic low is applied to this terminal; places the amplifier

in normal operation when a TTL logic high is applied

4

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

AVDD

2.3 × R (DRV593)

PVDD

H/C

+

_

14.5 x R (DRV594)

Gate

Drive

R

IN-

_

+

_

+

PGND

PVDD

_

+

IN+

+

_

PWM

Gate

2.3 × R (DRV593)

14.5 x R (DRV594)

Drive

PGND

SHUTDOWN

INT/EXT

Start-Up

Protection

Logic

OC

Detect

TTL

Biases

and

References

Input

Ramp

Generator

Buffer

FREQ

COSC

ROSC

AREF

Thermal

VDDok

FAULT0

FAULT1

5

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

Efficiency

vs Load resistance

vs Supply voltage

vs Free-air temperature

vs Supply voltage

vs Frequency

2, 3

4

5

r

Drain-source on-state resistance

DS(on)

6

I

q

Supply current

7

PSRR

Power supply rejection ratio

Closed loop response

8, 9

12, 13

14

vs Output voltage

I

Maximum output current

Input offset voltage

O

vs Ambient temperature

Common-mode input voltage

15

V

16, 17

IO

TEST SETUP FOR GRAPHS

The LC output filter used in Figures 2, 3, 8, and 9 is shown below.

L1

PWM

C1

R

L

H/C

L1 = 10 µH (part number: CDRH104R, manufacturer: Sumida)

C1 = 10 µF (part number: ECJ-4YB1C106K, manufacturer: Panasonic)

Figure 1. LC Output Filter

6

DRV593

DRV594

www.ti.com

SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

TYPICAL CHARACTERISTICS

EFFICIENCY

vs

EFFICIENCY

vs

LOAD RESISTANCE

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

P

= 2 W

O

P

= 1 W

O

P

= 0.5 W

P

O

= 1 W

O

P

= 0.5 W

O

P

O

= 0.25 W

V

f

= 3.3 V

= 500 kHz

V

= 5 V

= 500 kHz

DD

f

S

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

R

L

- Load Resistance - Ω

R

L

- Load Resistance - Ω

Figure 2

Figure 3

DRAIN-SOURCE ON-STATE RESISTANCE

vs

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

300

250

300

V

I

= 5 V

= 1 A

I

= 1 A

DD

O

T = 25°C

O

A

VFP Package

250

200

150

Total

200

150

100

Total

Low Side

High Side

Low Side

High Side

100

50

0

50

0

-40

-15

10

35

60

85

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

T

A

- Free-Air Temperature - °C

V

DD

- Supply Voltage - V

Figure 4

Figure 5

7

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

TYPICAL CHARACTERISTICS

DRAIN-SOURCE ON-STATE RESISTANCE

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

vs

FREE-AIR TEMPERATURE

300

250

200

150

100

10

9

V

I

= 3.3 V

= 1 A

DD

No Load

O

VFP Package

8

Total

7

6

5

Low Side

4

3

High Side

2

50

0

1

0

-40

-15

10

35

60

85

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

T

A

- Free-Air Temperature - °C

V

DD

- Supply Voltage - V

Figure 6

Figure 7

POWER SUPPLY REJECTION RATIO

vs

FREQUENCY

-20

-30

-40

-50

-60

-20

-30

-40

-50

-60

V

= 5 V

= 500 kHz

DD

V

= 3.3 V

DD

f

S

f = 500 kHz

S

R = 1 Ω

L

R = 1 Ω

L

V

ripple

= 100 mV

pp

V

= 100 mV

ripple pp

-70

-80

-70

-80

10

100

1k

10k

100k

10

100

1k

10k

100k

f - Frequency - Hz

Figure 8

Figure 9

8

DRV593

DRV594

www.ti.com

SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

TYPICAL CHARACTERISTICS

DRV594

DRV593

CLOSED LOOP RESPONSE

4

10

16

14

12

10

Gain

0

Phase

Gain

0

-10

-20

3

2

-10

-20

-30

-40

-50

-60

-70

Phase

-30

-40

-50

-60

8

6

4

2

0

1

0

V

= 5 V

DD

V

= 5 V

DD

No Load

-70

-80

No Load

10

100

1 k

10 k

100 k

10

100

1k

10k

100k

f - Frequency - Hz

Figure 10

Figure 11

DRV593

DRV594

CLOSED LOOP RESPONSE

10

4

16

14

12

10

8

10

Gain

0

Phase

-10

-20

3

2

-10

-20

-30

-40

-50

-60

-70

Phase

Gain

-30

-40

-50

6

1

0

4

-60

-70

-80

V

= 3.3 V

DD

V

= 3.3 V

DD

2

No Load

0

10

100

1 k

10 k

100 k

10

100

1k

10k

100k

f - Frequency - Hz

Figure 12

Figure 13

9

DRV593

DRV594

www.ti.com

SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

TYPICAL CHARACTERISTICS

MAXIMUM OUTPUT CURRENT

vs

OUTPUT VOLTAGE

AMBIENT TEMPERATURE

3.5

3

3.5

3

T = 100°C

J

2.5

2

T = 85°C

2.5

2

J

T = 125°C

J

1.5

1

1.5

1

V

= 5 V

0.5

0

DD

0.5

0

T = 25°C

A

T ≤ 125°C

J

VFP Package

0

1

2

3

4

5

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80

V

O

- Output Voltage - V

T

A

- Ambient Temperature - °C

Figure 14

Figure 15

INPUT OFFSET VOLTAGE

vs

INPUT OFFSET VOLTAGE

vs

COMMON-MODE INPUT VOLTAGE

10

9

20

19

18

17

16

15

14

13

12

11

10

V

= 5 V

V

= 3.3 V

DD

No Load

8

7

6

5

4

3

2

1

0

1.2

1.6

2.0

2.4

2.8

3.2

3.6 3.8

1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1

V

IC

- Common-Mode Input Voltage - V

V

IC

- Common-Mode Input Voltage - V

Figure 16

Figure 17

10

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

APPLICATION INFORMATION

PULSE-WIDTH MODULATION SCHEME FOR DRV593 AND DRV594

The pulse-width modulation scheme implemented in the DRV593 and DRV594 eliminates one-half of the full output

filter previously required for PWM drivers. The DRV593 and DRV594 require only one inductor and capacitor for the

output filter. The H/C outputs determine the direction of the current and do not switch back and forth. The PWM outputs

switch to produce a voltage across the load that is proportional to the input control voltage.

COOLING MODE

Figure 18 shows the DRV593 and DRV594 in cooling mode. The H/C outputs (pins 14-17) are at ground and the

PWM outputs (pins 24-27) create a voltage across the load that is proportional to the input voltage.

The differential voltage across the load is determined using equation (1) and the duty cycle using equation (2). The

differential voltage is defined as the voltage measured after the filter on the PWM output relative to the H/C output.

V

+ D V

Load

DD

(1)

ǒ

A V

v

_IN–Ǔ

–V

IN)

V

D +

DD

(2)

where

D

duty cycle of the PWM signal

A_v

Gain of DRV593/594 (DRV593: 2.3 V/V, DRV594: 14.5 V/V)

Positive input terminal of the DRV593/594

Negative input terminal of the DRV593/594

Power supply voltage

V_IN+

V_IN-

V_DD

For example, a 50% duty cycle, shown in Figure 18, results in 2.5 V across the load for V_DD= 5 V.

VDD

PWM

0

VDD

H/C

0

VDD

VDD/2

Load

Voltage

0

Figure 18. Cooling Mode

11

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

HEATING MODE

Figure 19 shows the DRV593 and DRV594 in heating mode. The H/C output is at VDD and the PWM output is

proportional to the voltage across the load.

The differential voltage across the load is determined using equation (3). The variables are the same as used

previously for equations (1) and (2).

V

+ –(1–D) V

Load

DD

(3)

For example, a 50% duty cycle, shown in Figure 19, results in -2.5 V across the load for VDD = 5 V. The differential

voltage across the load is defined as the voltage measured after the filter on the PWM output relative to the H/C output.

VDD

PWM

0

VDD

H/C

0

Load

0

Voltage

-VDD/2

-VDD

Figure 19. Heating Mode

12

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DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

HEAT/COOL TRANSITION

As the device transitions from cooling to heating, the duty cycle of the PWM outputs decrease to a small value and

the H/C outputs remains at ground. When the device transitions to heating mode, the H/C outputs change from zero

volts to VDD and the PWM outputs change to a high duty cycle. The direction of the current flow is reversed, but a

low voltage is maintained across the load. The duty cycle decreases as the part is put further into heating mode to

drive more current through the load. Figure 20 illustrates the transition from cooling to heating.

ZERO-CROSSING REGION

When the differential output voltage is near zero, the control logic in the DRV593 and DRV594 causes the outputs

to change between heating and cooling modes. There are two possible states for the PWM and H/C outputs to obtain

zero volts differentially: both outputs can be at VDD or both outputs can be at ground. Therefore, random noise causes

the outputs to change between the two states when the two input voltages are equal. The outputs switch from zero

to VDD, although not at a fixed frequency rate. Some of the pulses may be wider than others, but the two outputs

(PWM and H/C) track each other to provide zero differential voltage. These uneven pulse widths can increase the

switching noise during the zero-crossing condition.

To avoid this phenomenon, hysteresis should be implemented in the control loop to prevent the device from operating

within this region. Although planning for operation during the zero-crossing is important, the normal operating points

for the DRV593 and DRV594 are outside of this region. For laser temperature/wavelength regulation, the zero volts

output condition is only a concern when the laser temperature or wavelength, relative to the ambient temperature,

requires no heating or cooling from the TEC element.

VDD

IN +

IN -

0

VDD

PWM

0

VDD

H/C

0

Figure 20. Transition From Cooling to Heating

13

DRV593

DRV594

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SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

V

DD

1 µF

10 µF

10 µH

1 µF

To TEC or Laser

Diode Anode

AVDD

PWM

PGND

H/C

AGND (Connect to PowerPAD)

120 kΩ

ROSC

COSC

220 pF

DC Control

Voltage

DRV593

DRV594

AREF

1 µF

IN+

1 kΩ

10 µF

IN-

SHUTDOWN

Shutdown Control

FAULT1

FAULT0

To TEC or Laser

Diode Cathode

1 µF

Figure 21. Typical Application Circuit

OUTPUT FILTER CONSIDERATIONS

TEC element manufacturers provide electrical specifications for maximum dc current and maximum output

voltage for each particular element. The maximum ripple current, however, is typically only recommended to

be less than 10% with no reference to the frequency components of the current. The maximum temperature

differential across the element, which decreases as ripple current increases, may be calculated with the

following equation:

(4)

1

DT +

DT

max

2

ǒ

Ǔ

1 ) N

where

∆T = actual temperature differential

∆T = maximum temperature differential (specified by manufacturer)

max

N = ratio of ripple current to dc current

According to this relationship, a 10% ripple current reduces the maximum temperature differential by 1%. An

LC network may be used to filter the current flowing to the TEC to reduce the amount of ripple and, more

importantly, protect the rest of the system from any electromagnetic interference (EMI).

FILTER COMPONENT SELECTION

The LC filter, which may be designed from two different perspectives, both described below, helps estimate the

overall performance of the system. The filter should be designed for the worst-case conditions during operation,

which is typically when the differential output is at 50% duty cycle. The following section serves as a starting

point for the design, and any calculations should be confirmed with a prototype circuit in the lab.

Any filter should always be placed as close as possible to the DRV593 and DRV594 to reduce EMI.

L

PWM

C

R

TEC

H/C

Figure 22. LC Output Filter

14

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LC FILTER IN THE FREQUENCY DOMAIN

The transfer function for a second-order low-pass filter (Figures 17 and 18) is shown in equation (5):

1

(5)

H

(jw) +

LP

2

jw

w

_–ǒ Ǔ

w

1

Q

)

) 1

w

0

1

w

+

0

Ǹ

LC

Q + quality factor

w + DRV593 or DRV594 switching frequency

For the DRV593 and DRV594, the differential output switching frequency is typically selected to be 500 kHz.

The resonant frequency for the filter is typically chosen to be at least one order of magnitude lower than the

switching frequency. equation (5) may then be simplified to give the following magnitude equation (6). These

equations assume the use of the filter in Figure 22.

(6)

f

s

Ť_HLPŤ_dB

_{+ –40 log}ǒ Ǔ

Ǹ

f

o

1

f

+

o

2p LC

f + 500 kHz (DRV593 or DRV594 switching frequency)

s

If L=10 µH and C=10 µF, the cutoff frequency is 15.9 kHz, which corresponds to –60 dB of attenuation at the

500 kHz switching frequency. For VDD = 5 V, the amount of ripple voltage at the TEC element is approximately

5 mV.

The average TEC element has a resistance of 1.5 Ω, so the ripple current through the TEC is approximately

3.4 mA. At the 3-A maximum output current of the DRV593 and DRV594, this 5.4 mA corresponds to 0.11%

ripple current, causing less than 0.0001% reduction of the maximum temperature differential of the TEC

element (see equation 4).

LC FILTER IN THE TIME DOMAIN

The ripple current of an inductor may be calculated using equation (7):

(7)

ǒ_{V –V}Ǔ_DT

s

O

TEC

L

DI

+

L

D + duty cycle (0.5 worst case)

T + 1ńf + 1ń500 kHz

s

For V = 5 V, V

= 2.5 V, and L = 10 µH, the inductor ripple current is 250 mA. To calculate how much of that

O

TEC

ripple current flows through the TEC element, however, the properties of the filter capacitor must be considered.

For relatively small capacitors (less than 22 µF) with very low equivalent series resistance (ESR, less than

10 mΩ), such as ceramic capacitors, the following equation (8) may be used to estimate the ripple voltage on

the capacitor due to the change in charge:

2

(8)

f

2

o

p

ǒ

Ǔ

_1–Dǒ Ǔ _VTEC

DV

+

C

2

f

s

D + duty cycle

f + 500 kHz

s

1

f

+

o

Ǹ

2p LC

15

DRV593

DRV594

www.ti.com

SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

For L = 10 µH and C = 10 µF, the cutoff frequency, f , is 15.9 kHz. For worst case duty cycle of 0.5 and

o

V

=2.5 V, the ripple voltage on the capacitors is 6.2 mV. The ripple current may be calculated by dividing the

TEC

ripple voltage by the TEC resistance of 1.5 Ω, resulting in a ripple current through the TEC element of 4.1 mA.

Note that this is similar to the value calculated using the frequency domain approach.

For larger capacitors (greater than 22 µF) with relatively high ESR (greater than 100 mΩ), such as electrolytic

capacitors, the ESR dominates over the charging/discharging of the capacitor. The following simple

equation (9) may be used to estimate the ripple voltage:

(9)

DV + DI R

L

C

ESR

DI + inductor ripple current

L

R

+ filter capacitor ESR

ESR

For a 100 µF electrolytic capacitor, an ESR of 0.1 Ω is common. If the 10 µH inductor is used, delivering 250 mA

of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times

that of the 10 µF ceramic capacitor, as ceramic capacitors typically have negligible ESR.

SWITCHING FREQUENCY CONFIGURATION: OSCILLATOR COMPONENTS R_OSCAND C_OSC

AND FREQ OPERATION

The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. The

frequency may be either 500 kHz or 100 kHz by selecting the proper capacitor value and by holding the FREQ

pin either low (500 kHz) or high (100 kHz). Table 1 shows the values required and FREQ pin configuration for

each switching frequency.

Table 1. Frequency Configuration Options

SWITCHING FREQUENCY

500 kHz

R

C

FREQ

OSC

120 kΩ

220 pF

1 nF

LOW (GND)

HIGH (VDD)

100 kHz

For proper operation, the resistor R

should have 1% tolerance while capacitor C

should be a ceramic

OSC

type with 10% tolerance. Both components should be grounded to AGND, which should be connected to PGND

at a single point, typically where power and ground are physically connected to the printed-circuit board.

EXTERNAL CLOCKING OPERATION

To synchronize the switching to an external clock signal, pull the INT/EXT terminal low, and drive the clock signal

into the COSC terminal. This clock signal must be from 10% to 90% duty cycle and meet the voltage

requirements specified in the electrical specifications table. Since the DRV593 and DRV594 include an internal

frequency doubler, the external clock signal must be approximately 250 kHz. Deviations from the 250 kHz clock

frequency are allowed and are specified in the electrical characteristic table. The resistor connected from ROSC

to ground may be omitted from the circuit in this mode of operation—the source is disconnected internally.

INPUT CONFIGURATION: DIFFERENTIAL AND SINGLE-ENDED

If a differential input is used, it should be biased around the midrail of the DRV593 or DRV594 and must not

exceed the common-mode input range of the input stage (see the operating characteristics at the beginning

of the data sheet).

The most common configuration employs a single-ended input. The unused input should be tied to V /2, which

DD

may be simply accomplished with a resistive voltage divider. For the best performance, the resistor values

chosen should be at least 100 times lower than the input resistance of the DRV593 or DRV594. This prevents

the bias voltage at the unused input from shifting when the signal input is applied. A small ceramic capacitor

should also be placed from the input to ground to filter noise and keep the voltage stable. An op amp configured

as a buffer may also be used to set the voltage at the unused input.

16

DRV593

DRV594

www.ti.com

SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

FIXED INTERNAL GAIN

The differential output voltage may be calculated using equation (10):

(10)

_vǒ_V

_IN–Ǔ

V

+ V

–V

OUT) OUT–

+ A

–V

IN)

O

A is the voltage gain, which is fixed internally at 2.3 V/V for DRV593 and 14.5 V/V for DRV594. The maximum

V

and minimum ratings are provided in the electrical specification table at the beginning of the data sheet.

POWER SUPPLY DECOUPLING

To reduce the effects of high-frequency transients or spikes, a small ceramic capacitor, typically 0.1 µF to 1 µF,

should be placed as close to each set of PVDD pins of the DRV593 and DRV594 as possible. For bulk

decoupling, a 10 µF to 100 µF tantalum or aluminum electrolytic capacitor should be placed relatively close to

the DRV593 and DRV594.

AREF CAPACITOR

The AREF terminal is the output of an internal mid-rail voltage regulator used for the onboard oscillator and ramp

generator. The regulator may not be used to provide power to any additional circuitry. A 1 µF ceramic capacitor

must be connected from AREF to AGND for stability (see oscillator components above for AGND connection

information).

SHUTDOWN OPERATION

The DRV593 and DRV594 include a shutdown mode that disables the outputs and places the device in a low

supply current state. The SHUTDOWN pin may be controlled with a TTL logic signal. When SHUTDOWN is

held high, the device operates normally. When SHUTDOWN is held low, the device is placed in shutdown. The

SHUTDOWN pin must not be left floating. If the shutdown feature is unused, the pin may be connected to VDD.

FAULT REPORTING

The DRV593 and DRV594 include circuitry to sense three faults:

D Overcurrent

D Undervoltage

D Overtemperature

These three fault conditions are decoded via the FAULT1 and FAULT0 terminals. Internally, these are

open-drain outputs, so an external pullup resistor of 5 kΩ or greater is required.

Table 2. Fault Indicators

FAULT1

FAULT0

0

1

0

1

0

1

Overcurrent

Undervoltage

Overtemperature

Normal operation

The overcurrent fault is reported when the output current exceeds four amps. As soon as the condition is

sensed, the overcurrent fault is set and the outputs go into a high-impedance state for approximately 3 µs to

5 µs (500 kHz operation). After 3 µs to 5 µs, the outputs are re-enabled. If the overcurrent condition has ended,

the fault is cleared and the device resumes normal operation. If the overcurrent condition still exists, the above

sequence repeats.

The undervoltage fault is reported when the operating voltage is reduced below 2.8 V. This fault is not latched,

so as soon as the power supply recovers, the fault is cleared and normal operation resumes. During the

undervoltage condition, the outputs go into a high-impedance state to prevent overdissipation due to increased

r

.

DS(on)

17

DRV593

DRV594

www.ti.com

SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

The overtemperature fault is reported when the junction temperature exceeds 115°C. The device continues

operating normally until the junction temperature reaches 150°C, at which point the IC is disabled to prevent

permanent damage from occurring. The system’s controller must reduce the power demanded from the

DRV593 or DRV594 once the overtemperature flag is set, or else the device switches off when it reaches 150°C.

This fault is not latched; once the junction temperature drops below 115°C, the fault is cleared, and normal

operation resumes.

POWER DISSIPATION AND MAXIMUM AMBIENT TEMPERATURE

Though the DRV593 and DRV594 are much more efficient than traditional linear solutions, the power drop

across the on-resistance of the output transistors does generate some heat in the package, which may be

calculated as shown in equation (11):

₊ǒ_IOUTǓ²

(11)

P

r

DISS

DS(on), total

For example, at the maximum output current of 3 A through a total on-resistance of 130 mΩ (at T = 25°C),

J

the power dissipated in the package is 1.17 W.

Calculate the maximum ambient temperature using equation (12):

(12)

_*ǒ_θ

JA

_DISSǓ

T

+ T

P

A

J

PRINTED-CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS

Since the DRV593 and DRV594 are high-current switching devices, a few guidelines for the layout of the

printed-circuit board (PCB) must be considered:

1. Grounding. Analog ground (AGND) and power ground (PGND) must be kept separated, ideally back to

where the power supply physically connects to the PCB, minimally back to the bulk decoupling capacitor

(10 µF ceramic minimum). Furthermore, the PowerPAD ground connection should be made to AGND, not

PGND. Ground planes are not recommended for AGND or PGND, traces should be used to route the

currents. Wide traces (100 mils) should be used for PGND while narrow traces (15 mils) should be used

for AGND.

2. Power supply decoupling. A small 0.1 µF to 1 µF ceramic capacitor should be placed as close to each

set of PVDD pins as possible, connecting from PVDD to PGND. A 0.1 µF to 1 µF ceramic capacitor should

also be placed close to the AVDD pin, connecting from AVDD to AGND. A bulk decoupling capacitor of at

least 10 µF, preferably ceramic, should be placed close to the DRV593 or DRV594, from PVDD to PGND.

If power supply lines are long, additional decoupling may be required.

3. Power and output traces. The power and output traces should be sized to handle the desired maximum

output current. The output traces should be kept as short as possible to reduce EMI, i.e., the output filter

should be placed as close to the DRV593 or DRV594 outputs as possible.

4. PowerPAD. The DRV593 and DRV594 in the Quad Flatpack package use TI’s PowerPAD technology to

enhance the thermal performance. The PowerPAD is physically connected to the substrate of the DRV593

and DRV594 silicon, which is connected to AGND. The PowerPAD ground connection should therefore be

kept separate from PGND as described above. The pad underneath the AGND pin may be connected

underneath the device to the PowerPAD ground connection for ease of routing. For additional information

on PowerPAD PCB layout, refer to the PowerPAD Thermally Enhanced Package application note,

SLMA002.

5. Thermal performance. For proper thermal performance, the PowerPAD must be soldered down to a

thermal land, as described in the PowerPAD Thermally Enhanced Package application note, SLMA002.

In addition, at high current levels (greater than 2 A) or high ambient temperatures (greater than 25°C), an

internal plane may be used for heat sinking. The vias under the PowerPAD should make a solid connection,

and the plane should not be tied to ground except through the PowerPAD connection, as described above.

18

DRV593

DRV594

www.ti.com

SLOS401A - SEPTEMBER 2002 REVISED - OCTOBER 2002

MECHANICAL DATA

VFP (S-PQFP-G32)

PowerPAD PLASTIC QUAD FLATPACK

0,45

M

0,22

0,80

0,30

24

17

25

16

Thermal Pad

(See Note D)

32

9

0,13 NOM

1

8

5,60 TYP

7,20

SQ

6,80

Gage Plane

9,20

SQ

8,80

0,25

0,05 MIN

0°-7°

1,45

1,35

0,75

0,45

Seating Plane

0,10

1,60 MAX

4200791/A04/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MS-026

PowerPAD is a trademark of Texas Instruments.

19

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

DRV593VFP

DRV593VFPR

DRV594VFP

DRV594VFPR

ACTIVE

HLQFP

VFP

32

250

1000

250

None

CU NIPDAU Level-1-235C-UNLIM

VFP

1000

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Use of such information may require a license from a third party under the patents or other intellectual property

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Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	DRV594VFPR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	QFP
包装说明：	HLQFP, QFP32,.35SQ,32
针数：	32
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	0.82
内置保护：	OVER CURRENT; THERMAL; UNDER VOLTAGE
驱动器位数：	1
输入特性：	DIFFERENTIAL
接口集成电路类型：	HB BASED PERIPHERAL DRIVER WITH PWM
JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e4
长度：	7 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	32
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出电流流向：	SOURCE AND SINK
最大输出电流：	3 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	HLQFP
封装等效代码：	QFP32,.35SQ,32
封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, LOW PROFILE
峰值回流温度（摄氏度）：	260
电源：	3/5 V
认证状态：	Not Qualified
座面最大高度：	1.6 mm
子类别：	Peripheral Drivers
最大供电电压：	5.5 V
最小供电电压：	2.8 V
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm
Base Number Matches：	1

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