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产品型号DRV632PWR的概述

DRV632PWR 芯片概述 DRV632PWR 是一款高效的放大器驱动芯片，专门用于音频和高电流负载的驱动。随着消费电子产品的广泛应用，音频放大器需求不断增加，DRV632PWR 应运而生，旨在提供高性能、高效率的解决方案。该芯片的设计可以满足多种应用需求，包括扬声器驱动、耳机放大器以及其他音频相关应用。厂家信息 DRV632PWR 由德州仪器（Texas Instruments，TI）生产。德州仪器是一家全球领先的半导体设计和制造公司，提供一系列用于工业、汽车、通信和个人电子设备的电源管理和信号链解决方案。该公司以其高质量和创新能力而闻名，是电源管理和音频集成电路领域的市场先行者。包装与封装 DRV632PWR 通常采用 HTQFP-32 封装，这种封装方式能够有效降低引脚间的电容和感应，减少高频干扰。这种封装结构也便于焊接，提高了生产效率。此外，HTQFP 封装的尺寸为 7...

产品型号DRV632PWR的Datasheet PDF文件预览

DRV632

www.ti.com

SLOS681A –JANUARY 2011–REVISED JULY 2013

DirectPath™, 2-VRMS Audio Line Driver With Adjustable Gain

Check for Samples: DRV632

FEATURES

DESCRIPTION

The DRV632 is a 2-V_RMSpop-free stereo line driver

designed to allow the removal of the output dc-

blocking capacitors for reduced component count and

cost. The device is ideal for single-supply electronics

where size and cost are critical design parameters.

•

Stereo DirectPath™ Audio Line Driver

2 Vrms Into 10 kΩ With 3.3-V Supply

–

•

Low THD+N < 0.01% at 2 Vrms Into 10 kΩ

High SNR, >90 dB

•

600-Ω Output Load Compliant

Designed

using

TI’s

patented

DirectPath™

technology, The DRV632 is capable of driving 2 V_RMS

into a 10-kΩ load with 3.3-V supply voltage. The

device has differential inputs and uses external gain-

setting resistors to support a gain range of ±1 V/V to

±10 V/V, and gain can be configured individually for

each channel. Line outputs have ±8-kV IEC ESD

protection, requiring just a simple resistor-capacitor

ESD protection circuit. The DRV632 has built-in

active-mute control for pop-free audio on/off control.

The DRV632 has an external undervoltage detector

that mutes the output when the power supply is

removed, ensuring a pop-free shutdown.

Differential Input and Single-Ended Output

Adjustable Gain by External Gain-Setting

Resistors

•

Low DC Offset, <1 mV

Ground-Referenced Outputs Eliminate DC-

Blocking Capacitors

–

Reduce Board Area

Reduce Component Cost

Improve THD+N Performance

No Degradation of Low-Frequency

Response Due to Output Capacitors

Using the DRV632 in audio products can reduce

component count considerably compared to

traditional methods of generating a 2-V_RMSoutput.

The DRV632 does not require a power supply greater

than 3.3 V to generate its 5.6-V_ppoutput, nor does it

•

Short-Circuit Protection

Click- and Pop-Reduction Circuitry

External Undervoltage Mute

require

a split-rail power supply. The DRV632

Active Mute Control for Pop-Free Audio On/Off

Control

integrates its own charge pump to generate a

negative supply rail that provides a clean, pop-free

ground-biased 2-V_RMSoutput.

•

Space-Saving TSSOP Package

The DRV632 is available in a 14-pin TSSOP.

APPLICATIONS

•

Set-Top Boxes

Blu-ray Disc™, DVD Players

LCD and PDP TV

Mini/Micro Combo Systems

Sound Cards

Laptops

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DirectPath, FilterPro are trademarks of Texas Instruments.

Blu-ray Disc is a trademark of Blu-ray Disc Association.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DRV632

SLOS681A –JANUARY 2011–REVISED JULY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE

DESCRIPTION

–40°C to 85°C

DRV632PW

14-Pin

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range

VALUE

–0.3 to 4

UNIT

Supply voltage, VDD to GND

V_I

Input voltage

V_SS– 0.3 to VDD + 0.3

600

R_L

Minimum load impedance – line outputs – OUTL, OUTR

Mute to GND, UVP to GND

Ω

–0.3 to VDD + 0.3

–40 to 150

T_J

Maximum operating junction temperature range

Storage temperature range

°C

T_stg

–40 to 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

DRV632

THERMAL METRIC⁽¹⁾

14 PINS

130

UNIT

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

°C/W

θ_JCtop

θ_JB

ψ_JT

3.6

ψ_JB

θ_JCbot

n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

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SLOS681A –JANUARY 2011–REVISED JULY 2013

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

UNIT

VDD

R_L

Supply voltage

DC supply voltage

3.3

3.6

Load impedance

0.6

kΩ

V_IL

V_IH

T_A

Low-level input voltage

High-level input voltage

Operating free-air temperature

Mute

% of VDD

°C

–40

ELECTRICAL CHARACTERISTICS

T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX UNIT

|V_OS

Output offset voltage

VDD = 3.3 V

0.5

PSRR Power-supply rejection ratio

V_OH

V_OL

High-level output voltage

Low-level output voltage

VDD = 3.3 V

3.1

–3.05

V_{UVP_}External UVP detect voltage

1.25

V_{UVP_}External UVP detect hysteresis current

µA

EX_HYS

TERESI

f_CP

Charge pump switching frequency

High-level input current, Mute

Low-level input current, Mute

200

300

400

kHz

µA

|I_IH

VDD = 3.3 V, V_IH= VDD

|I_IL|

VDD = 3.3 V, V_IL= 0 V

µA

VDD = 3.3 V, no load, Mute = VDD

VDD = 3.3 V, no load, Mute = GND, disabled

I_DD

Supply current

OPERATING CHARACTERISTICS

VDD = 3.3 V, R_DL= 10 kΩ, R_FB= 30 kΩ, R_IN= 15 kΩ, T_A= 25°C, Charge pump: C_P= 1 µF (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

V_O

Output voltage, outputs in phase

THD+N = 1%, VDD = 3.3 V, f = 1 kHz, R_L= 10 kΩ

2.4

V_rms

THD+N

SNR

DNR

V_N

Total harmonic distortion plus noise V_O= 2 V_RMS, f = 1 kHz

0.002%

Signal-to-noise ratio⁽¹⁾

A-weighted

Mute = GND

105

μV

mΩ

Dynamic range

Noise voltage

Z_O

Output Impedance when muted

110

Input-to-output attenuation when

muted

Crosstalk—L to R, R to L

Current limit

V_O= 1 V_rms

–110

I_LIMIT

(1) SNR is calculated relative to 2-Vrms output.

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SLOS681A –JANUARY 2011–REVISED JULY 2013

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PW PACKAGE

(TOP VIEW)

+INR

–INR

14 +INL

–INL

OUTL

UVP

GND

VDD

OUTR

GND

Mute

VSS

External

Under-

Voltage

Detector

Charge Pump

PIN FUNCTIONS

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

I/O

Charge-pump flying capacitor negative connection

Charge-pump flying capacitor positive connection

Ground

GND

–INL

+INL

–INR

+INR

Mute

OUTL

OUTR

UVP

4, 10

Left-channel OPAMP negative input

Left-channel OPAMP positive input

Right-channel OPAMP negative input

Right-channel OPAMP positive input

Mute, active-low

Left-channel OPAMP output

Right-channel OPAMP output

Undervoltage protection, internal pullup; unconnected if UVP function is unused.

VDD

VSS

Positive supply

Supply voltage

(1) I = input, O = output, P = power

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SLOS681A –JANUARY 2011–REVISED JULY 2013

FUNCTIONAL BLOCK DIAGRAM

+INL

–INL

OUTL

GND

Mute

VSS

+INR

–INR

OUTR

UVP

GND

VDD

Line

Driver

Line

Driver

Click and Pop

Suppression

Short-Circuit

Protection

Bias

Circuitry

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SLOS681A –JANUARY 2011–REVISED JULY 2013

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TYPICAL CHARACTERISTICS

VDD = 3.3 V , T_A= 25°C, C_(PUMP)= C_(VSS)= 1 µF , C_IN= 2.2 µF, R_IN= 15 kΩ, R_fb= 30 kΩ, R_OUT= 32 Ω, C_OUT= 1 nF (unless

otherwise noted)

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT VOLTAGE

Active Filter

Gain = 2V/V

R_L= 10 kΩ

Active Filter

Gain = 2V/V

R_L= 600Ω

0.1

0.01

0.001

0.0001

0.01

0.001

0.0001

100 Hz

1 kHz

10 kHz

100 Hz

1 kHz

10 kHz

0.1

Output Voltage (V)

Figure 1.

Figure 2.

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

Active Filter

Gain = 2V/V

R_L= 10 kΩ

Ch1 1 Vrms

Ch1 2 Vrms

Active Filter

Gain = 2V/V

R_L= 600 Ω

Ch1 1 Vrms

Ch1 2 Vrms

0.1

0.01

0.001

0.0001

0.01

0.001

0.0001

100

10k 20k

100

10k 20k

Frequency (Hz)

Figure 3.

Figure 4.

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SLOS681A –JANUARY 2011–REVISED JULY 2013

TYPICAL CHARACTERISTICS (continued)

VDD = 3.3 V , T_A= 25°C, C_(PUMP)= C_(VSS)= 1 µF , C_IN= 2.2 µF, R_IN= 15 kΩ, R_fb= 30 kΩ, R_OUT= 32 Ω, C_OUT= 1 nF (unless

otherwise noted)

CROSSTALK

FREQUENCY

R_L= 10 kΩ

V_O= 1 Vrms

V_REF= 1 V

Left to Right

Right to Left

−20

−40

−60

−80

−100

−120

−140

100

10k 20k

Frequency (Hz)

Figure 5.

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SLOS681A –JANUARY 2011–REVISED JULY 2013

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APPLICATION INFORMATION

LINE DRIVER AMPLIFIERS

Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 6 illustrates

the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often

large in value. The line load (typical resistive values of 600 Ω to 10 kΩ) combines with the dc blocking capacitors

to form a high-pass filter. Equation 1 shows the relationship between the load impedance (R_L), the capacitor

(C_O), and the cutoff frequency (f_C).

f_c=

2pR_LC_O

(1)

C_Ocan be determined using Equation 2, where the load impedance and the cutoff frequency are known.

C_O

2pR_Lf_c

(2)

If f_Cis low, the capacitor must then have a large value because the load resistance is small. Large capacitance

values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,

increase cost of assembly, and can reduce the fidelity of the audio output signal.

9 V–12 V

Conventional Solution

VDD

VDD/2

Mute Circuit

–

Output

OPAMP

GND

Enable

3.3 V

DirectPath

VDD

DRV632 Solution

Mute Circuit

–

Output

GND

DRV632

VSS

Enable

Figure 6. Conventional and DirectPath Line Drivers

The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to

provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the

IC, the device operates in what is effectively a split-supply mode. The output voltages are now centered at zero

volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop

reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram

and waveform of Figure 6 illustrate the ground-referenced line-driver architecture. This is the architecture of the

DRV632.

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SLOS681A –JANUARY 2011–REVISED JULY 2013

CHARGE-PUMP FLYING CAPACITOR AND PVSS CAPACITOR

The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.

The PVSS capacitor must be at least equal to the charge-pump capacitor in order to allow maximum charge

transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical. Capacitor values that are

smaller than 1 μF can be used, but the maximum output voltage may be reduced and the device may not

operate to specifications. If the DRV632 is used in highly noise-sensitive circuits, it is recommended to add a

small LC filter on the VDD connection.

DECOUPLING CAPACITORS

The DRV632 is a DirectPath line-driver amplifier that requires adequate power supply decoupling to ensure that

the noise and total harmonic distortion (THD) are low. A good, low equivalent-series-resistance (ESR) ceramic

capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this decoupling

capacitor close to the DRV632 is important for the performance of the amplifier. For filtering lower-frequency

noise signals, a 10-μF or greater capacitor placed near the audio power amplifier would also help, but it is not

required in most applications because of the high PSRR of this device.

GAIN-SETTING RESISTOR RANGES

The gain-setting resistors, R_INand R_fb, must be chosen so that noise, stability, and input capacitor size of the

DRV632 are kept within acceptable limits. Voltage gain is defined as R_fbdivided by R_IN.

Selecting values that are too low demands a large input ac-coupling capacitor, C_IN. Selecting values that are too

high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different inverting-

input gain settings.

Table 1. Recommended Resistor Values

GAIN

–1 V/V

INPUT RESISTOR VALUE, R_IN

FEEDBACK RESISTOR VALUE, R_fb

10 kΩ

8.2 kΩ

15 kΩ

4.7 kΩ

10 kΩ

12 kΩ

30 kΩ

47 kΩ

–1.5 V/V

–2 V/V

–10 V/V

USING THE DRV632 AS A SECOND-ORDER FILTER

Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible

with the DRV632, as it can be used like a standard operational amplifier. Several filter topologies can be

implemented, both single-ended and differential. In Figure 7, multi-feedback (MFB) with differential input and

single-ended input are shown.

An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from

the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum.

The component values can be calculated with the help of the TI FilterPro™ program available on the TI Web site

at:

http://focus.ti.com/docs/toolsw/folders/print/filterpro.html.

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SLOS681A –JANUARY 2011–REVISED JULY 2013

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Differential Input

Inverting Input

–IN

+IN

–IN

–

DRV632

–

DRV632

Figure 7. Second-Order Active Low-Pass Filter

The resistor values should have a low value for obtaining low noise, but should also have a high enough value to

get a small-size ac-coupling capacitor. With the proposed values of R1 = 15 kΩ, R2 = 30 kΩ, and R3 = 43 kΩ, a

dynamic range (DYR) of 106 dB can be achieved with a 1-μF input ac-coupling capacitor.

INPUT-BLOCKING CAPACITORS

DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the

DRV632. These capacitors block the dc portion of the audio source and allow the DRV632 inputs to be properly

biased to provide maximum performance.

These capacitors form a high-pass filter with the input resistor, R_IN. The cutoff frequency is calculated using

Equation 3. For this calculation, the capacitance used is the input-blocking capacitor, and the resistance is the

input resistor chosen from Table 1; then the frequency and/or capacitance can be determined when one of the

two values is given.

It is recommended to use electrolytic capacitors or high-voltage-rated capacitors as input blocking capacitors to

ensure minimal variation in capacitance with input voltages. Such variation in capacitance with input voltages is

commonly seen in ceramic capacitors and can increase low-frequency audio distortion.

f_cIN

C_IN=

2pR_INC_IN

2pf_cINR_IN

(3)

DRV632 UVP OPERATION

The shutdown threshold at the UVP pin is 1.25 V. The customer must use a resistor divider to obtain the

shutdown threshold and hysteresis desired for a particular application. The customer-selected thresholds can be

determined as follows:

EXTERNAL UNDERVOLTAGE DETECTION

External undervoltage detection can be used to mute/shut down the DRV632 before an input device can

generate a pop.

The shutdown threshold at the UVP pin is 1.25 V. The user selects a resistor divider to obtain the shutdown

threshold and hysteresis for the specific application. The thresholds can be determined as follows:

V_UVP= (1.25 – 6 μA × R3) × (R1 + R2) / R2

Hysteresis = 5 μA × R3 × (R1 + R2) / R2

For example, to obtain V_UVP= 3.8 V and 1-V hysteresis, we can use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ.

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SLOS681A –JANUARY 2011–REVISED JULY 2013

VSUP_MO

UVP

LAYOUT RECOMMENDATIONS

A proposed layout for the DRV632 can be seen in the DRV632EVM User's Guide, and the Gerber files can be

downloaded from http://www.ti.com. To access this information, open the DRV632 product folder and look in the

Tools and Software folder.

GAIN-SETTING RESISTORS

The gain-setting resistors, R_INand R_fb, must be placed close to pins 13 and 17, respectively, to minimize

capacitive loading on these input pins and to ensure maximum stability of the DRV632. For the recommended

PCB layout, see the DRV632EVM User's Guide.

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APPLICATION CIRCUIT

RIGHT

– INPUT

LEFT

– INPUT

DRV632

+INR

–INR

+INL

Line

Driver

Line

Driver

–INL

OUTL

UVP

GND

VDD

OUTR

GND

RIGHT OUTPUT

LEFT OUTPUT

Click and Pop

Suppression

Short-Circuit

Protection

R11

3.3-V Supply

R12

Bias

Circuitry

VSS

1mF

Linear

Low-Dropout

Regulator

1mF

System Supply

10mF

R1 = 15 kΩ, R2 = 30 kΩ, R3 = 43 kΩ, C1 = 47 pF, C2 = 180 pF

Differential-input, single-ended output, second-order filter

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SLOS681A –JANUARY 2011–REVISED JULY 2013

REVISION HISTORY

Changes from Original (January 2011) to Revision A

Page

•

Deleted min value for SNR and DNR in OPERATING CHARACTERISTICS table ............................................................. 3

Changed description of UVP in PIN FUNCTIONS table ....................................................................................................... 4

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PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

DRV632PW

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

TSSOP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

DRV632

DRV632PWR

ACTIVE

2000

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

-40 to 85

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DRV632PWR

TSSOP

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 14

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

DRV632PWR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

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