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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • DRV8302DCAR
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • DRV8302DCAR图
  • 集好芯城

     该会员已使用本站13年以上
  • DRV8302DCAR 现货库存
  • 数量25474 
  • 厂家TI(德州仪器) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • DRV8302DCAR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • DRV8302DCAR 现货库存
  • 数量5000 
  • 厂家TI 
  • 封装HTSSOP5 
  • 批号23+ 
  • 全新原装,欢迎查询
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • DRV8302DCAR图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • DRV8302DCAR 现货库存
  • 数量23100 
  • 厂家TI 
  • 封装N/A 
  • 批号21+ 
  • 全新原装有现货库存--价格有优势
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • DRV8302DCAR图
  • 深圳德田科技有限公司

     该会员已使用本站7年以上
  • DRV8302DCAR 现货库存
  • 数量9000 
  • 厂家原厂原装 
  • 封装NA 
  • 批号22+ 
  • 原装现货质量保证,可出样品可开税票
  • QQ:229754250QQ:229754250 复制
  • 0755-83254070 QQ:229754250
  • DRV8302DCAR图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • DRV8302DCAR 现货库存
  • 数量2000 
  • 厂家TI 
  • 封装HTSSOP (DCA) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • DRV8302DCAR图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • DRV8302DCAR
  • 数量5000 
  • 厂家TI/德州仪器 
  • 封装HTSSOP56 
  • 批号21+ 
  • 原厂原包装,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • DRV8302DCAR图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • DRV8302DCAR
  • 数量5000 
  • 厂家TI 
  • 封装HTSSOP5 
  • 批号23+ 
  • 原装正品长期供货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • DRV8302DCAR图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • DRV8302DCAR
  • 数量44300 
  • 厂家TI 
  • 封装HTSSOP56 
  • 批号2019+ 
  • TI一级代理专营品牌绝对进口原装假一赔十
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • DRV8302DCAR图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • DRV8302DCAR
  • 数量8571 
  • 厂家TI(德州仪器) 
  • 封装HTSSOP56 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • DRV8302DCAR图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • DRV8302DCAR
  • 数量4825 
  • 厂家TI 
  • 封装56-TFSOP(0.240,6.10mm 宽)裸露焊盘 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • DRV8302DCAR图
  • 集好芯城

     该会员已使用本站13年以上
  • DRV8302DCAR
  • 数量12956 
  • 厂家TI/德州仪器 
  • 封装HTSSOP56 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • DRV8302DCAR图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • DRV8302DCAR
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装贴/插片 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104891 QQ:857273081QQ:1594462451
  • DRV8302DCAR图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • DRV8302DCAR
  • 数量5600 
  • 厂家TI 
  • 封装HTSSOP56 
  • 批号23+ 
  • 100%深圳原装现货库存
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • DRV8302DCAR图
  • 深圳市积美福电子科技有限公司

     该会员已使用本站4年以上
  • DRV8302DCAR
  • 数量2000 
  • 厂家TI/德州仪器 
  • 封装SSOP-56 
  • 批号21+ 
  • 自己原包装现货 实单|原装| 现货
  • QQ:647176908QQ:647176908 复制
    QQ:499959596QQ:499959596 复制
  • 0755-83228296 QQ:647176908QQ:499959596
  • DRV8302DCAR图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • DRV8302DCAR
  • 数量1000 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • DRV8302DCAR图
  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • DRV8302DCAR
  • 数量12245 
  • 厂家TI/德州仪器 
  • 封装HTSSOP56 
  • 批号22+ 
  • 现货,原厂原装假一罚十!
  • QQ:2885659458QQ:2885659458 复制
    QQ:2885657384QQ:2885657384 复制
  • 0755-83952260 QQ:2885659458QQ:2885657384
  • DRV8302DCAR图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • DRV8302DCAR
  • 数量6328 
  • 厂家TI-德州仪器 
  • 封装TSSOP-56 
  • 批号▉▉:2年内 
  • ▉▉¥45一一有问必回一一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • DRV8302DCAR图
  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • DRV8302DCAR
  • 数量3300 
  • 厂家TI/德州仪器 
  • 封装HTSSOP56 
  • 批号2020+ 
  • 全新原装现货,一片也是批量价。
  • QQ:215672808QQ:215672808 复制
  • 0755-83229772 QQ:215672808
  • DRV8302DCAR图
  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • DRV8302DCAR
  • 数量5280 
  • 厂家TI(德州仪器) 
  • 封装HTSSOP-56 
  • 批号23+ 
  • ▉原装正品▉力挺实单可含税可拆样
  • QQ:3003797048QQ:3003797048 复制
    QQ:3003797050QQ:3003797050 复制
  • 0755-82779553 QQ:3003797048QQ:3003797050
  • DRV8302DCAR图
  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
  • DRV8302DCAR
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装标准封装 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 0755-82807802 QQ:528164397QQ:1318502189
  • DRV8302DCAR图
  • 现代芯城(深圳)科技有限公司

     该会员已使用本站15年以上
  • DRV8302DCAR
  • 数量51000 
  • 厂家一级代理 
  • 封装一级代理 
  • 批号一级代理 
  • 一级代理正品采购
  • QQ:3007226851QQ:3007226851 复制
    QQ:3007226849QQ:3007226849 复制
  • 0755-82542579 QQ:3007226851QQ:3007226849
  • DRV8302DCAR图
  • 首天国际(深圳)集团有限公司

     该会员已使用本站17年以上
  • DRV8302DCAR
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装标准封装 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 0755-82807088 QQ:528164397QQ:1318502189
  • DRV8302DCAR图
  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • DRV8302DCAR
  • 数量45000 
  • 厂家TI(德州仪器) 
  • 封装HTSSOP-48 
  • 批号2年内 
  • 原厂渠道 正品保障 长期供应
  • QQ:2355734291QQ:2355734291 复制
  • -0755-88604592 QQ:2355734291
  • DRV8302DCAR.图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • DRV8302DCAR.
  • 数量28500 
  • 厂家TI/德州仪器 
  • 封装 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495
  • DRV8302DCAR图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • DRV8302DCAR
  • 数量5600 
  • 厂家STANSON 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装,原厂渠道,价格优势可谈!
  • QQ:2853992132QQ:2853992132 复制
  • 0755-82570683 QQ:2853992132
  • DRV8302DCAR图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • DRV8302DCAR
  • 数量24566 
  • 厂家TI 
  • 封装 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • DRV8302DCAR图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • DRV8302DCAR
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装HTSSOP-56 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • DRV8302DCAR.图
  • 深圳市创德丰电子有限公司

     该会员已使用本站15年以上
  • DRV8302DCAR.
  • 数量
  • 厂家专营TI/BB 
  • 封装长期收购 
  • 批号N/A 
  • 长期收购此型号/专收TI/BB全系列
  • QQ:2851807192QQ:2851807192 复制
    QQ:2851807191QQ:2851807191 复制
  • 86-755-83226910, QQ:2851807192QQ:2851807191
  • DRV8302DCAR图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • DRV8302DCAR
  • 数量19624 
  • 厂家TI原装原标原盘 
  • 封装HTSSOP56 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507168QQ:2355507168 复制
    QQ:2355507169QQ:2355507169 复制
  • 86-755-83219286 QQ:2355507168QQ:2355507169
  • DRV8302DCAR图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • DRV8302DCAR
  • 数量85000 
  • 厂家TI/德州仪器 
  • 封装HTSSOP56 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • DRV8302DCAR图
  • 深圳市惠诺德电子有限公司

     该会员已使用本站7年以上
  • DRV8302DCAR
  • 数量29500 
  • 厂家Texas Instruments 
  • 封装IC MOTOR DRIVER 8V-60V 56HTSSOP 
  • 批号21+ 
  • 只做原装现货代理
  • QQ:1211267741QQ:1211267741 复制
    QQ:1034782288QQ:1034782288 复制
  • 159-7688-9073 QQ:1211267741QQ:1034782288
  • DRV8302DCAR图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • DRV8302DCAR
  • 数量16851 
  • 厂家TI/德州仪器 
  • 封装TI-2019 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • DRV8302DCAR图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • DRV8302DCAR
  • 数量72282 
  • 厂家TI/德州仪器 
  • 封装N/A 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • DRV8302DCAR图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • DRV8302DCAR
  • 数量8800 
  • 厂家TI 
  • 封装HTSSOP56 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
  • QQ:840638855QQ:840638855 复制
  • 0755-84876394 QQ:840638855
  • DRV8302DCAR图
  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • DRV8302DCAR
  • 数量
  • 厂家TI 
  • 封装原厂指定分销商,有意请来电或QQ洽谈 
  • 批号17+ 
  • QQ:1091796029QQ:1091796029 复制
    QQ:916896414QQ:916896414 复制
  • 0755-82772151 QQ:1091796029QQ:916896414
  • DRV8302DCAR图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • DRV8302DCAR
  • 数量12956 
  • 厂家TI/德州仪器 
  • 封装HTSSOP56 
  • 批号24+ 
  • 原装原厂 现货现卖
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • DRV8302DCAR图
  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • DRV8302DCAR
  • 数量68000 
  • 厂家TI 
  • 封装HTSSOP56 
  • 批号22+ 
  • 全新进口原厂原装,优势现货库存,有需要联系电话:18818596997 QQ:84556259
  • QQ:84556259QQ:84556259 复制
    QQ:783839662QQ:783839662 复制
  • 0755- QQ:84556259QQ:783839662
  • DRV8302DCAR图
  • 深圳市欧赛络斯电子有限公司

     该会员已使用本站5年以上
  • DRV8302DCAR
  • 数量8600 
  • 厂家TI/德州仪器 
  • 封装HTSSOP56 
  • 批号22+ 
  • 全新原装,支持实单,非诚勿扰
  • QQ:1638768328QQ:1638768328 复制
  • 17665218829 QQ:1638768328
  • DRV8302DCAR图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • DRV8302DCAR
  • 数量8800 
  • 厂家TI 
  • 封装HTSSOP56 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
  • QQ:3533288158QQ:3533288158 复制
    QQ:408391813QQ:408391813 复制
  • 0755-84876394 QQ:3533288158QQ:408391813

产品型号DRV8302DCAR的概述

DRV8302DCAR概述 DRV8302DCAR是一款由德州仪器(Texas Instruments)公司设计的高性能三相充电泵驱动器,专为无刷直流电机(BLDC)提供了高效的控制解决方案。这款芯片的设计目标是为电动工具、机器人以及电动车等应用提供强劲且高效的电机驱动能力。DRV8302DCAR集成了多个关键功能,使其在电机控制领域中的表现异常出色。 DRV8302DCAR详细参数 DRV8302DCAR的电气特性涵盖了广泛的工作参数,其中包括: - 电源电压范围:DRV8302DCAR适用于宽电压范围,允许输入电压在10V到60V之间变化,以适应多种应用场合。 - 输出电流:驱动电流可达到2A,可以驱动中型电机,满足大多数工业和消费应用的需求。 - 驱动方式:支持支持N沟道和P沟道MOSFET,提供灵活的选择以优化能量效率和热管理。 - 开关频率:内部开关频率可调,最高可达100k...

产品型号DRV8302DCAR的Datasheet PDF文件预览

DRV8302  
www.ti.com  
SLES267 AUGUST 2011  
Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator  
Hardware Controlled  
Check for Samples: DRV8302  
1
FEATURES  
DESCRIPTION  
The DRV8302 is a gate driver IC for three phase  
motor drive applications. It provides three half bridge  
drivers, each capable of driving two N-type  
MOSFETs, one for the high-side and one for the low  
side. It supports up to 2.3A sink and 1.7A source  
peak current capability and only needs a single power  
supply with a wide range from 8 to 60V. The  
DRV8302 uses bootstrap gate drivers with trickle  
charge circuitry to support 100% duty cycle. The gate  
driver uses automatic hand shaking when high side  
FET or low side FET is switching to prevent current  
shoot through. Vds of FETs is sensed to protect  
external power stage during overcurrent conditions.  
Operating Supply Voltage 8V60V  
2.3A Sink and 1.7A Source Gate Drive Current  
Capability  
Integrated Dual Shunt Current Amplifiers With  
Adjustable Gain and Offset  
Integrated Buck Converter to Support up to  
1.5A External Load  
Independent Control of 3 or 6 PWM Inputs  
Bootstrap Gate Driver With 100% Duty Cycle  
Support  
Programmable Dead Time to Protect External  
FETs from Shoot Through  
The DRV8302 includes two current shunt amplifiers  
for accurate current measurement. The current  
amplifiers support bi-directional current sensing and  
provide an adjustable output offset of up to 3V.  
Programmable Overcurrent Protection of  
External MOSFETs  
Thermally Enhanced 56-Pin TSSOP Pad Down  
DCA Package  
The DRV8302 also has an integrated switching mode  
buck converter with adjustable output and switching  
frequency to support MCU or additional system power  
needs. The buck is capable to drive up to 1.5A load.  
APPLICATIONS  
3-Phase Brushless DC Motor and Permanent  
Magnet Synchronous Motor  
CPAP and Pump  
E-bike, Hospital Bed, Wheel Chair  
Power Drill, Blender, Chopper  
PVDD  
DRV8302  
GH_A  
GL_A  
GH_B  
GL_B  
GH_C  
GL_C  
Buck  
Converter  
Three-Phase  
NMOS Gate  
Driver  
MOTOR  
PWM  
Vs  
3 or 6  
Control  
and  
Control  
Error  
Reporting  
Protection  
Logic  
Motor  
Controller  
ADC1  
Vref  
+
_
offset  
ADC2  
+
_
offset  
Figure 1. DRV8302 Simplified Application Schematic  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011, Texas Instruments Incorporated  
DRV8302  
SLES267 AUGUST 2011  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
DEVICE INFORMATION  
PIN ASSIGNMENT  
The DRV8302 is designed to fit the 56pin DCA package. Here is the pinout of the device.  
1
2
56  
55  
SS_TR  
RT_CLK  
COMP  
EN_BUCK  
54  
53  
PVDD2  
PVDD2  
3
4
VSENSE  
PWRGD  
52  
51  
50  
49  
48  
BST_BK  
PH  
5
6
OCTW  
FAULT  
7
PH  
DTC  
M_PWM  
M_OC  
BIAS  
8
9
BST_A  
GH_A  
47  
10  
11  
12  
GAIN  
46  
45  
SH_A  
GL_A  
OC_ADJ  
DC_CAL  
44  
43  
SL_A  
13  
14  
GVDD  
CP1  
BST_B  
42  
41  
40  
39  
15  
16  
17  
18  
GH_B  
SH_B  
GL_B  
SL_B  
CP2  
EN_GATE  
INH_A  
INL_A  
38  
37  
BST_C  
19  
20  
INH_B  
INL_B  
INH_C  
INL_C  
GH_C  
SH_C  
GL_C  
SL_C  
36  
35  
34  
33  
32  
31  
21  
22  
23  
24  
25  
26  
DVDD  
REF  
SN1  
SP1  
SN2  
SO1  
SO2  
SP2  
AVDD  
AGND  
30  
29  
27  
28  
PVDD1  
2
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Product Folder Link(s): DRV8302  
DRV8302  
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SLES267 AUGUST 2011  
PIN FUNCTIONS  
PIN  
I/O(1)  
DESCRIPTION  
NAME  
NO.  
RT_CLK  
1
I
Resistor timing and external clock for buck regulator. Resistor should connect to GND (power pad) with  
very short trace to reduce the potential clock jitter due to noise.  
COMP  
2
3
4
O
I
Buck error amplifier output and input to the output switch current comparator.  
Buck output voltage sense pin. Inverting node of error amplifier.  
VSENSE  
PWRGD  
I
An open drain output with external pull-up resistor required. Asserts low if buck output voltage is low  
due to thermal shutdown, dropout, over-voltage, or EN_BUCK shut down  
OCTW  
5
O
Over current and over temperature warning indicator. This output is open drain with external pull-up  
resistor required.  
FAULT  
DTC  
6
7
8
O
I
Fault report indicator. This output is open drain with external pull-up resistor required.  
Dead-time adjustment with external resistor to GND  
M_PWM  
I
Mode selection pin for PWM input configuration. If M_PWM = LOW, the device supports 6 independent  
PWM inputs. When M_PWM = HIGH, the device must be connected to ONLY 3 PWM input signals on  
INH_x. The complementary PWM signals for low side signaling will be internally generated from the  
high side inputs.  
M_OC  
9
I
Mode selection pin for over-current protection options. If M_OC = LOW, the gate driver will operate in a  
cycle-by-cycle current limiting mode. If M_OC = HIGH, the gate driver will shutdown the channel which  
detected an over-current event.  
GAIN  
10  
11  
12  
O
I
Gain selection for integrated current shunt amplifiers. If GAIN = LOW, the internal current shunt  
amplifiers have a gain of 10V/V. If GAIN = HIGH, the current shunt amplifiers have a gain of 40V/V.  
OC_ADJ  
DC_CAL  
Over-current trip set pin. Apply a voltage on this pin to set the trip point for the internal over-current  
protection circuitry. A voltage divider from DVDD is recommended.  
I
When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset  
calibration can be done through external microcontroller.  
GVDD  
CP1  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
P
P
P
I
Internal gate driver voltage regulator. GVDD cap should connect to GND  
Charge pump pin 1, ceramic cap should be used between CP1 and CP2  
Charge pump pin 2, ceramic cap should be used between CP1 and CP2  
Enable gate driver and current shunt amplifiers. Control buck via EN_BUCK pin.  
PWM Input signal (high side), half-bridge A  
CP2  
EN_GATE  
INH_A  
INL_A  
INH_B  
INL_B  
INH_C  
INL_C  
DVDD  
I
I
PWM Input signal (low side), half-bridge A  
I
PWM Input signal (high side), half-bridge B  
I
PWM Input signal (low side), half-bridge B  
I
PWM Input signal (high side), half-bridge C  
I
PWM Input signal (low side), half-bridge C  
P
Internal 3.3V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified  
to drive external circuitry.  
REF  
24  
I
Reference voltage to set output of shunt amplfiiers with a bias voltage which equals to half of the  
voltage set on this pin. Connect to ADC reference in microcontroller.  
SO1  
25  
26  
27  
O
O
P
Output of current amplifier 1  
Output of current amplifier 2  
SO2  
AVDD  
Internal 6V supply voltage, AVDD cap should connect to AGND. This is an output, but not specified to  
drive external circuitry.  
AGND  
28  
29  
P
P
Analog ground pin  
PVDD1  
Power supply pin for gate driver and current shunt amplifier. PVDD1 is independent of buck power  
supply, PVDD2. PVDD1 cap should connect to GND  
SP2  
30  
I
Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground  
side of the sense resistor for the best commom mode rejection.  
SN2  
SP1  
31  
32  
I
I
Input of current amplifier 2 (connecting to negative input of amplifier).  
Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground  
side of the sense resistor for the best commom mode rejection.  
SN1  
33  
I
Input of current amplifier 1 (connecting to negative input of amplifier).  
(1) KEY: I =Input, O = Output, P = Power  
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DRV8302  
SLES267 AUGUST 2011  
www.ti.com  
PIN FUNCTIONS (continued)  
PIN  
I/O(1)  
DESCRIPTION  
NAME  
NO.  
SL_C  
34  
I
Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and  
SH_C.  
GL_C  
SH_C  
35  
36  
O
I
Gate drive output for Low-Side MOSFET, half-bridge C  
High-Side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and  
PVDD1.  
GH_C  
BST_C  
SL_B  
37  
38  
39  
O
P
I
Gate drive output for High-Side MOSFET, half-bridge C  
Bootstrap cap pin for half-bridge C  
Low-Side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin and  
SH_B.  
GL_B  
SH_B  
40  
41  
O
I
Gate drive output for Low-Side MOSFET, half-bridge B  
High-Side MOSFET source connection, half-bridge B. High-side VDS measured between this pin and  
PVDD1.  
GH_B  
BST_B  
SL_A  
42  
43  
44  
O
P
I
Gate drive output for High-Side MOSFET, half-bridge B  
Bootstrap cap pin for half-bridge B  
Low-Side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin and  
SH_A.  
GL_A  
SH_A  
45  
46  
O
I
Gate drive output for Low-Side MOSFET, half-bridge A  
High-Side MOSFET source connection, half-bridge A. High-side VDS measured between this pin and  
PVDD1.  
GH_A  
47  
48  
O
P
I
Gate drive output for High-Side MOSFET, half-bridge A  
Bootstrap cap pin for half-bridge A  
BST_A  
BIAS  
49  
Bias pin. Connect 1MΩ resistor to GND, or 0.1 µF capacitor to GND.  
The source of the internal high side MOSFET of buck converter  
Bootstrap cap pin for buck converter  
PH  
50, 51  
52  
O
P
P
I
BST_BK  
PVDD2  
EN_BUCK  
53,54  
55  
Power supply pin for buck converter, PVDD2 cap should connect to GND.  
Enable buck converter. Internal pull-up current source. Pull below 1.2V to disable. Float to enable.  
Adjust the input undervoltage lockout with two resistors  
SS_TR  
56  
57  
I
Buck soft-start and tracking. An external capacitor connected to this pin sets the output rise time. Since  
the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. Cap  
should connect to GND  
GND  
(POWER  
PAD)  
P
GND pin. The exposed power pad must be electrically connected to ground plane through soldering to  
PCB for proper operation and connected to bottom side of PCB through vias for better thermal  
spreading.  
4
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Product Folder Link(s): DRV8302  
DRV8302  
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SLES267 AUGUST 2011  
FUNCTION BLOCK DIAGRAM  
PVDD1  
CP2  
OCTW  
FAULT  
Charge  
Pump  
Regulator  
Gate Driver  
Control  
&
EN_GATE  
DTC  
OSC  
CP1  
M_PWM  
Fault  
Handling  
GVDD  
M_OC  
GAIN  
Trickle  
Charge  
PVDD1  
OC_ADJ  
BIAS  
BST_A  
GH_A  
Phase A  
(repeated for B& C)  
High Side  
Motor  
Gate Drive  
Timing  
_A  
SH  
INH_A  
and  
Control  
Logic  
GL _A  
SL_A  
_A  
INL  
Low Side  
Gate Drive  
PVDD2  
Current  
Sense  
Amplifier1  
SN1  
SP1  
VSENSE  
BST_ BK  
1
Rshunt  
PGND  
REF  
PH  
_
DC CAL  
Offset  
½ Vref  
SN2  
SP2  
Current  
Sense  
Amplifier2  
Buck  
Converter  
Power  
Pad  
_
EN BUCK  
PWRGD  
AVDD  
_
SS TR  
Offset  
½ Vref  
_
RT CLK  
GND  
COMP  
DVDD  
AGND  
SO1  
SO2  
AGND GND PGND  
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SLES267 AUGUST 2011  
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UNITS  
ABSOLUTE MAXIMUM RATINGS(1)  
VALUE  
MIN  
MAX  
PVDD  
Supply voltage range including transient Relative to PGND  
Maximum supply voltage ramp rate Voltage rising up to PVDDMAX  
0.3  
50  
70  
V
V/mS  
V
PVDDRAMP  
VPGND  
Maximum voltage between PGND and GND  
±0.3  
±1  
IIN_MAX  
Maximum current, all digital and analog input pins except FAULT and OCTW pins  
Maximum sinking current for open drain pins (FAULT and OCTW Pins)  
Voltage range for SPx and SNx pins  
mA  
mA  
V
IIN_OD_MAX  
VOPA_IN  
VLOGIC  
7
±0.6  
-0.3  
Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C,  
INL_C, EN_GATE, M_PWM, M_OC, OC_ADJ, GAIN, DC_CAL)  
7
V
VGVDD  
VAVDD  
VDVDD  
VREF  
Maximum voltage for GVDD Pin  
Maximum voltage for AVDD Pin  
Maximum voltage for DVDD Pin  
Maximum reference voltage for current amplifier  
Maximum current for REF Pin  
13.2  
8
V
V
3.6  
7
V
V
IREF  
100  
40  
55  
500  
2000  
µA  
°C  
°C  
V
TJ  
Maximum operating junction temperature range  
Storage temperature range  
150  
150  
TSTORAGE  
Capacitive discharge model  
Human body model  
V
(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
THERMAL INFORMATION  
DRV8302  
THERMAL METRIC(1)  
DCA  
(56) PINS  
30.3  
UNITS  
θJA  
Junction-to-ambient thermal resistance  
θJCtop  
θJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
33.5  
17.5  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
0.9  
ψJB  
7.2  
θJCbot  
0.9  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
6
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RECOMMENDED OPERATING CONDITIONS  
MIN TYP MAX UNITS  
PVDD1  
PVDD2  
CAVDD  
CDVDD  
CGVDD  
CCP  
DC supply voltage PVDD1 for normal operation  
DC supply voltage PVDD2 for buck converter  
Relative to PGND  
8
60  
60  
V
3.5  
V
External capacitance on AVDD pin (ceramic cap) 20% tolerance  
External capacitance on DVDD pin (ceramic cap) 20% tolerance  
External capacitance on GVDD pin (ceramic cap) 20% tolerance  
Flying cap on charge pump pins (between CP1 and CP2) (ceramic cap) 20% tolerance  
Bootstrap cap (ceramic cap)  
1
1
µF  
µF  
µF  
nF  
nF  
µA  
µA  
pF  
pF  
2.2  
22  
CBST  
100  
IDIN_EN  
IDIN_DIS  
CDIN  
Input current of digital pins when EN_GATE is high  
100  
1
Input current of digital pins when EN_GATE is low  
Maximum capacitance on digital input pin  
10  
20  
CO_OPA  
Maximum output capacitance on outputs of shunt amplifier  
Dead time control resistor range. Time range is 50ns (-GND) to 500ns (150kΩ) with a  
linear approximation.  
RDTC  
0
150  
kΩ  
IFAULT  
IOCTW  
VREF  
FAULT pin sink current. Open-drain  
OCTW pin sink current. Open-drain  
V = 0.4 V  
V = 0.4 V  
2
2
6
mA  
mA  
V
External voltage reference voltage for current shunt amplifiers  
2
Qg(TOT) = 25 nC or total 30 mA gate  
drive average current  
fgate  
TA  
Operating switching frequency of gate driver  
Ambient temperature  
200  
125  
kHz  
40  
°C  
ELECTRICAL CHARACTERISTICS  
PVDD = 8-60 V, TC = 25°C, unless specified under test condition  
PARAMETER  
TEST CONDITIONS  
MIN TYP MAX UNIT  
INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL  
VIH  
High input threshold  
2
V
V
VIL  
Low input threshold  
0.8  
REN_GATE  
Internal pull down resistor for EN_GATE  
100  
100  
kΩ  
Internal pull down resistor for high side PWMs  
(INH_A, INH_B, and INH_C)  
RINH_X  
RINH_X  
EN_GATE high  
kΩ  
kΩ  
Internal pull down resistor for low side PWMs  
(INL_A, INL_B, and INL_C)  
EN_GATE high  
100  
RM_PWM  
RM_OC  
Internal pull down resistor for M_PWM  
Internal pull down resistor for M_OC  
Internal pull down resistor for DC_CAL  
EN_GATE high  
EN_GATE high  
EN_GATE high  
100  
100  
100  
kΩ  
kΩ  
kΩ  
RDC_CAL  
OUTPUT PINS: FAULT AND OCTW  
VOL  
Low output threshold  
IO = 2 mA  
0.4  
1
V
V
External 47 kΩ pull up resistor connected to  
3-5.5 V  
VOH  
High output threshold  
2.4  
Leakage Current on Open Drain Pins When  
Logic High (FAULT and OCTW)  
IOH  
µA  
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ELECTRICAL CHARACTERISTICS (continued)  
PVDD = 8-60 V, TC = 25°C, unless specified under test condition  
PARAMETER  
TEST CONDITIONS  
MIN TYP MAX UNIT  
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C  
VGX_NORM  
Ioso1  
Gate driver Vgs voltage  
PVDD = 860V  
9.5  
11.5  
V
A
A
Maximum source current setting 1, peak  
Maximum sink current setting 1, peak  
Vgs of FET equals to 2 V. REG 0x02  
Vgs of FET equals to 8 V. REG 0x02  
1.7  
2.3  
Iosi1  
Gate output impedence during standby mode  
when EN_GATE low (pins GH_x, GL_x)  
Rgate_off  
1.6  
2.4  
50  
kΩ  
SUPPLY CURRENTS  
IPVDD1_STB  
IPVDD1_OP  
IPVDD1_HIZ  
PVDD1 supply current, standby  
EN_GATE is low. PVDD1 = 8V.  
20  
15  
5
µA  
EN_GATE is high, no load on gate drive  
output, switching at 10 kHz,  
100 nC gate charge  
PVDD1 supply current, operating  
PVDD1 Supply current, HiZ  
mA  
EN_GATE is high, gate not switching  
2
11 mA  
INTERNAL REGULATOR VOLTAGE  
AVDD  
DVDD  
AVDD voltage  
DVDD voltage  
6
3
6.5  
3.3  
7
V
V
3.6  
VOLTAGE PROTECTION  
VPVDD_UV  
VGVDD_UV  
VGVDD_OV  
Under voltage protection limit, PVDD  
6
8
V
V
V
Under voltage protection limit, GVDD  
Over voltage protection limit, GVDD  
16  
CURRENT PROTECTION, (VDS SENSING)  
VDS_OC  
Toc  
Drain-source voltage protection limit  
OC sensing response time  
0.125  
2.4  
V
1.5  
64  
µs  
OCTW pin reporting pulse stretch length for OC  
event  
TOC_PULSE  
µs  
8
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GATE TIMING AND PROTECTION CHARACTERISTICS  
PARAMETER  
TEST CONDITIONS  
MIN TYP  
MAX UNIT  
TIMING, OUTPUT PINS  
tpd,If-O  
tpd,Ir-O  
Td_min  
Tdtp  
Positive input falling to GH_x falling  
Positive input rising to GL_x falling  
Minimum dead time after hand shaking(1)  
Dead Time  
CL=1nF, 50% to 50%  
CL=1nF, 50% to 50%  
45  
45  
ns  
ns  
50  
ns  
ns  
ns  
ns  
With RDTC set to different values  
CL=1nF, 10% to 90%  
50  
500  
tGDr  
Rise time, gate drive output  
Fall time, gate drive output  
25  
25  
tGDF  
CL=1nF, 90% to 10%  
Not including handshake communication.  
Hiz to on state, output of gate driver  
TON_MIN  
Minimum on pulse  
50  
ns  
Propagation delay matching between high  
side and low side  
Tpd_match  
Tdt_match  
5
5
ns  
ns  
Deadtime matching  
TIMING, PROTECTION AND CONTROL  
PVDD is up before start up, all charge  
pump caps and regulator caps as in  
recommended condition  
Start up time, from EN_GATE active high  
to device ready for normal operation  
tpd,R_GATE-OP  
5
10  
10  
ms  
us  
If EN_GATE goes from high to low and  
back to high state within quick reset time,  
it will only reset all faults and gate driver  
without powering down charge pump,  
current amp, and related internal voltage  
regulators.  
tpd,R_GATE-Quick  
Maximum low pulse time  
tpd,E-L  
Delay, error event to all gates low  
Delay, error event to FAULT low  
200  
200  
ns  
ns  
tpd,E-FAULT  
Junction temperature for resetting over  
temperature warning  
OTW_CLR  
115  
130  
150  
°C  
°C  
°C  
Junction temperature for over  
temperature warning and resetting over  
temperature shut down  
OTW_SET/OTSD  
_CLR  
Junction temperature for over  
temperature shut down  
OTSD_SET  
(1) Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising  
edge. This is a minimum dead-time insertion. It is not added to the value set by the microcontroller externally.  
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CURRENT SHUNT AMPLIFIER CHARACTERISTICS  
TC = 25°C unless otherwise specified  
PARAMETER  
Gain option 1  
TEST CONDITIONS  
(GAIN = 0V)  
MIN  
9.5  
38  
TYP  
10  
MAX UNIT  
G1  
10.5  
42  
V/V  
V/V  
ns  
G2  
Gain Option 2  
(GAIN = 2V)  
40  
Tsettling  
Tsettling  
Vswing  
Slew Rate  
DC_offset  
Drift_offset  
Ibias  
Settling time to 1%  
Settling time to 1%  
Output swing linear range  
Tc = 0-60°C, G = 10, Vstep = 2 V  
Tc = 0-60°C, G = 40, Vstep = 2 V  
300  
1.2  
µs  
0.3  
5.7  
4
V
G = 10  
10  
10  
V/µs  
mV  
µV/C  
µA  
V
Offset error RTI  
G = 10 with input shorted  
Offset drift RTI  
Input bias current  
Common input mode range  
Differential input range  
Output bias  
100  
0.15  
0.3  
Vin_com  
Vin_dif  
Vo_bias  
0.15  
0.3  
V
With zero input current, Vref up to 6 V  
CMRR at DC, gain = 10  
0.5% 0.5×Vref  
0.5%  
V
Overall CMRR with gain resistor  
mismatch  
CMRR_OV  
70  
85  
dB  
BUCK CONVERTER CHARACTERISTICS  
TC = 25°C unless otherwise specified  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
2.5  
MAX UNIT  
VUVLO  
Internal undervoltage lockout threshold  
Shutdown supply current  
No voltage hysteresis, rising and falling  
EN = 0 V, 25°C, 3.5 V VIN 60 V  
VSENSE = 0.83 V, VIN = 12 V  
V
ISD(PVDD2)  
1.3  
4
µA  
µA  
INON_SW(PVDD2) Operating: nonswitching supply current  
116  
136  
No voltage hysteresis, rising and falling,  
25°C  
VEN_BUCK  
Enable threshold voltage  
0.9  
1.25  
1.55  
410  
V
RDS_ON  
ILIM  
On-resistance  
VIN = 12 V, BOOT-PH = 6 V  
200  
2.7  
mΩ  
A
Current limit threshold  
Thermal shutdown  
Switching frequency  
VIN = 12 V, TJ = 25°C  
1.8  
OTSD_BK  
Fsw  
150  
°C  
RT = 200 kΩ  
450  
581  
720  
kHz  
VSENSE falling  
VSENSE rising  
VSENSE rising  
VSENSE falling  
VSENSE falling  
92%  
94%  
109%  
107%  
2%  
PWRGD  
VSENSE threshold  
Hysteresis  
VSENSE = VREF, V(PWRGD) = 5.5 V,  
25°C  
Output high leakage  
On resistance  
10  
50  
nA  
I(PWRGD) = 3 mA, VSENSE < 0.79 V  
10  
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FUNCTIONAL DESCRIPTION  
THREE-PHASE GATE DRIVER  
The DRV8302 provides three half bridge drivers, each capable of driving two N-type MOSFETs, one for the  
high-side and one for the low side.  
Gate driver has following features:  
Internal hand shake between high side and low side FETs during switching transition to prevent current shoot  
through.  
Support up to 200kHz switching frequency with Qg(TOT)=25nC or total 30mA gate drive average current  
Provide cycle-by-cycle current limiting and latch over-current (OC) shut down of external FETs. Current is  
sensed through FET drain-to-source voltage and the over-current level is programmable through OC_ADJ pin  
High side gate drive will survive negative output from half bridge up to 10V for 10ns  
During EN_GATE pin low and fault conditions, gate driver will keep external FETs in high impedance mode.  
Programmable dead time through DTC pin. Dead time control range: 50ns to 500ns. Short DTC pin to ground  
will provide minimum dead time (50ns). External dead time will override internal dead time as long as the time  
is longer than the dead time setting (minimum hand shake time cannot be reduced in order to prevent shoot  
through current).  
Bootstraps are used in high side FETs of three-phase pre-gate driver. Trickle charge circuitry is used to  
replenish current leakage from bootstrap cap and support 100% duty cycle operation.  
CURRENT SHUNT AMPLIFIERS  
The DRV8302 includes two high performance current shunt amplifiers for accurate current measurement. The  
current amplifiers provide output offset up to 3V to support bi-directional current sensing.  
Current shunt amplifier has following features:  
Programmable gain: 2 gain settings through GAIN pin  
Programmable output offset through reference pin (half of the Vref)  
Minimize DC offset and drift over temperature with dc calibrating through DC_CAL pin. When DC calibration  
is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating can be  
done at anytime even when FET is switching since the load is disconnected. For best result, perform the DC  
calibrating during switching off period when no load is present to reduce the potential noise impact to the  
amplifier.  
The output of current shunt amplifier can be calculated as:  
VREF  
VO  
=
- G ´ SN - SPX  
X
(
)
2
(1)  
Where Vref is the reference voltage, G is the gain of the amplifier; SNx and SPx are the inputs of channel x. SPx  
should connect to resistor ground for the best common mode rejection.  
Figure 2 shows current amplifier simplified block diagram.  
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S2  
S1  
200 kW  
50 kW  
DC_CAL  
SN  
5 kW  
5 kW  
AVDD  
_
100 W  
DC_CAL  
SO  
+
SP  
S1  
S2  
50 kW  
DC CAL  
_
200 kW  
Vref/2  
REF  
AVDD  
_
+
50 kW  
50 kW  
Figure 2. Current Shunt Amplifier Simplified Block Diagram  
BUCK CONVERTER  
Although integrated in the same device, buck converter is designed completely independent of rest of the gate  
driver circuitry. Since buck will support external MCU or other external power need, the independency of buck  
operation is very critical for a reliable system; this will give buck minimum impact from gate driver operations.  
Some examples are: when gate driver shuts down due to any failure, buck will still operate unless the fault is  
coming from buck itself. The buck keeps operating at much lower PVDD of 3.5V, this will assure the system to  
have a smooth power up and power down sequence when gate driver is not able to operate due to a low PVDD.  
The buck has an integrated high side n-channel MOSFET. To improve performance during line and load  
transients the device implements a constant frequency, current mode control which reduces output capacitance  
and simplifies external frequency compensation design.  
The wide switching frequency of 450kHz to 720kHz allows for efficiency and size optimization when selecting the  
output filter components. The switching frequency is adjusted using a resistor to ground on the RT_CLK pin.  
The buck converter has a default start up voltage of approximately 2.5V. The EN_BUCK pin has an internal  
pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with  
two external resistors. In addition, the pull up current provides a default condition. When the EN_BUCK pin is  
floating the device will operate. The operating current is 116µA when not switching and under no load. When the  
device is disabled, the supply current is 1.3µA.  
The integrated 200mΩ high side MOSFET allows for high efficiency power supply designs capable of delivering  
1.5 amperes of continuous current to a load. The bias voltage for the integrated high side MOSFET is supplied  
by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn  
the high side MOSFET off when the boot voltage falls below a preset threshold. The buck can operate at high  
duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V  
reference.  
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The buck has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than  
92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which  
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the  
pin to transition high when a pull-up resistor is used.  
The buck minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good  
comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from turning  
on until the output voltage is lower than 107%.  
The SS_TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing  
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor  
divider can be coupled to the pin for critical power supply sequencing requirements. The SS_TR pin is  
discharged before the output powers up. This discharging ensures a repeatable restart after an over-temperature  
fault,  
The buck, also, discharges the slow start capacitor during overload conditions with an overload recovery circuit.  
The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage  
once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup  
and overcurrent fault conditions to help control the inductor current.  
PROTECTION FEATURES  
Power Stage Protection  
The DRV8302 provides over-current and under-voltage protection for the MOSFET power stage. During fault  
shut down conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state.  
Over-Current Protection (OCP) and Reporting  
To protect the power stage from damage due to high currents, a VDS sensing circuitry is implemented in the  
DRV8302. Based on RDS(on) of the power MOSFETs and the maximum allowed IDS, a voltage threshold can be  
calculated which, when exceeded, triggers the OC protection feature. This voltage threshold level is  
programmable through the OC_ADJ terminal (see next section) by applying an external reference voltage with a  
DAC or resistor divider from DVDD.  
There are a total of 2 OC_MODE settings selectable with the M_OC pin.  
1. Current Limit Mode (M_OC = LOW)  
When current limit mode is enabled, device operates current limiting instead of OC shut down during OC  
event. During OC event, the FET that detected OC will turn off until next PWM cycle. The over-current event  
is reported through OCTW pin. OCTW reporting should hold low during same PWM cycle or for a max 64µs  
period (internal timer) so external controller has enough time to sample the warning signal. If in the middle of  
reporting, other FET(s) gets OC, then OCTW reporting will hold low and recount another 64µS unless PWM  
cycles on both FETs are ended.  
2. OC latch shut down mode (M_OC = HIGH)  
When OC occurs, device will turn off both high side and low side FETs in the same phase if any of the FETs  
in that phase has OC.  
OC_ADJ  
When external MOSFET is turned on, the output current flows through the on resistance, RDS(on) of the  
MOSFET, which creates a voltage drop VDS. The over current protection event will be enabled when the VDS  
exceeds a pre-set value. The voltage on OC_ADJ pin will be used to pre-set the OC tripped value. The OC  
tripped value IOC has to meet following equations:  
R2  
´ DVDD = VDS  
(R1 + R2)  
(2)  
VDS  
IOC  
=
RDS(on)  
(3)  
13  
Where  
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R1 + R2 100 KΩ  
DVDD = 3.3 V  
Connect OC_ADJ pin to DVDD to disable the over-current protection feature.  
DVDD  
R1  
V
OC  
OC_ADJ  
R2  
Figure 3. OC_ADJ Current Programming Pin Connection  
Under-Voltage Protection (UVP)  
To protect the power output stage during startup, shutdown and other possible under-voltage conditions, the  
DRV8302 provides power stage under-voltage protection by driving its outputs low whenever PVDD is below 6V  
(PVDD_UV) or GVDD is below 8V (GVDD_UV). When UVP is triggered, the DRV8302 outputs are driven low  
and the external MOSFETs will go to a high impedance state.  
Over-Voltage Protection (GVDD_OV)  
Device will shut down both gate driver and charge pump if GVDD voltage exceeds 16V to prevent potential issue  
related to GVDD or charge pump (e.g. short of external GVDD cap or charge pump). The fault is a latched fault  
and can only be reset through a transition on EN_GATE pin.  
Over-Temperature Protection  
A two-level over-temperature detection circuit is implemented:  
Level 1: over temperature warning (OTW)  
OTW is reported through OCTW pin.  
Level 2: over temperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE)  
Fault will be reported to FAULT pin. This is a latched shut down, so gate driver will not be recovered  
automatically even if OT condition is not present anymore. An EN_GATE reset through pin is required to  
recover gate driver to normal operation after temperature goes below a preset value, tOTSD_CLR  
.
Fault and Protection Handling  
The FAULT pin indicates an error event with shut down has occurred such as over-current, over-temperature,  
over-voltage, or under-voltage. Note that FAULT is an open-drain signal. FAULT will go high when gate driver is  
ready for PWM signal (internal EN_GATE goes high) during start up.  
The OCTW pin indicates an over temperature or over current event that is not necessarily related to shut down.  
Following is the summary of all protection features and their reporting structure:  
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Table 1. Fault and Warning Reporting and Handling  
REPORTING ON  
FAULT PIN  
REPORTING ON  
OCTW PIN  
EVENT  
ACTION  
LATCH  
External FETs HiZ;  
Weak pull down of all gate  
driver output  
PVDD  
undervoltage  
N
Y
Y
Y
N
N
N
External FETs HiZ;  
Weak pull down of all gate  
driver output; When recovering,  
reset all status registers  
DVDD  
undervoltage  
N
N
External FETs HiZ;  
Weak pull down of all gate  
driver output  
GVDD  
undervoltage  
External FETs HiZ;  
Weak pull down of all gate driver output  
Shut down the charge pump  
Wont recover and reset through  
SPI reset command or  
GVDD  
overvoltage  
Y
Y
N
quick EN_GATE toggling  
OTW  
None  
N
Y
N
Y
Y
Y
Gate driver latched shut down.  
Weak pull down of all gate driver output  
to force external FETs HiZ  
OTSD_GATE  
OTSD_BUCK  
Shut down the charge pump  
OTSD of Buck  
Y
N
N
N
N
Buck output  
undervoltage  
UVLO_BUCK: auto-restart  
Y, in PWRGD pin  
Buck current limiting  
Buck overload  
External FET  
(HiZ high side until current reaches  
zero and then auto-recovering)  
N
N
N
N
N
Y
External FETs current Limiting  
(only OC detected FET)  
overload current limit  
mode  
Weak pull down of gate driver  
output and PWM logic 0of  
LS and HS in the same phase.  
External FETs HiZ  
External FET  
overload Latch mode  
Y
N
Y
N
Y
Y
External FET  
overload reporting only  
mode  
Reporting only  
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PIN CONTROL FUNCTIONS  
EN_GATE  
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EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into  
a low power consumption mode to save energy. Device will put the MOSFET output stage to high impedance  
mode as long as PVDD is still present.  
When EN_GATE pin goes to high, it will go through a power up sequence, and enable gate driver, current  
amplifiers, charge pump, internal regulator, etc and reset all latched faults related to gate driver block. All latched  
faults can be reset when EN_GATE is toggled after an error event unless the fault is still present.  
When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can put  
external FETs in high impedance mode. It will then wait for 10us before completely shutting down the rest of the  
blocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10µS).  
This will prevent device to shut down other function blocks such as charge pump and internal regulators and  
bring a quicker and simple fault recovery.  
One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset wont work with GVDD_OV fault.  
A complete EN_GATE with low level holding longer than 10 µs is required to reset GVDD_OV fault. It is highly  
recommended to inspect the system and board when GVDD_OV occurs.  
EN_BUCK  
Buck enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable.  
DTC  
Dead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to control  
the dead time. Dead time control range is from 50ns to 500ns. Short DTC pin to ground will provide minimum  
dead time (50ns). Resistor range is 0 to 150kΩ. Dead time is linearly set over this resistor range.  
Current shoot through prevention protection will be enabled in the device all time independent of dead time  
setting and input mode setting.  
DC_CAL  
When DC_CAL is enabled, device will short inputs of shunt amplifier and disconnect from the load, so external  
microcontroller can do a DC offset calibration.  
STARTUP AND SHUTDOWN SEQUENCE CONTROL  
During power-up all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifiers  
can be initiated by toggling EN_GATE from a low state to a high state. If no errors are present after a 10-ms wait  
time, the DRV8302 is ready to accept PWM inputs. Gate driver always has control of the power FETs even in  
gate disable mode as long as PVDD is within functional region.  
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APPLICATION SCHEMATIC EXAMPLE  
Example:  
Buck: PVDD= 3.5V 40V, Iout_max = 1.5A, Vo = 3.3V, Fs = 570 kHz  
PVDD  
0.015 mF  
6.8nF  
VCC  
120  
pF  
205kW  
3.3  
470mF  
16.2KW  
RT_CLK  
SS_TR  
EN_BUCK  
PVDD 2  
10 nF  
31.6kW  
10kW  
COMP  
PVDD  
VSENSE  
PWRGD  
10kW  
0.1 mF  
0.1 mF  
10kW  
VCC  
PVDD 2  
4.7mF  
22 mH  
10kW  
OCTW  
FAULT  
DTC  
BST _BK  
PH  
VCC (3.3V)  
PVDD  
47mF  
PH  
M_PWM  
M_OC  
GAIN  
BIAS  
0.1mF  
1 MW  
BST _A  
GH_A  
SH_A  
GL_A  
OC_ADJ  
DC_CAL  
GVDD  
CP1  
_A  
SL  
MOTOR  
2.2 mF  
0.1mF  
22 nF  
BST _B  
GH_B  
SH_B  
Motor  
Controller  
CP2  
EN_GATE  
_A  
INH  
_B  
GL  
SL_B  
_C  
INL_A  
0.1 mF  
_B  
INH  
BST  
GH_C  
_C  
INL_B  
_C  
INH  
SH  
INL_C  
DVDD  
REF  
GL_C  
SL_C  
SN1  
1 mF  
Power  
Pad  
10mW RS1  
1 nF  
SO1  
SP1  
SO2  
SN2  
RS2  
1 nF  
10mW  
GND  
AVDD  
SP2  
1 mF  
AGND  
PVDD 1  
PVDD  
4.7 mF  
0.1 mF  
AGND GND  
GND PGND  
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PACKAGE OPTION ADDENDUM  
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19-Sep-2011  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
DRV8302DCA  
ACTIVE  
ACTIVE  
HTSSOP  
HTSSOP  
DCA  
DCA  
56  
56  
35  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
DRV8302DCAR  
2000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Audio  
Applications  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
www.ti.com/security  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
Medical  
Security  
Logic  
Space, Avionics and Defense www.ti.com/space-avionics-defense  
Transportation and Automotive www.ti.com/automotive  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
microcontroller.ti.com  
www.ti-rfid.com  
Video and Imaging  
www.ti.com/video  
OMAP Mobile Processors www.ti.com/omap  
Wireless Connectivity www.ti.com/wirelessconnectivity  
TI E2E Community Home Page  
e2e.ti.com  
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