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产品型号DS90C363AMTDX的概述

芯片DS90C363AMTDX的概述 DS90C363AMTDX是一款高速串行数字信号传输芯片，主要用于在较远距离内，以极高的传输速率传送数字数据。此技术尤其适用于需要远程传输的应用，比如汽车电子、视频监控及工业自动化等领域。DS90C363AMTDX包含串行收发器，该收发器通过差分信号处理方式来减少信号在传输过程中的干扰，确保在高噪声环境中也能稳定运行。 DS90C363AMTDX的设计目的在于提供一种高带宽、低延迟的解决方案，使得多种数据类型能够安全、有效地进行传输。它能够支持多种协议，并具有兼容性，适应各种应用需求。其工作频率可达到几百兆赫兹，体现出良好的性能，尤其是在复杂的电路板设计和制造过程中，借助其高集成度，它可以有效减少布线的复杂性，从而提高整体系统性能。芯片DS90C363AMTDX的详细参数 DS90C363AMTDX的主要技术参数如下： - 工作电压: 3.3V ...

产品型号DS90C363AMTDX的Datasheet PDF文件预览

September 1999

DS90C363/DS90CF364

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel

Display (FPD) Link—65 MHz, +3.3V LVDS Receiver

18-Bit Flat Panel Display (FPD) Link—65 MHz

General Description

Features

n 20 to 65 MHz shift clock support

n Programmable Transmitter (DS90C363) strobe select

(Rising or Falling edge strobe)

The DS90C363 transmitter converts 21 bits of CMOS/TTL

data into three LVDS (Low Voltage Differential Signaling)

data streams. A phase-locked transmit clock is transmitted in

parallel with the data streams over a fourth LVDS link. Every

cycle of the transmit clock 21 bits of input data are sampled

and transmitted. The DS90CF364 receiver converts the

LVDS data streams back into 21 bits of CMOS/TTL data. At

a transmit clock frequency of 65 MHz, 18 bits of RGB data

n Single 3.3V supply

n Chipset (Tx + Rx) power consumption 250 mW (typ)

n Power-down mode ( 0.5 mW total)

n Single pixel per clock XGA (1024x768) ready

n Supports VGA, SVGA, XGA and higher addressability.

n Up to 170 Megabyte/sec bandwidth

and

3 bits of LCD timing and control data (FPLINE,

FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per

LVDS data channel. Using a 65 MHz clock, the data through-

puts is 170 Mbytes/sec. The Transmitter is offered with pro-

grammable edge data strobes for convenient interface with a

variety of graphics controllers. The Transmitter can be pro-

grammed for Rising edge strobe or Falling edge strobe

through a dedicated pin. A Rising edge Transmitter will inter-

operate with a Falling edge Receiver (DS90CF364) without

any translation logic.

n Up to 1.3 Gbps throughput

n Narrow bus reduces cable size and cost

n 290 mV swing LVDS devices for low EMI

n PLL requires no external components

n Low profile 48-lead TSSOP package

n Falling edge data strobe Receiver

n Compatible with TIA/EIA-644 LVDS standard

n ESD rating 7 kV

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

n Operating Temperature: −40˚C to +85˚C

Block Diagrams

Application

DS012886-14

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS012886

www.national.com

Block Diagrams (Continued)

DS90C363

DS012886-1

Order Number DS90C363MTD

See NS Package Number MTD48

DS90CF364

DS012886-24

Order Number DS90CF364MTD

See NS Package Number MTD48

www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

DS90C363

DS90CF364

1.98 W

1.89 W

Package Derating:

DS90C363

16 mW/˚C above +25˚C

15 mW/˚C above +25˚C

DS90CF364

Supply Voltage (V_CC

)

−0.3V to +4V

−0.3V to (V_CC+ 0.3V)

ESD Rating

(HBM, 1.5 kΩ, 100 pF)

CMOS/TTL Input Voltage

CMOS/TTL Output Voltage

LVDS Receiver Input Voltage

LVDS Driver Output Voltage

7 kV

Recommended Operating

Conditions

LVDS Output Short Circuit

Duration

Continuous

+150˚C

Min Nom Max

Units

Junction Temperature

Storage Temperature

Supply Voltage (V_CC

Operating Free Air

Temperature (T_A)

)

3.0

3.3

3.6

−65˚C to +150˚C

Lead Temperature

(Soldering, 4 sec)

−40

+25

+85

2.4

˚C

+260˚C

Receiver Input Range

Maximum Package Power Dissipation Capacity 25˚C

MTD48 (TSSOP) Package:

Supply Noise Voltage (V_CC

)

100

mV_PP

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CMOS/TTL DC SPECIFICATIONS

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Clamp Voltage

2.0

GND

2.7

V_CC

0.8

V_OH

V_OL

V_CL

I_IN

I_OH= −0.4 mA

I_OL= 2 mA

3.3

0.06

0.3

I_CL= −18 mA

−0.79

−1.5

Input Current

V_IN= V_CC, GND, 2.5V or 0.4V

V_OUT= 0V

5.1

µA

I_OS

Output Short Circuit Current

−60

−120

LVDS DC SPECIFICATIONS

V_OD

Differential Output Voltage

R_L= 100Ω

250

345

450

∆V_OD

Change in V_ODbetween

complimentary output states

Offset Voltage (Note 4)

V_OS

1.125

1.25

−3.5

1.375

∆V_OS

Change in V

between

complimentary output states

Output Short Circuit Current

Output TRI-STATE^®Current

I_OS

I_OZ

V_OUT= 0V, R_L= 100Ω

PWR DWN = 0V,

V_OUT= 0V or V_CC

V_CM= +1.2V

−5

µA

V_TH

V_TL

I_IN

Differential Input High Threshold

Differential Input Low Threshold

Input Current

+100

µA

−100

V_IN= +2.4V, V_CC= 3.6V

V_IN= 0V, V_CC= 3.6V

µA

TRANSMITTER SUPPLY CURRENT

ICCTW

Transmitter Supply Current, Worst

Case

R_L= 100Ω,

f = 32.5 MHz

C_L= 5 pF, Worst

Case Pattern (Figures

1, 3 ), T_A= −40˚C to

+85˚C

f = 37.5 MHz

f = 65 MHz

ICCTG

Transmitter Supply Current, 16

Grayscale

R_L= 100Ω,

C_L= 5 pF, 16

Grayscale Pattern

(Figures 2, 3 ), T_A

−40˚C to +85˚C

f = 32.5 MHz

f = 37.5 MHz

f = 65 MHz

www.national.com

Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

TRANSMITTER SUPPLY CURRENT

ICCTZ

Transmitter Supply Current

Power Down

PWR DWN = Low

Driver Outputs in TRI-STATE^®under

µA

Power Down Mode

RECEIVER SUPPLY CURRENT

ICCRW

ICCRG

ICCRZ

Receiver Supply Current, Worst

Case

C_L= 8 pF, Worst

Case Pattern (Figures

1, 4 ), T_A= −40˚C to

+85˚C

f = 32.5 MHz

f = 37.5 MHz

f = 65 MHz

105

Receiver Supply Current, 16

Grayscale

C_L= 8 pF, 16

Grayscale Pattern

f = 32.5 MHz

(Figures 2, 4 ), T_A

−40˚C to +85˚C

f = 37.5 MHz

f = 65 MHz

µA

Receiver Supply Current

Power Down

PWR DWN = Low

Receiver Outputs Stay Low during

Power Down Mode

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V

= 3.3V and T = +25C.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-

fied (except V and ∆V ).

Note 4:

previously referred as V .

www.national.com

Transmitter Switching Characteristics

Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified

Symbol

LLHT

Parameter

LVDS Low-to-High Transition Time (Figure 3 )

LVDS High-to-Low Transition Time (Figure 3 )

TxCLK IN Transition Time (Figure 5 )

Min

Typ

0.75

Max

1.5

Units

LHLT

TCIT

TCCS

TPPos0

TxOUT Channel-to-Channel Skew (Figure 6 )

250

Transmitter Output Pulse Position for Bit 0

(Figure 17 )

f = 65 MHz

−0.4

0.3

TPPos1

TPPos2

TPPos3

TPPos4

TPPos5

TPPos6

TCIP

Transmitter Output Pulse Position for Bit 1

Transmitter Output Pulse Position for Bit 2

Transmitter Output Pulse Position for Bit 3

Transmitter Output Pulse Position for Bit 4

Transmitter Output Pulse Position for Bit 5

Transmitter Output Pulse Position for Bit 6

TxCLK IN Period (Figure 7)

1.8

4.0

2.2

4.4

2.5

4.7

6.2

6.6

6.9

8.4

8.8

9.1

10.6

12.8

11.0

13.2

11.3

13.5

TCIH

TxCLK IN High Time (Figure 7)

0.35T

2.5

0.5T

0.65T

TCIL

TxCLK IN Low Time (Figure 7)

TSTC

TxIN Setup to TxCLK IN (Figure 7 )

TxIN Hold to TxCLK IN (Figure 7 )

f = 65 MHz

THTC

TCCD

TPLLS

TPDD

TxCLK IN to TxCLK OUT Delay 25˚C, V_CC= 3.3V (Figure 9 )

Transmitter Phase Lock Loop Set (Figure 11 )

Transmitter Power Down Delay (Figure 15 )

3.0

3.7

5.5

100

www.national.com

Receiver Switching Characteristics

Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified

Symbol

CLHT

Parameter

CMOS/TTL Low-to-High Transition Time (Figure 4 )

CMOS/TTL High-to-Low Transition Time (Figure 4 )

Receiver Input Strobe Position for Bit 0 (Figure 18 )

Receiver Input Strobe Position for Bit 1

Receiver Input Strobe Position for Bit 2

Receiver Input Strobe Position for Bit 3

Receiver Input Strobe Position for Bit 4

Receiver Input Strobe Position for Bit 5

Receiver Input Strobe Position for Bit 6

RxIN Skew Margin (Note 5) (Figure 19 )

RxCLK OUT Period (Figure 8)

Min

Typ

2.2

Max

5.0

Units

µs

CHLT

2.2

5.0

RSPos0

RSPos1

RSPos2

RSPos3

RSPos4

RSPos5

RSPos6

RSKM

f = 65 MHz

0.7

2.9

1.1

1.4

3.3

3.6

5.1

5.5

5.8

7.3

7.7

8.0

9.5

9.9

10.2

12.4

14.6

11.7

13.9

400

12.1

14.3

f = 65 MHz

RCOP

RCOH

RCOL

RxCLK OUT High Time (Figure 8 )

f = 65 MHz

7.3

8.6

4.9

6.9

5.7

7.1

RxCLK OUT Low Time (Figure 8)

3.45

2.5

RSRC

RxOUT Setup to RxCLK OUT (Figure 8 )

RxOUT Hold to RxCLK OUT (Figure 8 )

RHRC

2.5

RCCD

RxCLK IN to RxCLK OUT Delay 25˚C, V_CC= 3.3V (Figure 10 )

Receiver Phase Lock Loop Set (Figure 12 )

5.0

9.0

RPLLS

RPDD

Receiver Power Down Delay (Figure 16 )

Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min

and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol inter-

ference (both dependent on type/length of cable), and clock jitter (less than 250 ps).

AC Timing Diagrams

DS012886-2

FIGURE 1. “Worst Case” Test Pattern

www.national.com

AC Timing Diagrams (Continued)

DS012886-3

FIGURE 2. “16 Grayscale” Test Pattern (Notes 6, 7, 8, 9)

Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.

Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed

to produce groups of 16 vertical stripes across the display.

Note 8: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).

Note 9: Recommended pin to signal mapping. Customer may choose to define differently.

DS012886-15

FIGURE 3. DS90C363 (Transmitter) LVDS Output Load and Transition Times

DS012886-4

FIGURE 4. DS90CF364 (Receiver) CMOS/TTL Output Load and Transition Times

DS012886-16

FIGURE 5. DS90C363 (Transmitter) Input Clock Transition Time

www.national.com

AC Timing Diagrams (Continued)

DS012886-17

Measurements at Vdiff=0V

TCCS measured between earliest and latest LVDS edges

→

TxCLK Differential Low

High Edge

FIGURE 6. DS90C363 (Transmitter) Channel-to-Channel Skew

DS012886-18

FIGURE 7. DS90C363 (Transmitter) Setup/Hold and High/Low Times

DS012886-5

FIGURE 8. DS90CF364 (Receiver) Setup/Hold and High/Low Times

DS012886-19

FIGURE 9. DS90C363 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)

www.national.com

AC Timing Diagrams (Continued)

DS012886-6

FIGURE 10. DS90CF364 (Receiver) Clock In to Clock Out Delay

DS012886-20

FIGURE 11. DS90C363 (Transmitter) Phase Lock Loop Set Time

DS012886-7

FIGURE 12. DS90CF364 (Receiver) Phase Lock Loop Set Time

www.national.com

AC Timing Diagrams (Continued)

DS012886-9

FIGURE 13. Seven Bits of LVDS in One Clock Cycle

DS012886-10

FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs

DS012886-21

FIGURE 15. Transmitter Power Down Delay

DS012886-8

FIGURE 16. Receiver Power Down Delay

www.national.com

AC Timing Diagrams (Continued)

DS012886-22

FIGURE 17. Transmitter LVDS Output Pulse Position Measurement

www.national.com

AC Timing Diagrams (Continued)

DS012886-25

FIGURE 18. Receiver LVDS Input Strobe Position

www.national.com

AC Timing Diagrams (Continued)

DS012886-11

C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max

Tppos — Transmitter output pulse position (min and max)

RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)

Cable Skew — typically 10 ps–40 ps per foot, media dependent

Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHz.

Note 11: ISI is dependent on interconnect length; may be zero.

FIGURE 19. Receiver LVDS Input Skew Margin

DS90C363 Pin Description— FPD Link Transmitter

Pin Name

TxIN

I/O No.

Description

TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,

FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).

TxOUT+

Positive LVDS differentiaI data output.

TxOUT−

Negative LVDS differential data output.

FPSHIFT IN

R_FB

TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.

Programmable strobe select.

RTxCLK OUT+

TxCLK OUT−

PWR DWN

Positive LVDS differential clock output.

Negative LVDS differential clock output.

TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at

power down.

V _CC

Power supply pins for TTL inputs.

Ground pins for TTL inputs.

Power supply pin for PLL.

GND

PLL V _CC

PLL GND

LVDS V _CC

LVDS GND

Ground pins for PLL.

Power supply pin for LVDS outputs.

Ground pins for LVDS outputs.

www.national.com

DS90CF364 Pin Description— FPD Link Receiver

Pin Name

RxIN+

I/O No.

Description

Positive LVDS differentiaI data inputs.

Negative LVDS differential data inputs.

RxIN−

RxOUT

TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,

FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).

RxCLK IN+

RxCLK IN−

FPSHIFT OUT

PWR DWN

V _CC

Positive LVDS differential clock input.

Negative LVDS differential clock input.

TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.

TTL level input. When asserted (low input) the receiver outputs are low.

Power supply pins for TTL outputs.

GND

Ground pins for TTL outputs.

PLL V _CC

PLL GND

LVDS V _CC

LVDS GND

Power supply for PLL.

Ground pin for PLL.

Power supply pin for LVDS inputs.

Ground pins for LVDS inputs.

Applications Information

The DS90C363 and DS90CF364 are backward compatible

with the existing 5V FPD Link transmitter/receiver pair

(DS90CF563 and DS90CF564). To upgrade from a 5V to a

3.3V system the following must be addressed:

1. Change 5V power supply to 3.3V. Provide this supply to

the V_CC, LVDS V_CCand PLL V _CCof both the transmitter

and receiver devices. This change may enable the re-

moval of a 5V supply from the system, and power may

be supplied from an existing 3V power source.

2. The DS90C363 (transmitter) incorporates

a rise/fall

strobe select pin. This select function is on pin 14, for-

merly a V_CCconnection on the 5V products. When the

rise/fall strobe select pin is connected to V _CC, the part is

configured with a rising edge strobe. In a system cur-

rently using

a 5V rising edge strobe transmitter

(DS90CR563), no layout changes are required to ac-

commodate the new rise/fall select pin on the 3.3V

transmitter. The V_CCsignal may remain at pin 14, and

the device will be configured with a rising edge strobe.

When converting from a 5V falling edge transmitter

(DS90CF563) to the 3V transmitter a minimal board

layout change is necessary. The 3.3V transmitter will

not be configured with a falling edge strobe if V_CCre-

mains connected to the select pin. To guarantee the

3.3V transmitter functions with a falling edge strobe pin

14 should be connected to ground OR left unconnected.

When not connected (left open) and internal pull-down

resistor ties pin 14 to ground, thus configuring the trans-

mitter with a falling edge strobe.

3. The DS90C363 transmitter input and control inputs ac-

cept 3.3V TTL/CMOS levels. They are not 5V tolerant.

www.national.com

Pin Diagram

DS90C363

DS90CF364

DS012886-13

DS012886-23

TABLE 1. Programmable Transmitter

Condition

R_FB = V_CC

R_FB = GND

Strobe Status

Rising edge strobe

Falling edge strobe

R_FB

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Molded Thin Shrink Small Outline Package, JEDEC

Dimensions show in millimeters

Order Number DS90C363MTD and DS90CF364MTD

NS Package Number MTD48

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 1 80-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 1 80-530 85 85

English Tel: +49 (0) 1 80-532 78 32

Français Tel: +49 (0) 1 80-532 93 58

Italiano Tel: +49 (0) 1 80-534 16 80

Email: sea.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

DS90C363AMTDX相关文章

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DS90C363AMTDX产品参数

型号:	DS90C363AMTDX
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Active
IHS 制造商：	ROCHESTER ELECTRONICS LLC
零件包装代码：	TSSOP
包装说明：	LOW PROFILE, PLASTIC, TSSOP-48
针数：	48
Reach Compliance Code：	unknown
风险等级：	5.08
差分输出：	YES
驱动器位数：	4
输入特性：	STANDARD
接口集成电路类型：	LINE DRIVER
接口标准：	EIA-644; TIA-644
JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0
长度：	12.5 mm
湿度敏感等级：	NOT SPECIFIED
功能数量：	4
端子数量：	48
最高工作温度：	70 °C
最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	COMMERCIAL
座面最大高度：	1.2 mm
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	6.1 mm
Base Number Matches：	1

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产品型号DS90C363AMTDX的概述

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