DS90CR288MTD全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号DS90CR288MTD的概述

DS90CR288MTD芯片概述 DS90CR288MTD是一款广泛应用于高速串行数据传输的双通道数字串行接口芯片，尤其适用于汽车、工业自动化及通信设备等领域。由于其优秀的传输速率和可靠性，DS90CR288MTD成为了众多应用的首选组件。该芯片的设计主要是为了满足数据在长距离传输时的稳定性和完整性要求，通过差分信号传输的方式，降低了对噪声的敏感性，从而提高系统的抗干扰能力。 DS90CR288MTD详细参数 1. 电源电压：5V ±10% 2. 传输速率：高达 1 Gbps 3. 信号通道：2 通道 4. 工作温度范围：-40°C 到 +85°C 5. 数据格式：支持 8、10 或者 12 位数据 6. 接口标准：兼容LVDS（低压差分信号） 7. 供电功耗：低功耗设计 8. 封装类型：TQFP(Thin Quad Flat Package) 9. 引脚数：48引脚厂家、包装和...

产品型号DS90CR288MTD的Datasheet PDF文件预览

May 2002

DS90CR288

+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel

Link Receiver - 75 MHz

General Description

Features

n 20 to 75 MHz shift clock support

n 50% duty cycle on receiver output clock

The DS90CR287 (see DS90CR287/288A datasheet) trans-

mitter converts 28 bits of CMOS/TTL data into four LVDS

(Low Voltage Differential Signaling) data streams. A phase-

locked transmit clock is transmitted in parallel with the data

streams over a fifth LVDS link. Every cycle of the transmit

clock 28 bits of input data are sampled and transmitted. The

DS90CR288 receiver converts the four LVDS data streams

back into 28 bits of CMOS/TTL data. At a transmit clock

frequency of 75 MHz, 28 bits of TTL data are transmitted at

a rate of 525 Mbps per LVDS data channel. Using a 75 MHz

clock, the data throughput is 2.10 Gbit/s (262.5 Mbytes/sec).

n Best-in-Class Set & Hold Times on TxINPUTs and

RxOUTPUTs

n Low power consumption

n Tx + Rx Powerdown mode 400µW (max)

1V common-mode range (around +1.2V)

n Narrow bus reduces cable size and cost

n Up to 2.10 Gbps throughput

n Up to 262.5 Mbytes/sec bandwidth

n 345 mV (typ) swing LVDS devices for low EMI

n PLL requires no external components

n Rising edge data strobe

Complete specifications for the DS90CR287 are located in

the DS90CR287/DS90CR288A datasheet. The DS90CR287

supports clock rates from 20 to 85 MHz.

n Compatible with TIA/EIA-644 LVDS standard

n Low profile 56-lead TSSOP package

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high-speed TTL interfaces.

Block Diagrams

DS90CR287

DS90CR288

DS100872-27

DS100872-1

Order Number DS90CR288MTD

See NS Package Number MTD56

Order Number DS90CR287MTD

See NS Package Number MTD56

(See DS90CR287/DS90CR288A datasheet)

DS100872

www.national.com

Pin Diagram

DS90CR288

DS100872-22

Typical Application

DS100872-23

www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Package Derating:

DS90CR288

12.4 mW/˚C above +25˚C

ESD Rating

(HBM, 1.5kΩ, 100pF)

(EIAJ, 0Ω, 200pF)

7kV

700V

Supply Voltage (V_CC

)

−0.3V to +4V

−0.5V to (V_CC+ 0.3V)

−0.3V to (V_CC+ 0.3V)

+150˚C

300mA

Latch Up Tolerance +25˚C

CMOS/TTL Input Voltage

CMOS/TTL Output Voltage

LVDS Receiver Input Voltage

Junction Temperature

Storage Temperature

Lead Temperature

Recommended Operating

Conditions

−65˚C to +150˚C

Min Nom Max Units

Supply Voltage (V_CC

Operating Free Air

Temperature (T_A)

)

3.0

3.3

3.6

(Soldering, 4 sec.)

+260˚C

Maximum Package Power Dissipation +25˚C

MTD56 (TSSOP) Package:

DS90CR288

−10

+25

+70

2.4

˚C

Receiver Input Range

1.61 W

Supply Noise Voltage (V_CC

)

100 mV_PP

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CMOS/TTL DC SPECIFICATIONS

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Clamp Voltage

Input Current

2.0

GND

2.7

V_CC

0.8

V_OH

V_OL

V_CL

I_IN

I_OH= −0.4 mA

3.3

I_OL= 2 mA

0.06

0.3

−1.5

+10

I_CL= −18 mA

V_IN= 0.4V, 2.5V or V_CC

V_IN= GND

−0.79

+1.8

µA

−10

I_OS

Output Short Circuit Current

V_OUT= 0V

−60

−120

+100

LVDS RECEIVER DC SPECIFICATIONS

V_TH

V_TL

I_IN

Differential Input High Threshold

Differential Input Low Threshold

Input Current

V_CM= +1.2V

µA

−100

V_IN= +2.4V, V_CC= 3.6V

V_IN= 0V, V_CC= 3.6V

µA

RECEIVER SUPPLY CURRENT

I_CCRWReceiver Supply Current Worst

C_L= 8 pF,

Worst Case

Pattern

f = 33 MHz

Case

f = 40 MHz

f = 66 MHz

f = 75 MHz

105

130

(Figures 1, 2)

110

I_CCRZ

Receiver Supply Current Power

Down

PWR DWN = Low

Receiver Outputs Stay Low during

Powerdown Mode

µA

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V

= 3.3V and T = +25˚C.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise

specified (except V and V ).

www.national.com

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

CLHT

Parameter

CMOS/TTL Low-to-High Transition Time (Figure 2)

CMOS/TTL High-to-Low Transition Time (Figure 2)

Receiver Input Strobe Position for Bit 0 (Figure 8)

Receiver Input Strobe Position for Bit 1

Receiver Input Strobe Position for Bit 2

Receiver Input Strobe Position for Bit 3

Receiver Input Strobe Position for Bit 4

Receiver Input Strobe Position for Bit 5

Receiver Input Strobe Position for Bit 6

Min

Typ

Max

3.5

Units

CHLT

1.8

3.5

RSPos0

RSPos1

RSPos2

RSPos3

RSPos4

RSPos5

RSPos6

RSKM

f = 75 MHz

0.58

2.49

4.39

6.30

8.20

10.11

12.01

380

0.95

2.86

4.76

6.67

8.57

10.48

12.38

1.32

3.23

5.13

7.04

8.94

10.85

12.75

Receiver Skew Margin (when used with DS90CR287) (Note

4) (Figure 9)

f = 75 MHz

RCOP

RCOH

RCOL

RSRC

RHRC

RCCD

RPLLS

RPDD

RxCLK OUT Period (Figure 3)

13.33

3.6

6.0

µs

RxCLK OUT High Time (Figure 3)

RxCLK OUT Low Time (Figure 3)

RxOUT Setup to RxCLK OUT (Figure 3)

RxOUT Hold to RxCLK OUT (Figure 3)

3.6

3.5

RxCLK IN to RxCLK OUT Delay 25˚C, V_CC= 3.3V (Note 5)(Figure 4)

Receiver Phase Lock Loop Set (Figure 5)

3.4

5.0

7.3

Receiver Powerdown Delay (Figure 7)

Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min

and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference

(both dependent on type/length of cable), and source clock (less than 250 ps).

Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency

for the 217/287 transmitter and 218/288 receiver is: (T + TCCD) + (2 T + RCCD), where T = Clock period. See also DS90CR287/DS90CR288A datasheet.

AC Timing Diagrams

DS100872-2

FIGURE 1. “Worst Case” Test Pattern

DS100872-5

DS100872-6

FIGURE 2. DS90CR288 (Receiver) CMOS/TTL Output Load and Transition Times

www.national.com

AC Timing Diagrams (Continued)

DS100872-10

FIGURE 3. DS90CR288 (Receiver) Setup/Hold and High/Low Times

DS100872-12

FIGURE 4. DS90CR288 (Receiver) Clock In to Clock Out Delay

DS100872-14

FIGURE 5. DS90CR288 (Receiver) Phase Lock Loop Set Time

www.national.com

AC Timing Diagrams (Continued)

DS100872-16

FIGURE 6. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR287)

DS100872-18

FIGURE 7. Receiver Powerdown Delay

www.national.com

AC Timing Diagrams (Continued)

DS100872-28

FIGURE 8. Receiver LVDS Input Strobe Position

www.national.com

AC Timing Diagrams (Continued)

DS100872-20

C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max

Tppos — Transmitter output pulse position (min and max)

RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 6) + ISI (Inter-symbol interference)(Note 7)

Cable Skew — typically 10 ps–40 ps per foot, media dependent

Note 6: Cycle-to-cycle jitter is less than 250ps at 75MHz.

Note 7: ISI is dependent on interconnect length; may be zero

FIGURE 9. Receiver LVDS Input Skew Margin (DS90CR287/DS90CR288A)

DS90CR288 Pin Description—Channel Link Receiver

Pin Name

RxIN+

I/O

No.

Description

Positive LVDS differential data inputs. (Note 8)

RxIN−

Negative LVDS differential data inputs. (Note 8)

TTL level data outputs.

RxOUT

RxCLK IN+

RxCLK IN−

RxCLK OUT

PWR DWN

V_CC

Positive LVDS differential clock input.

Negative LVDS differential clock input.

TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.

TTL level input. When asserted (low input) the receiver outputs are low.

Power supply pins for TTL outputs.

GND

Ground pins for TTL outputs.

PLL V_CC

PLL GND

LVDS V_CC

LVDS GND

Power supply for PLL.

Ground pin for PLL.

Power supply pin for LVDS inputs.

Ground pins for LVDS inputs.

Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions

receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last

valid state. A floating/terminated clock input will result in a LOW clock output.

www.national.com

Applications Information

The DS90CR287 and DS90CR288 are backward compatible

with the existing 5V Channel Link transmitter/receiver pair

(DS90CR283, DS90CR284). To upgrade from a 5V to a 3.3V

system the following must be addressed:

improved transmission parameters such as faster attainable

speeds, longer distances between transmitter and receiver

and reduced problems associated with EMS or EMI.

The high-speed transport of LVDS signals has been demon-

strated on several types of cables with excellent results.

However, the best overall performance has been seen when

using Twin-Coax cable. Twin-Coax has very low cable skew

and EMI due to its construction and double shielding. All of

the design considerations discussed here and listed in the

supplemental application notes provide the subsystem com-

munications designer with many useful guidelines. It is rec-

ommended that the designer assess the tradeoffs of each

application thoroughly to arrive at a reliable and economical

cable solution.

1. Change 5V power supply to 3.3V. Provide this supply to

the V_CC, LVDS V_CCand PLL V_CC

2. Transmitter input and control inputs except 3.3V TTL/

CMOS levels. They are not 5V tolerant.

3. The receiver powerdown feature when enabled will lock

receiver output to a logic low. However, the 5V/66 MHz

receiver maintain the outputs in the previous state when

powerdown occurred.

The Channel Link devices are intended to be used in a wide

variety of data transmission applications. Depending upon

the application the interconnecting media may vary. For

example, for lower data rate (clock rate) and shorter cable

BOARD LAYOUT: To obtain the maximum benefit from the

noise and EMI reductions of LVDS, attention should be paid

to the layout of differential lines. Lines of a differential pair

should always be adjacent to eliminate noise interference

from other signals and take full advantage of the noise

canceling of the differential signals. The board designer

should also try to maintain equal length on signal traces for

a given differential pair. As with any high-speed design, the

impedance discontinuities should be limited (reduce the

numbers of vias and no 90 degree angles on traces). Any

discontinuities which do occur on one signal line should be

mirrored in the other line of the differential pair. Care should

be taken to ensure that the differential trace impedance

match the differential impedance of the selected physical

media (this impedance should also match the value of the

termination resistor that is connected across the differential

pair at the receiver’s input). Finally, the location of the

CHANNEL LINK TxOUT/RxIN pins should be as close as

possible to the board edge so as to eliminate excessive pcb

runs. All of these considerations will limit reflections and

crosstalk which adversely effect high frequency performance

and EMI.

lengths ( 2m), the media electrical performance is less

critical. For higher speed/long distance applications the me-

dia’s performance becomes more critical. Certain cable con-

structions provide tighter skew (matched electrical length

between the conductors and pairs). Twin-coax for example,

has been demonstrated at distances as great as 5 meters

and with the maximum data transfer of 2.10 Gbit/s. Addi-

tional applications information can be found in the following

National Interface Application Notes:

AN = ####

AN-1041

AN-1108

Topic

Introduction to Channel Link

PCB Design Guidelines for LVDS and

Link Devices

AN-806

AN-905

Transmission Line Theory

Transmission Line Calculations and

Differential Impedance

AN-916

Cable Information

TERMINATION: Use of current mode drivers requires a

terminating resistor across the receiver inputs. The CHAN-

NEL LINK chipset will normally require a single 100Ω resistor

between the true and complement lines on each differential

pair of the receiver input. The actual value of the termination

resistor should be selected to match the differential mode

characteristic impedance (90Ω to 120Ω typical) of the cable.

Figure 10 shows an example. No additional pull-up or pull-

down resistors are necessary as with some other differential

technologies such as PECL. Surface mount resistors are

recommended to avoid the additional inductance that ac-

companies leaded resistors. These resistors should be

placed as close as possible to the receiver input pins to

reduce stubs and effectively terminate the differential lines.

CABLES: A cable interface between the transmitter and

receiver needs to support the differential LVDS pairs. The

21-bit CHANNEL LINK chipset (DS90CR217/218) requires

four pairs of signal wires and the 28-bit CHANNEL LINK

chipset (DS90CR287/288) requires five pairs of signal wires.

The ideal cable/connector interface would have a constant

100Ω differential impedance throughout the path. It is also

recommended that cable skew remain below 130ps ( 75

MHz clock rate) to maintain a sufficient data sampling win-

dow at the receiver.

In addition to the four or five cable pairs that carry data and

clock, it is recommended to provide at least one additional

conductor (or pair) which connects ground between the

transmitter and receiver. This low impedance ground pro-

vides a common-mode return path for the two devices.

Some of the more commonly used cable types for point-to-

point applications include flat ribbon, flex, twisted pair and

Twin-Coax. All are available in a variety of configurations and

options. Flat ribbon cable, flex and twisted pair generally

perform well in short point-to-point applications while Twin-

Coax is good for short and long applications. When using

ribbon cable, it is recommended to place a ground line

between each differential pair to act as a barrier to noise

coupling between adjacent pairs. For Twin-Coax cable ap-

plications, it is recommended to utilize a shield on each

cable pair. All extended point-to-point applications should

also employ an overall shield surrounding all cable pairs

regardless of the cable type. This overall shield results in

DECOUPLING CAPACITORS: Bypassing capacitors are

needed to reduce the impact of switching noise which could

limit performance. For

a conservative approach three

parallel-connected decoupling capacitors (Multi-Layered Ce-

ramic type in surface mount form factor) between each V_CC

and the ground plane(s) are recommended. The three ca-

pacitor values are 0.1 µF, 0.01 µF and 0.001 µF. An example

is shown in Figure 11. The designer should employ wide

traces for power and ground and ensure each capacitor has

its own via to the ground plane. If board space is limiting the

number of bypass capacitors, the PLL V_CCshould receive

the most filtering/bypassing. Next would be the LVDS V_CC

pins and finally the logic V_CCpins.

www.national.com

Applications Information (Continued)

DS100872-24

FIGURE 10. LVDS Serialized Link Termination

importance to the system’s operation due to the differential

data transmission. LVDS supports an input voltage range of

Ground to +2.4V. This allows for a 1.0V shifting of the

center point due to ground potential differences and

common-mode noise.

TRANSMITTER INPUT CLOCK: The transmitter input clock

must always be present when the device is enabled (PWR

DWN = HIGH). If the clock is stopped, the PWR DWN pin

must be used to disable the PLL. The PWR DWN pin must

be held low until after the input clock signal has been reap-

plied. This will ensure a proper device reset and PLL lock to

occur.

DS100872-25

POWER SEQUENCING AND POWERDOWN MODE: Out-

puts of the CHANNEL LINK transmitter remain in TRI-STATE

until the power supply reaches 2V. Clock and data outputs

will begin to toggle 10 ms after V_CChas reached 3V and the

Powerdown pin is above 1.5V. Either device may be placed

into a powerdown mode at any time by asserting the Pow-

erdown pin (active low). Total power dissipation for each

device will decrease to 5 µW (typical).

FIGURE 11. CHANNEL LINK

Decoupling Configuration

CLOCK JITTER: The CHANNEL LINK devices employ a

PLL to generate and recover the clock transmitted across the

LVDS interface. The width of each bit in the serialized LVDS

data stream is one-seventh the clock period. For example, a

75 MHz clock has a period of 13.33 ns which results in a

data bit width of 1.90 ns. Differential skew (∆t within one

differential pair), interconnect skew (∆t of one differential pair

to another) and clock jitter will all reduce the available win-

dow for sampling the LVDS serial data streams. Care must

be taken to ensure that the clock input to the transmitter be

a clean low noise signal. Individual bypassing of each V_CCto

ground will minimize the noise passed on to the PLL, thus

creating a low jitter LVDS clock. These measures provide

more margin for channel-to-channel skew and interconnect

skew as a part of the overall jitter/skew budget.

The transmitter input clock may be applied prior to powering

up and enabling the transmitter. The transmitter input clock

may also be applied after power up; however, the use of the

PWR DWN pin is required as described in the Transmitter

Input Clock section. Do not power up and enable (PWR

DWN = HIGH) the transmitter without a valid clock signal

applied to the TxCLK IN pin.

The CHANNEL LINK chipset is designed to protect itself

from accidental loss of power to either the transmitter or

receiver. If power to the transmit board is lost, the receiver

clocks (input and output) stop. The data outputs (RxOUT)

retain the states they were in when the clocks stopped.

When the receiver board loses power, the receiver inputs are

shorted to V_CCthrough an internal diode. Current is limited

(5 mA per input) by the fixed current mode drivers, thus

avoiding the potential for latchup when powering the device.

COMMON-MODE vs. DIFFERENTIAL MODE NOISE MAR-

GIN: The typical signal swing for LVDS is 300 mV centered

at +1.2V. The CHANNEL LINK receiver supports a 100 mV

threshold therefore providing approximately 200 mV of dif-

ferential noise margin. Common-mode protection is of more

www.national.com

Applications Information (Continued)

DS100872-26

FIGURE 12. Single-Ended and Differential Waveforms

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Physical Dimensions inches (millimeters) unless otherwise noted

Order Number DS90CR288MTD

Dimensions in millimeters only

NS Package Number MTD56

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: support@nsc.com

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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DS90CR288MTD产品参数

型号:	DS90CR288MTD
生命周期：	Obsolete
零件包装代码：	TSSOP
包装说明：	TSSOP,
针数：	56
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	7.5
差分输出：	NO
输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE RECEIVER
接口标准：	EIA-644; TIA-644
JESD-30 代码：	R-PDSO-G56
长度：	14 mm
功能数量：	1
端子数量：	56
最高工作温度：	70 °C
最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
接收器位数：	28
座面最大高度：	1.1 mm
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
宽度：	6.1 mm
Base Number Matches：	1

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