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DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

DS90UB925Q-Q1 具有双向控制通道的 5 到 85 MHz 24 位

彩色 FPD-Link III 串行器

1 特性

3 说明

具有 I²C 兼容串行控制总线的双向控制接口通道接

口

DS90UB925Q-Q1 串行器与 DS90UB926Q-Q1 解串器

相连，可提供完整的数字接口以实现汽车显示屏和图像

传感应用中高速视频、音频和控制数据的并行传输。

1

•

支持高清 (720p) 数字视频格式

支持 RGB888 + VS，HS，DE 和 I2S 音频

支持两个 10 位摄像机视频流

支持 5 至 85MHz 并行时钟 (PCLK)

该芯片组非常适合高清 (HD) 格式的车载视频显示系统

和具有百万象素级分辨率的车载视觉系统。

DS90UB925Q-Q1 整合了嵌入式双向控制通道和低延

迟 GPIO 控制。该芯片组将一个并行接口转换为一个

单对高速串行接口。 FPD-Link III 串行总线方案支持通

过单个差分链路实现高速视频数据传输和双向控制通信

的全双工控制。通过单个差分对整合视频数据和控制

可减少互连线尺寸和重量，同时还消除了偏差问题并简

化了系统设计。

通过 1.8V 或 3.3V 兼容 LVCMOS I/O 接口实现

3.3V 单电源运行

•

长达 10 米的 AC 耦合生成树协议 (STP) 互连

并行 LVCMOS 视频输出

具有嵌入式时钟的直流均衡和扰频数据

支持中继器应用

内部模式生成

DS90UB925Q-Q1 串行器内嵌时钟，可通过直流扰频

& 均衡数据有效载荷，并将信号电平转换为高速低压差

分信令。最多有 24 个数据位可随视频控制信号一同

串化。

低功率模式最大限度地减少了功率耗散

汽车应用级产品：符合 AEC-Q100 2 级要求

>8kV 人体模型 (HBM) 和 ISO 10605 静电放电

(ESD) 等级

•

向下兼容至 FPD-Link II

串行传输通过用户可选的去加重功能进行优化。低压

差分信令的使用、数据换序和随机生成以及展频定时兼

容性最大限度地减少了电磁干扰 (EMI)。

2 应用范围

•

汽车导航显示屏

器件信息⁽¹⁾

后座娱乐系统

汽车驾驶员辅助系统

车载百万象素级摄像机系统

部件号

封装

WQFN (48)

封装尺寸（标称值）

DS90UB925Q-Q1

7.00mm x 7.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

V

DDIO

DD33

DDIO

(1.8Vor3.3V) (3.3V)

DD33

(3.3V) (1.8Vor3.3V)

R[7:0]

G[7:0]

R[7:0]

G[7:0]

FPD-Link III

1 Pair / AC Coupled

B[7:0]

HS

VS

DE

PCLK

0.1 PF

HOST

Graphics

Processor

RGB Display

720p

24-bit color depth

HS

DOUT+

RIN+

RIN-

VS

DE

PCLK

DOUT-

100: STP Cable

DS90UB925Q-Q1

Serializer

DS90UB926Q-Q1

Deserializer

LOCK

PASS

PDB

OSS_SEL

OEN

PDB

3

I2S AUDIO

(STEREO)

3

I2S AUDIO

(STEREO)

MODE_SEL

INTB

INTB_IN

MCLK

SCL

SDA

IDx

SCL

SDA

IDx

DAP

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SNLS407

DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

www.ti.com.cn

7.4 Device Functional Modes........................................ 22

7.5 Programming .......................................................... 25

7.6 Register Maps ........................................................ 27

Application and Implementation ........................ 38

8.1 Application Information............................................ 38

8.2 Typical Application .................................................. 38

Power Supply Recommendations...................... 41

9.1 Power Up Requirements and PDB Pin................... 41

9.2 CML Interconnect Guidelines.................................. 41

1

2

3

4

5

6

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

6.1 Absolute Maximum Ratings ..................................... 7

6.2 Handling Ratings....................................................... 7

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 8

6.5 DC Electrical Characteristics .................................... 8

6.6 AC Electrical Characteristics................................... 10

6.7 Recommended Timing for the Serial Control Bus .. 11

6.8 Switching Characteristics........................................ 13

6.9 Typical Charateristics ............................................. 14

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 15

7.3 Feature Description................................................. 15

8

9

10 Layout................................................................... 42

10.1 Layout Guidelines ................................................. 42

10.2 Layout Example .................................................... 43

11 器件和文档支持 ..................................................... 45

11.1 文档支持................................................................ 45

11.2 商标....................................................................... 45

11.3 静电放电警告......................................................... 45

11.4 术语表 ................................................................... 45

12 机械封装和可订购信息 .......................................... 45

7

4 修订历史记录

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (April 2013) to Revision D

Page

•

已添加数据表流程和版面布局，以符合全新 TI 标准。已添加以下章节：处理额定值、器件功能模式；编程；电源建

议；布局布线；器件和文档支持；机械封装和订购信息 ......................................................................................................... 1

已添加器件信息表.................................................................................................................................................................. 1

Fixed typo for GPIO configuration ........................................................................................................................................ 19

Removed two MODE_SEL modes: I2S Channel B, and Backward Compatible.................................................................. 23

Removed IDx addresses 0x22, 0x24, 0x2E, 0x30, 0x32, 0x34............................................................................................ 26

Changed suggested resistor values for IDx addresses 0x1E, 0x20, 0x26, 0x28, 0x2A....................................................... 26

•

Changes from Revision B (August 2012) to Revision C

Page

•

已更改国家数据表布局至 TI 格式。....................................................................................................................................... 1

Changes from Revision A (July 2012) to Revision B

Page

•

Added typical charateristic graphics..................................................................................................................................... 14

Added” Note: frequency range = 15 - 65MHz when LFMODE = 0 and frequency range = 5 - <15MHz when

LFMODE = 1.” under Functional Description. ...................................................................................................................... 16

•

Reformatted Table 2 and added clarification to notes.......................................................................................................... 19

Added clarification to notes on Table 6, address 0x04[3:0] (backwards compatible and LFMODE registers). .................. 27

Changes from Original (March 2012) to Revision A

Page

•

已转换为混合 TI 格式。 .......................................................................................................................................................... 1

Corrected typo in SCL from pin 6 to pin 8.............................................................................................................................. 4

Corrected typo in SDA from pin 7 to pin 9.............................................................................................................................. 4

2

DS90UB925Q-Q1

www.ti.com.cn

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

•

Added to Absolute Maximum Rating section, note (3): The maximum limit (V_DDIO+0.3V) does not apply to the PDB

pin during the transition to the power down state (PDB transitioning from HIGH to LOW).................................................... 7

•

Deleted derate from Maximum Power Dissipation Capacity at 25°C..................................................................................... 7

Added "Note: BIST is not available in backwards compatible mode." ................................................................................. 20

Corrected typo in Table 4 "I2S Channel B (18-bit Mode)" from L to H ............................................................................... 23

Corrected typo in Table 5 Ideal V_R2(V) from 2.475 to 1.475. .............................................................................................. 26

3

DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

www.ti.com.cn

5 Pin Configuration and Functions

DS90UB925Q-Q1

48 Pin WQFN

Top View

G2 / DIN10

37

MODE_SEL

CMF

24

23

22

21

20

19

18

17

16

15

14

13

G3 / DIN11

38

G4 / DIN12

39

VDD33

PDB

G5 / DIN13

40

G6 / DIN14

41

DOUT+

DOUT-

RES1

G7 / DIN15

42

DS90UB925Q-Q1

TOP VIEW

GPO_REG4 / B0 / DIN16

43

CAPHS12

NC

I2S_DB / GPO_REG5 / B1 / DIN17 44

B2 / DIN18

45

DAP = GND

B3 / DIN19

46

RES0

B4 / DIN20

47

CAPP12

B5 / DIN21

48

I2S_CLK / GPO_REG8

Pin Functions

PIN NAME

PIN #

I/O, TYPE

DESCRIPTION

LVCMOS PARALLEL INTERFACE

DIN[23:0] /

R[7:0],

25, 26, 27, 28, I, LVCMOS Parallel Interface Data Input Pins

29, 32, 33, 34, w/ pull down Leave open if unused

G[7:0],

B[7:0]

35, 36, 37, 38,

39, 40, 41, 42,

43, 44, 45, 46,

47, 48, 1, 2

DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as GPIO1

DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as GPIO3

DIN16 / B0 can optionally be used as GPIO4 and DIN17 / B1 can optionally be used as

GPIO5

HS

VS

3

I, LVCMOS Horizontal Sync Input Pin

w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the

Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when

the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.

See Table 6.

4

I, LVCMOS Vertical Sync Input Pin

w/ pull down Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width

is 130 PCLKs.

4

DS90UB925Q-Q1

www.ti.com.cn

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

Pin Functions (continued)

PIN NAME

PIN #

I/O, TYPE

DESCRIPTION

DE

5

I, LVCMOS Data Enable Input Pin

w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the

Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when

the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.

See Table 6.

PCLK

10

I, LVCMOS Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6.

w/ pull down

I2S_CLK,

I2S_WC,

I2S_DA

13, 12, 11

I, LVCMOS Digital Audio Interface Data Input Pins

w/ pull down Leave open if unused

I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as

GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.

OPTIONAL PARALLEL INTERFACE

I2S_DB

44

I, LVCMOS

Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by

w/ pull down MODE_SEL pin or configuration register

Leave open if unused

I2S_DB can optionally be used as DIN17 or GPO_REG5.

GPIO[3:0]

36, 35, 26, 25 I/O, LVCMOS General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or

w/ pull down configuration register. See Table 6.

Leave open if unused.

Shared with DIN9, DIN8, DIN1 and DIN0

GPO_REG[ 13, 12, 11, 44, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 6.

8:4]

43

w/ pull down Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or DIN17, DIN16.

CONTROL

PDB

21

I, LVCMOS Power-down Mode Input Pin

w/ pull-down PDB = H, device is enabled (normal operation)

Refer to Power Up Requirements and PDB Pin section.

PDB = L, device is powered down.

When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is

shutdown, and IDD is minimized. Control Registers are RESET.

MODE_SEL

I²C

24

6

I, Analog

Device Configuration Select. See Table 4.

IDx

I²C Serial Control Bus Device ID Address Select

External pull-up to V_DD33is required under all conditions, DO NOT FLOAT.

Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 19.

SCL

SDA

8

9

I/O, LVCMOS I²C Clock Input / Output Interface

Open Drain Must have an external pull-up to V_DD33, DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.

I/O, LVCMOS I²C Data Input / Output Interface

Open Drain Must have an external pull-up to V_DD33, DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.

STATUS

INTB

31

O, LVCMOS Interrupt

Open Drain INTB = H, normal

INTB = L, Interrupt request

Recommended pull-up: 4.7kΩ to V_DDIO

FPD-LINK III SERIAL INTERFACE

DOUT+

DOUT-

CMF

20

19

23

O, LVDS

Analog

True Output

The output must be AC-coupled with a 0.1µF capacitor.

Inverting Output

The output must be AC-coupled with a 0.1µF capacitor.

Common Mode Filter.

Connect 0.1µF to GND

5

DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

www.ti.com.cn

Pin Functions (continued)

PIN NAME

PIN #

I/O, TYPE

DESCRIPTION

(1)

POWER AND GROUND

V_DD33

V_DDIO

GND

22

30

Power

Ground

Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND

LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND

DAP

DAP is the large metal contact at the bottom side, located at the center of the WQFN

package. Connect to the ground plane (GND) with at least 9 vias.

REGULATOR CAPACITOR

CAPHS12,

CAPP12

17, 14

CAP

Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each

CAP pin.

CAPL12

7

Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this

CAP pin.

OTHERS

NC

16

NC

Do not connect.

RES[1:0]

18, 15

GND

Reserved. Tie to Ground.

(1) The VDD (V_DD33and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.

6

DS90UB925Q-Q1

www.ti.com.cn

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

6 Specifications

6.1 Absolute Maximum Ratings

(1) (2)

MIN

-0.3

MAX

UNIT

V

Supply Voltage – V_DD33

Supply Voltage – V_DDIO

LVCMOS I/O Voltage⁽³⁾

Serializer Output Voltage

Junction Temperature

+4.0

V

V_DDIO+ 0.3

+2.75

V

+150

°C

(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(2) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(3) The maximum limit (VDDIO +0.3V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from

HIGH to LOW).

6.2 Handling Ratings

MIN

-65

MAX

+150

±8

UNIT

T_stg

Storage temperature range

Electrostatic discharge

°C

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011

Machine Model (MM)

±8

kV

V

V_(ESD)

±1.25

±250

±15

±1.25

±250

±15

Air Discharge

(DOUT+, DOUT-)

ESD Rating (IEC 61000-4-2,

powered-up only)

R_D= 330Ω, C_S= 150pF

Contact Discharge

(DOUT+, DOUT-)

±8

±15

±8

±15

±8

kV

Air Discharge

(DOUT+, DOUT-)

ESD Rating (ISO 10605)

R_D= 330Ω, C_S= 150pF/330pF

R_D= 2KΩ, C_S= 150pF/330pF

Contact Discharge

(DOUT+, DOUT-)

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN

3.0

NOM

3.3

MAX

UNIT

V

Supply Voltage (V_DD33

)

3.6

LVCMOS Supply Voltage (V_DDIO

)

3.0

3.3

V

OR

LVCMOS Supply Voltage (V_DDIO

1.71

−40

5

1.8

1.89

+105

85

V

Operating Free Air Temperature (T_A)

PCLK Frequency

+25

°C

MHz

mV_P-P

Supply Noise

100

7

DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

www.ti.com.cn

6.4 Thermal Information

WQFN

48 PINS

35

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

5.2

5.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

5.5

R_θJC(bot)

1.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾

(2) (3)

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

LVCMOS I/O DC SPECIFICATIONS

High Level Input

Voltage

V_IH

V_DDIO= 3.0 to 3.6V

2.0

V_DDIO

0.8

V

Low Level Input

Voltage

PDB

V_IL

V_DDIO= 3.0 to 3.6V

GND

I_IN

Input Current

V_IN= 0V or V_DDIO= 3.0 to 3.6V

V_DDIO= 3.0 to 3.6V

−10

±1

+10

μA

2.0

V_DDIO

V

High Level Input

Voltage

V_IH

0.65*

V_DDIO

V_DDIO= 1.71 to 1.89V

V_DDIO= 3.0 to 3.6V

V_DDIO= 1.71 to 1.89V

V_DDIO= 3.0

V_DDIO

0.8

V

DIN[23:0], HS,

VS, DE, PCLK,

I2S_CLK,

I2S_WC,

I2S_DA, I2S_DB

GND

Low Level Input

Voltage

V_IL

0.35*

V_DDIO

−10

±1

+10

μA

V

to 3.6V

V_IN= 0V or

I_IN

Input Current

V_DDIO

V_DDIO= 1.71

to 1.89V

V_DDIO= 3.0 to

2.4

V_DDIO

0.4

3.6V

High Level Output

Voltage

V_OH

I_OH= −4mA

V_DDIO= 1.71

V_DDIO- 0.45

GND

V

to 1.89V

V_DDIO= 3.0 to

V

3.6V

Low Level Output

Voltage

GPIO[3:0],

GPO_REG[8:4]

V_OL

I_OL= +4mA

V_DDIO= 1.71

GND

0.35

V

to 1.89V

Output Short Circuit

Current

I_OS

I_OZ

V_OUT= 0V

−50

mA

μA

TRI-STATE® Output

Current

V_OUT= 0V or V_DDIO, PDB = L,

−10

+10

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V_DD= 3.3 V, T_A= +25 °C, and at the Recommended Operating Conditions at

the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V_ODand ΔV_OD, which are differential voltages.

8

DS90UB925Q-Q1

www.ti.com.cn

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

DC Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.^{(1) (2) (3)}

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

FPD-LINK III CML DRIVER DC SPECIFICATIONS

Differential Output

Voltage

(DOUT+) – (DOUT-)

R_L= 100Ω,

See Figure 1

V_ODp-p

ΔV_OD

V_OS

1160

1250

1

1340

50

mV_p-p

mV

V

Output Voltage

Unbalance

2.5-

0.25*V_ODp-p

Offset Voltage –

Single-ended

R_L= 100Ω,

See Figure 1

(TYP)

DOUT+, DOUT-

Offset Voltage

Unbalance

Single-ended

ΔV_OS

1

50

62

mV

mA

Ω

Output Short Circuit

Current

I_OS

DOUT+/- = 0V, PDB = L or H

−38

Internal Termination

Resistor - Single

ended

R_T

40

52

SERIAL CONTROL BUS

0.7*

V_DD33

V_IH

V_IL

Input High Level

SDA and SCL

V_DD33

V

Input Low Level

Voltage

0.3*

V_DD33

GND

V_HY

V_OL

I_in

Input Hysteresis

>50

<5

mV

V

SDA, I_OL= 1.25 mA

0

0.36

10

SDA or SCL, V_IN= V_DD33or GND

SDA or SCL

-10

µA

pF

C_in

Input Capacitance

SUPPLY CURRENT

I_DD1

V_DD33= 3.6V

V_DD33

V_DDIO

V_DD33

V_DDIO

V_DD33

V_DDIO

148

90

1

170

180

1.6

2.4

150

2

mA

μA

mA

μA

mA

μA

Supply Current

(includes load current) Pattern,

R_L= 100Ω, f = 85MHz See Figure 2

Checker Board

V_DDIO= 3.6V

V_DDIO= 1.89V

V_DD33= 3.6V

V_DDIO= 3.6V

V_DDIO= 1.89V

V_DD33= 3.6V

V_DDIO= 3.6V

V_DDIO= 1.89V

I_DDIO1

I_DDS1

I_DDIOS1

I_DDS2

1.2

65

55

1

Supply Current

Remote Auto Power

Down Mode

0x01[7] = 1,

deserializer is

powered down

PDB = L, All

Supply Current Power LVCMOS inputs

Down

65

50

150

are floating or

tied to GND

I_DDIOS2

9

DS90UB925Q-Q1

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MAX UNIT

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾

(2) (3)

PARAMETER

GPIO BIT RATE

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

Forward Channel Bit Rate

Back Channel Bit Rate

f = 5 – 85

MHz

GPIO[3:0]

0.25* f

75

Mbps

kbps

B_R

See^{(4) (5)}

RECOMMENDED TIMING FOR PCLK

t_TCP

t_CIH

t_CIL

PCLK Period

11.76

0.4*T

4.0

T

0.5*T

200

0.6*T

ns

PCLK Input High Time

PCLK Input Low Time

PCLK Input Transition Time,

See^{(4) (5)}

PCLK

f = 5 MHz

(4) (5)

t_CLKT

t_IJIT

See Figure 3

f = 85 MHz

0.5

PCLK Input Jitter Tolerance,

f / 40 < Jitter Freq < f / 20^{(4) (6)}

f = 5 –

78MHz

0.4

0.6

UI

Bit Error Rate ≤10^–10

(7)

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V_DD= 3.3 V, T_A= +25 °C, and at the Recommended Operating Conditions at

the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V_ODand ΔV_OD, which are differential voltages.

(4) Specification is ensured by characterization and is not tested in production.

(5) Specification is ensured by design and is not tested in production.

(6) Jitter Frequency is specified in conjunction with DS90UB926 PLL bandwidth.

(7) UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.

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6.7 Recommended Timing for the Serial Control Bus

Over 3.3V supply and temperature ranges unless otherwise specified.

MIN

0

TYP

MAX UNIT

f_SCL

Standard Mode

Fast Mode

100 kHz

SCL Clock Frequency

SCL Low Period

0

400 kHz

t_LOW

Standard Mode

Fast Mode

4.7

1.3

4.0

0.6

4.0

µs

t_HIGH

Standard Mode

Fast Mode

SCL High Period

t_HD;STA

Hold time for a start or a

repeated start condition,

See Figure 8

Standard Mode

Fast Mode

0.6

4.7

0.6

µs

t_SU:STA

Set Up time for a start or a

repeated start condition,

See Figure 8

Standard Mode

Fast Mode

t_HD;DAT

t_SU;DAT

t_SU;STO

Standard Mode

Fast Mode

0

0.615

0.56

3.45

0.9

µs

ns

µs

Data Hold Time,

See Figure 8

Standard Mode

Fast Mode

250

100

4.0

Data Set Up Time,

See Figure 8

0.56

Set Up Time for STOP

Condition,

See Figure 8

Standard Mode

Fast Mode

0.6

4.7

1.3

µs

Bus Free Time

Between STOP and START,

See Figure 8

Standard Mode

Fast Mode

t_BUF

Standard Mode

Fast Mode

430

20

1000

300

ns

SCL and SDA Rise Time,

See Figure 8

t_r

Standard Mode

Fast mode

SCL and SDA Fall Time,

See Figure 8

t_f

20

t_sp

input Filter

50

DOUT+

0.1 PF

Differential probe

Input Impedance û 100

k:

30

DIN[23:0],

HS,VS,DE,

I2S

SCOPE

BW û 4 GHz

100:

D

C

L

ú 0.5 pF

DOUT-

BW û 3.5 GHz

PCLK

D

OUT

-

V

OD-

Single Ended

V

OD

V

OD+

D

OUT

+

V

OS

0V

|

V

OD+

(D +) - (D -)

OUT OUT

0V

Differential

V

OD-

Figure 1. Serializer V_ODDC Output

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V

DDIO

PCLK

GND

V

DDIO

DIN[n] (odd),

VS, HS

GND

V

DDIO

DIN[n] (even),

DE

GND

Figure 2. Checkboard Data Pattern

VDDIO

80%

PCLK

20%

CLKT

0V

t

CLKT

t

Figure 3. Serializer Input Clock Transition Time

80%

Differential

Signal

V

diff

= 0V

20%

t

HLT

LHT

Figure 4. Serializer CML Output Load and Transition Time

t

TCP

V

/2

V

DDIO

/2

V

DDIO

/2

PCLK

DDIO

t

DIH

DIS

V

DDIO

DIN[23:0],

HS,VS,DE

V

/2

DDIO

Setup

Hold

0V

Figure 5. Serializer Setup and Hold Times

PDB

1/2 V

DDIO

PCLK

"X"

active

t

PLD

DOUT

(Diff.)

Driver On

Driver OFF, V

OD

= 0V

Figure 6. Serializer Lock Time

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t

DJIT

VOD (+)

DOUT

(Diff.)

EYE OPENING

0V

VOD (-)

t

(1 UI)

BIT

Figure 7. Serializer CML Output Jitter

SDA

SCL

t

BUF

t

f

t

HD;STA

t

r

LOW

t

SP

t

f

r

t

HD;STA

SU;STA

t

SU;STO

t

HIGH

t

SU;DAT

HD;DAT

STOP START

START

REPEATED

START

Figure 8. Serial Control Bus Timing Diagram

6.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX UNIT

t_LHT

t_HLT

t_DIS

CML Output Low-to-High

Transition Time

80

130

ps

DOUT+,

DOUT-

See Figure 4

CML Output High-to-Low

Transition Time

ps

ns

Data Input Setup to PCLK

Data Input Hold from PCLK

R[7:0],

G[7:0],

B[7:0], HS,

VS, DE,

PCLK,

I2S_CLK,

I2S_WC,

I2S_DA

2.0

See Figure 5

See Figure 6

t_DIH

ns

(1)

t_PLD

t_SD

f = 15 -

45MHz

Serializer PLL Lock Time

Delay — Latency

131*T

145*T

ns

f = 15 -

45MHz

Output Total Jitter,

R_L= 100Ω

f = 45MHz

DOUT+,

DOUT-

t_TJIT

Bit Error Rate ≥10^-10

0.25

0.30

UI

(2) (3) (4)

Figure 7

(1) tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK

(2) Specification is ensured by characterization and is not tested in production.

(3) Specification is ensured by design and is not tested in production.

(4) UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.

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6.9 Typical Charateristics

78 MHz TX

Pixel Clock

Input

(2 V/DIV)

78 MHz RX

Pixel Clock

Output

(2 V/DIV)

Time (1.25 ns/DIV)

Time (10 ns/DIV)

Note: On the rising edge of each clock period, the CML driver outputs

a low Stop bit, high Start bit, and 33 DC-scrambled data bits.

Figure 9. Serializer CML Driver Output with 78 MHz TX Pixel

Clock

Figure 10. Comparison of Deserializer LVCMOS RX PCLK

Output Locked to a 78 MHz TX PCLK

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7 Detailed Description

7.1 Overview

The DS90UB925Q-Q1 serializer transmits a 35-bit symbol over a single serial FPD-Link III pair operating up to

2.975 Gbps line rate. The serial stream contains an embedded clock, video control signals and DC-balanced

video data and audio data which enhance signal quality to support AC coupling. The serializer is intended for use

with the DS90UB926Q-Q1 deserializer, but is also backward compatible with DS90UR906Q or DS90UR908Q

FPD-Link II deserializer.

The DS90UB925Q-Q1 serializer and DS90UB926Q-Q1 deserializer incorporate an I²C compatible interface. The

I²C compatible interface allows programming of serializer or deserializer devices from a local host controller. In

addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between

serializer/deserializer as well as remote I²C slave devices.

The bidirectional control channel is implemented via embedded signaling in the high-speed forward channel

(serializer to deserializer) as well as lower speed signaling in the reverse channel (deserializer to serializer).

Through this interface, the BCC provides a mechanism to bridge I²C transactions across the serial link from one

I²C bus to another. The implementation allows for arbitration with other I²C compatible masters at either side of

the serial link.

There are two operating modes available on DS90UB925Q-Q1, display mode and camera mode. In display

mode, I²C transactions originate from the host controller attached to the serializer and target either the

deserializer or an I²C slave attached to the deserializer. Transactions are detected by the I²C slave in the

serializer and forwarded to the I²C master in the deserializer. Similarly, in camera mode, I²C transactions

originate from a controller attached to the deserializer and target either the serializer or an I²C slave attached to

the serializer. Transactions are detected by the I²C slave in the deserializer and forwarded to the I²C master in

the serializer.

7.2 Functional Block Diagram

REGULATOR

CMF

24

DIN [23:0]

HS

VS

D

+

-

OUT

DE

D

PCLK

OUT

I2S_CLK

I2S_WC

I2S_DA

3

PDB

MODE_SEL

INTB

PLL

Timing

and

Control

SDA

SCL

IDx

DS90UB925Q-Q1

Serializer

7.3 Feature Description

7.3.1 High Speed Forward Channel Data Transfer

The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or

YUV data, sync signals, I²C, and I2S audio transmitted from Serializer to Deserializer. Figure 11 illustrates the

serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link.

Data is randomized, balanced and scrambled.

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Feature Description (continued)

C1

C0

Figure 11. FPD-Link III Serial Stream

The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps

maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.

7.3.2 Low Speed Back Channel Data Transfer

The Low-Speed Backward Channel (LS_BC) of the DS90UB925Q-Q1 provides bidirectional communication

between the display and host processor. The information is carried back from the Deserializer to the Serializer

per serial symbol. The back channel control data is transferred over the single serial link along with the high-

speed forward data, DC balance coding and embedded clock information. This architecture provides a backward

path across the serial link together with a high speed forward channel. The back channel contains the I²C, CRC

and 4 bits of standard GPIO information with 10 Mbps line rate.

7.3.3 Backward Compatible Mode

The DS90UB925Q-Q1 is also backward compatible to DS90UR906Q and DS90UR908Q FPD Link II

deserializers at 5-65 MHz of PCLK. It transmits 28-bits of data over a single serial FPD-Link II pair operating at

the line rate of 140 Mbps to 1.82 Gbps. The backward configuration mode can be set via MODE_SEL pin

(Table 4) or the configuration register (Table 6). Note: frequency range = 15 – 65MHz when LFMODE = 0 and

frequency range = 5 – <15MHz when LFMODE = 1.

7.3.4 Common Mode Filter Pin (CMF)

The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin

for additional common-mode filtering of the differential pair. This can be useful in high noise environments for

additional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.

7.3.5 Video Control Signal Filter

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following

restrictions:

•

Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are

transmitted, the transition pulse must be 3 PCLK or longer.

Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are

transmitted, no restriction on minimum transition pulse.

VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal

can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency

noise on the control signals. See Figure 12.

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Feature Description (continued)

PCLK

IN

HS/VS/DE

IN

Latency

PCLK

OUT

Pulses 1 or 2

PCLKs wide

HS/VS/DE

OUT

Filetered OUT

Figure 12. Video Control Signal Filter Waveform

7.3.6 EMI Reduction Features

7.3.6.1 Input SSC Tolerance (SSCT)

The DS90UB925Q-Q1 serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile

up to ±2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–85 MHz, from a host source.

7.3.7 LVCMOS V_DDIOOption

1.8 V or 3.3 V Inputs and Outputs are powered from a separate V_DDIOsupply to offer compatibility with external

system interface signals.

NOTE

When configuring the V_DDIOpower supplies, all the single-ended data and control input

pins for device need to scale together with the same operating V_DDIOlevels.

7.3.8 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the

host or through the V_DDIO, where V_DDIO= 3.0V to 3.6V or V_DD33. To save power disable the link when the display

is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after V_DD33and V_DDIO

have reached final levels; no external components are required. In the case of driven by the V_DDIO= 3.0V to 3.6V

or V_DD33directly, a 10 kohm resistor to the V_DDIO= 3.0V to 3.6V or V_DD33, and a >10uF capacitor to the ground

are required (See Figure 23).

7.3.9 Remote Auto Power Down Mode

The Serializer features a remote auto power down mode. During the power down mode of the pairing

deserializer, the Serializer enters the remote auto power down mode. In this mode, the power dissipation of the

Serializer is reduced significantly. When the Deserializer is powered up, the Serializer enters the normal power

on mode automatically. This feature is enabled through the register bit 0x01[7] Table 6.

7.3.10 Input PCLK Loss Detect

The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A

clock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again,

the serializer will then lock to the incoming PCLK. Note – when PCLK is lost, the Serial Control Bus Registers

values are still RETAINED.

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Feature Description (continued)

7.3.11 Serial Link Fault Detect

The serial link fault detection is able to detect any of following seven (7) conditions:

1. cable open

2. “+” to “-“ short

3. “+” short to GND

4. “-“ short to GND

5. “+” short to battery

6. “-“ short to battery

7. Cable is linked correctly

If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address

0x0C Table 6.

7.3.12 Pixel Clock Edge Select (RFB)

The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines

the edge that the data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFB

is LOW (‘0’), data is latched on the Falling edge of the PCLK.

7.3.13 Low Frequency Optimization (LFMODE)

The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency

of the serializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is

High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed,

a PDB reset is required.

7.3.14 Interrupt Pin — Functional Description And Usage (INTB)

1. On DS90UB925, set register 0xC6[5] = 1 and 0xC6[0] = 1

2. DS90UB926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.

3. DS90UB925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an

interrupt condition.

4. External controller detects INTB = LOW; to determine interrupt source, read ISR register .

5. A read to ISR will clear the interrupt at the DS90UB925, releasing INTB.

6. The external controller typically must then access the remote device to determine downstream interrupt

source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the

INTB_IN (pin 16) on the DS90UB926Q-Q1. The system is now ready to return to step (1) at next falling edge

of INTB_IN.

7.3.15 Internal Pattern Generation

The DS90UB925Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and

debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and

repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down

mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test

pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application

Note AN-2198 (SNLA132).

7.3.16 GPIO[3:0] and GPO_REG[8:4]

In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB925Q-Q1 can be used as the

general purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) application.

7.3.16.1 GPIO[3:0] Enable Sequence

See Table 1 for the GPIO enable sequencing.

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Feature Description (continued)

Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UB925Q-Q1 only.

DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.

Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB925Q-Q1, then write 0x05 to

address 0x1F on DS90UB926Q-Q1.

Table 1. GPIO Enable Sequencing Table

#

DESCRIPTION

DEVICE

FORWARD CHANNEL

0x12 = 0x04

BACK CHANNEL

0x12 = 0x04

1

Enable 18-bit

mode

DS90UB925Q-Q1

DS90UB926Q-Q1

DS90UB925Q-Q1

DS90UB926Q-Q1

DS90UB925Q-Q1

DS90UB926Q-Q1

DS90UB925Q-Q1

DS90UB926Q-Q1

DS90UB925Q-Q1

DS90UB926Q-Q1

Auto Load from DS90UB925Q-Q1

0x0F = 0x03

Auto Load from DS90UB925Q-Q1

0x0F = 0x05

2

3

4

5

GPIO3

GPIO2

GPIO1

GPIO0

0x1F = 0x05

0x1F = 0x03

0x0E = 0x30

0x0E = 0x50

0x1E = 0x50

0x1E = 0x30

0x0E = 0x03

0x0E = 0x05

0x1E = 0x05

0x1E = 0x03

0x0D = 0x93

0x0D = 0x95

0x1D = 0x95

0x1D = 0x93

7.3.16.2 GPO_REG[8:4] Enable Sequence

GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 2

for the GPO_REG enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UB925Q-Q1 only.

DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.

Step 2: To enable GPO_REG8 outputs an “1”, write 0x90 to address 0x11 on DS90UB925Q.

Table 2. GPO_REG Enable Sequencing Table

#

1

2

DESCRIPTION

Enable 18-bit mode

GPO_REG8

DEVICE

LOCAL ACCESS

0x12 = 0x04

0x11 = 0x90

0x11 = 0x10

0x11 = 0x09

0x11 = 0x01

0x10 = 0x90

0x10 = 0x10

0x10 = 0x09

0x10 = 0x01

0x0F = 0x90

0x0F = 0x10

LOCAL OUTPUT

DS90UB925Q-Q1

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

3

4

5

6

GPO_REG7

GPO_REG6

GPO_REG5

GPO_REG4

DS90UB925Q-Q1

7.3.17 I2S Transmitting

In normal 24-bit RGB operation mode, the DS90UB925Q-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC

and I2S_DA. The optionally packetized audio information can be transmitted during the video blanking (data

island transport) or during active video (forward channel frame transport). Note: The bit rates of any I2S bits must

maintain one fourth of the PCLK rate.

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7.3.17.1 Secondary I2S Channel

In I2S Channel B operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio in

addition to the 3–bit of I2S. The I2S_DB input must be synchronized to I2S_CLK and aligned with I2S_DA and

I2S_WC at the input to the serializer. This operation mode is enabled through either the MODE_SEL pin

(Table 4) or through the register bit 0x12[0] (Table 6).

Table 3 covers the range of I2S sample rates.

Table 3. Audio Interface Frequencies

SAMPLE RATE (kHz)

I2S DATA WORD SIZE (BITS)

I2S CLK (MHz)

1.024

32

44.1

48

16

24

32

1.411

1.536

96

3.072

192

32

6.144

1.536

44.1

48

2.117

2.304

96

4.608

192

32

9.216

2.048

44.1

48

2.822

3.072

96

6.144

192

12.288

7.3.18 Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the

low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for

system diagnostics. Note: BIST is not available in backwards compatible mode.

7.3.18.1 BIST Configuration and Status

The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or

configuration register (Table 6) through the deserializer. When LFMODE = 0, the pin based configuration defaults

to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can

select the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the

pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.

When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the

Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test

pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to

35 bit errors.

The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset

(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS

indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to

the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the

connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the

deserializer is locked or unlocked, the lock status can be read in the register. See Table 6.

7.3.18.1.1 Sample BIST Sequence

See Figure 13 for the BIST mode flow diagram.

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Step 1: For the DS90UB925Q-Q1 and DS90UB926Q-Q1 FPD-Link III chipset, BIST Mode is enabled via the

BISTEN pin of DS90UB926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through BISTC

pin.

Step 2: The DS90UB925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero

pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the

deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and

BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low

for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to

determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the

data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there

was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST

is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the

BISTEN signal.

Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 14 shows the

waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple

errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data

transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,

reducing signal condition enhancements ( Rx Equalization).

Normal

Step 1: DES in BIST

BIST

Wait

Step 2: Wait, SER in BIST

BIST

start

Step 3: DES in Normal Mode -

check PASS

BIST

stop

Step 4: DES/SER in Normal

Figure 13. Bist Mode Flow Diagram

7.3.18.2 Forward Channel And Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero

pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to

the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-

zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The

deserializer then outputs a SSO pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as

indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The

register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the

functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in

BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.

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BISTEN

(DES)

PCLK

(RFB = L)

ROUT[23:0]

HS, VS, DE

DATA

(internal)

PASS

Prior Result

PASS

FAIL

X = bit error(s)

DATA

(internal)

X

PASS

BIST

Result

Held

Normal

SSO

Normal

BIST Test

BIST Duration

Figure 14. Bist Waveforms

7.4 Device Functional Modes

7.4.1 Configuration Select (MODE_SEL)

Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-

up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL

input (V_R4) and V_DD33to select one of the other 10 possible selected modes. See Figure 15 and Table 4.

V

DD33

R

3

V

R4

MODE_SEL

SER

R

4

Figure 15. MODE_SEL Connection Diagram

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Device Functional Modes (continued)

Table 4. Configuration Select (MODE_SEL)

#

IDEAL

RATIO

V_R4/V_DD33

IdeAl V_R4

(V)

SUGGESTED

RESISTOR R3

kΩ (1% tol)

SUGGESTED

RESISTOR R4

kΩ (1% tol)

LFMODE

REPEATER

BACKWARD I2S Channel

COMPATIBL

E

B

(18–bit

Mode)

1

2

3

4

5

6

7

8

0

Open

255

243

237

196

169

137

90.9

40.2 or Any

49.9

L

H

L

0.164

0.221

0.285

0.359

0.453

0.539

0.728

0.541

0.729

0.941

1.185

1.495

1.779

2.402

69.8

L

H

L

95.3

H

L

110

L

H

L

140

H

L

158

L

H^*

H

L

243

LFMODE:

L = frequency range is 15 – 85 MHz (Default)

H = frequency range is 5 – <15 MHz

Repeater:

L = Repeater OFF (Default)

H = Repeater ON

Backward Compatible:

L = Backward Compatible is OFF (Default)

H = Backward Compatible is ON; DES = DS90UR906Q or DS90UR916Q or DS90UR908Q

– frequency range = 15 - 65 MHz when LFMODE = 0

– frequency range = 5 - <15 MHz when LFMODE = 1

I2S Channel B:

L = I2S Channel B is OFF, Normal 24-bit RGB Mode (Default)

H = I2S Channel B is ON, 18-bit RGB Mode with I2S_DB Enabled. Note: use of GPIO(s) on unused inputs must be enabled by register.

7.4.2 Repeater Application

The DS90UB925Q-Q1 and DS90UB926Q-Q1 can be configured to extend data transmission over multiple links

to multiple display devices. Setting the devices into repeater mode provides a mechanism for transmitting to all

receivers in the system.

7.4.2.1 Repeater Configuration

In the repeater application, in this document, the DS90UB925Q-Q1 is referred to as the Transmitter or transmit

port (TX), and the DS90UB926Q-Q1 is referred to as the Receiver (RX). Figure 16 shows the maximum

configuration supported for Repeater implementations using the DS90UB925Q-Q1 (TX) and DS90UB926Q-Q1

(RX). Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver.

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1:3 Repeater

Display

RX

TX

RX

TX

Source

TX

RX

TX

Display

RX

1:3 Repeater

Display

RX

TX

RX

Display

RX

1:3 Repeater

Display

RX

TX

RX

Display

RX

Figure 16. Maximum Repeater Application

In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C

communications upstream or downstream to any I2C device within the system. This includes a mechanism for

assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.

At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel

RGB video data, HS/VS/DE control signals and, optionally, packetized audio data (transported during video

blanking intervals). Alternatively, the I2S audio interface may be used to transport digital audio data between

receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the

Receiver and is received by the Transmitter.

Figure 17 provides more detailed block diagram of a 1:2 repeater configuration.

DS90UB925Q-Q1

Transmitter

downstream

Receiver

or

Repeater

I2C

Slave

I2C

Master

upstream

Transmitter

Parallel

LVCMOS

DS90UB925Q-Q1

Transmitter

DS90UB926Q-Q1

Receiver

I2S Audio

downstream

Receiver

or

I2C

Slave

Repeater

FPD-Link III interfaces

Figure 17. 1:2 Repeater Configuration

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ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

7.4.2.2 Repeater Connections

The Repeater requires the following connections between the Receiver and each Transmitter Figure 18.

1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).

2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to V_DD33with 4.7 kΩ resistors.

3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.

4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.

5. MODE_SEL pin – All Transmitter and Receiver must be set into the Repeater Mode.

6. Interrupt pin – Connect DS90UB926Q-Q1 INTB_IN pin to DS90UB925Q-Q1 INTB pin. The signal must be

pulled up to V_DDIO

.

DS90UB926Q-Q1

DS90UB925Q-Q1

RGB[7:0) / ROUT[23:0]

DIN[23:0] / RGB[7:0]

DE

VS

HS

DE

VS

HS

I2S_CLK

I2S_WC

I2S_DA

I2S_CLK

I2S_WC

I2S_DA

VDD33

Optional

VDDIO

MODE_SEL

Optional

INTB_IN

INTB

VDD33

ID[x]

SDA

SCL

Figure 18. Repeater Connection Diagram

7.5 Programming

The DS90UB925Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. Multiple

serializer devices may share the serial control bus since 9 device addresses are supported. Device address is

set via R₁and R₂values on IDx pin. See Figure 19.

The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /

Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external

pull-up resistor to V_DD33. For most applications a 4.7 k pull-up resistor to V_DD33may be used. The resistor value

may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven

Low.

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Programming (continued)

V_DD33

R₁

V_DD33

VR2

IDx

4.7k

R₂

HOST

or

SER

or

Salve

DES

SCL

SDA

SCL

SDA

To other

Devices

Figure 19. Serial Control Bus Connection

The configuration pin is the IDx pin. This pin sets one of 9 possible device addresses. A pull-up resistor and a

pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (V_R2) and V_DD33to

select one of the other 9 possible addresses. See Table 5.

Table 5. Serial Control Bus Addresses for IDx

SUGGESTED

RESISTOR

R1 kΩ (1% tol)

SUGGESTED

RESISTOR

R2 kΩ (1% tol)

IDEAL RATIO

V_R2/ V_DD33

IDEAL V_R2

(V)

ADDRESS 8'b

APPENDED

#

ADDRESS 7'b

1

2

3

4

5

6

7

8

9

0

Open

294

280

137

118

115

102

115

90.9

40.2 or Any

40.2

0x0C

0x0D

0x0E

0x0F

0x10

0x13

0x14

0x15

0x1B

0x18

0x1A

0x1C

0x1E

0x20

0x26

0x28

0x2A

0x36

0.121

0.152

0.180

0.208

0.303

0.345

0.389

0.727

0.399

0.502

0.594

0.685

0.999

1.137

1.284

2.399

49.9

30.1

30.9

49.9

53.6

73.2

243

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when

SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See

Figure 20.

SDA

SCL

S

P

START condition, or

STOP condition

START repeat condition

Figure 20. Start and Stop Conditions

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To communicate with a remote device, the host controller (master) sends the slave address and listens for a

response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is

addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't

match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs

also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after

every data byte is successfully received. When the master is reading data, the master ACKs after every data

byte is received to let the slave know it wants to receive another data byte. When the master wants to stop

reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus

begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop

condition. A READ is shown in Figure 21 and a WRITE is shown in Figure 22.

If the Serial Bus is not required, the three pins may be left open (NC).

Register Address

Slave Address

Data

a

c

k

a

c

k

a

c

k

a

c

k

A

2

A

1

A

0

A

2

A

1

A

0

S

1

P

Figure 21. Serial Control Bus — Read

Register Address

Slave Address

Data

a

c

a

c

k

a

c

k

A

2

A

1

A

0

S

P

k

Figure 22. Serial Control Bus — Write

Table 6. Serial Control Bus Registers

7.6 Register Maps

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

0

0x00 I2C Device ID

7:1

0

RW

Device ID

ID Setting

7–bit address of Serializer

I2C ID Setting

1: Register I2C Device ID (Overrides IDx pin)

0: Device ID is from IDx pin

1

0x01 Reset

7

RW

0x00

Remote

Remote Auto Power Down

Auto Power 1: Power down when no Bidirectional Control Channel

Down

link is detected

0: Do not power down when no Bidirectional Control

Channel link is detected

6:2

1

Reserved

RW

Digital

RESET1

Reset the entire digital block including registers

This bit is self-clearing.

1: Reset

0: Normal operation

0

Digital

RESET0

Reset the entire digital block except registers

This bit is self-clearing

1: Reset

0: Normal operation

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Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

3

0x03 Configuration

[0]

7

RW

0xD2

Back

channel

CRC

Back Channel Check Enable

1: Enable

0: Disable

Checker

Enable

6

5

Reserved

RW

I2C Remote Automatically Acknowledge I2C Remote Write When

Write Auto enabled, I2C writes to the Deserializer (or any remote

Acknowledg I2C Slave, if I2C PASS ALL is enabled) are

e

immediately acknowledged without waiting for the

Deserializer to acknowledge the write. This allows

higher throughput on the I2C bus

1: Enable

0: Disable

4

3

RW

Filter

Enable

HS, VS, DE two clock filter When enabled, pulses less

than two full PCLK cycles on the DE, HS, and VS

inputs will be rejected

1: Filtering enable

0: Filtering disable

I2C Pass-

through

I2C Pass-Through Mode

1: Pass-Through Enabled

0: Pass-Through Disabled

2

1

Reserved

RW

PCLK Auto Switch over to internal OSC in the absence of PCLK

1: Enable auto-switch

0: Disable auto-switch

0

TRFB

Pixel Clock Edge Select

1: Parallel Interface Data is strobed on the Rising Clock

Edge.

0: Parallel Interface Data is strobed on the Falling

Clock Edge.

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Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

4

0x04 Configuration

[1]

7

RW

0x80

Failsafe

State

Input Failsafe State

1: Failsafe to Low

0: Failsafe to High

6

5

Reserved

RW

CRC Error

Reset

Clear back channel CRC Error Counters

This bit is NOT self-clearing

1: Clear Counters

0: Normal Operation

4

3

RGB

DE Gate

1: Gate RGB data with DE in Backward Compatibility

mode and with Non-HDCP Deserializer

0: Pass RGB data independent of DE in Backward

Compatibility mode and Non-HDCP operation (default)

RW

Backward

Backward Compatible (BC) mode set by MODE_SEL

Compatible pin or register

select by

pin or

1: BC is set by register bit. Use register bit reg_0x04[2]

to set BC Mode

register

control

0: BC is set by MODE_SEL pin.

2

1

0

RW

Backward

Backward compatible (BC) mode to DS90UR906Q or

Compatible DS90UR908Q, if reg_0x04[3] = 1

Mode

Select

1: Backward compatible with DS90UR906Q or

DS90UR908Q

0: Backward Compatible is OFF (default)

LFMODE

select by

pin or

register

control

Frequency range is set by MODE_SEL pin or register

1: Frequency range is set by register. Use register bit

reg_0x04[0] to set LFMODE

0: Frequency range is set by MODE_SEL pin.

RW

LFMODE

Frequency range select

1: PCLK range = 5MHz - <15 MHz), if reg_0x04[1] = 1

0: PCLK range = 15MHz - 85MHz (default)

5

0x05 I2C Control

7:5

4:3

0x00

Reserved

SDA Output SDA output delay

Delay Configures output delay on the SDA output. Setting this

value will increase output delay in units of 40ns.

Nominal output delay values for SCL to SDA are

00: 240ns

01: 280ns

10: 320ns

11: 360ns

2

RW

Local Write Disable remote writes to local registers

Disable

Setting the bit to a 1 prevents remote writes to local

device registers from across the control channel. It

prevents writes to the Serializer registers from an I2C

master attached to the Deserializer.

Setting this bit does not affect remote access to I2C

slaves at the Serializer

1

0

RW

I2C Bus

Timer

Speedup

Speed up I2C bus watchdog timer

1: Watchdog timer expires after ~50 ms.

0: Watchdog Timer expires after ~1 s

I2C Bus

timer

Disable

Disable I2C bus watchdog timer

When the I2C watchdog timer may be used to detect

when the I2C bus is free or hung up following an invalid

termination of a transaction.

If SDA is high and no signalling occurs for ~1 s, the I2C

bus assumes to be free. If SDA is low and no signaling

occurs, the device attempts to clear the bus by driving

9 clocks on SCL

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Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

6

0x06 DES ID

7:1

RW

0x00

DES Device 7-bit Deserializer Device ID

ID

Configures the I2C Slave ID of the remote Deserializer.

A value of 0 in this field disables I2C access to the

remote Deserializer. This field is automatically

configured by the Bidirectional Control Channel once

RX Lock has been detected. Software may overwrite

this value, but should also assert the FREEZE DEVICE

ID bit to prevent overwriting by the Bidirectional Control

Channel.

0

RW

Device ID

Frozen

Freeze Deserializer Device ID

Prevents autoloading of the Deserializer Device ID by

the Bidirectional Control Channel. The ID will be frozen

at the value written.

7

8

0x07 Slave ID

7:1

0x00

Slave

Device ID

7-bit Remote Slave Device ID

Configures the physical I2C address of the remote I2C

Slave device attached to the remote Deserializer. If an

I2C transaction is addressed to the Slave Device Alias

ID, the transaction will be remapped to this address

before passing the transaction across the Bidirectional

Control Channel to the Deserializer

0

Reserved

0x08 Slave Alias

7:1

RW

Slave

7-bit Remote Slave Device Alias ID

Device

Alias ID

Assigns an Alias ID to an I2C Slave device attached to

the remote Deserializer. The transaction will be

remapped to the address specified in the Slave ID

register. A value of 0 in this field disables access to the

remote I2C Slave.

0

Reserved

10

11

12

0x0A CRC Errors

0x0B

7:0

R

0x00

CRC Error

LSB

Number of back channel CRC errors – 8 least

significant bits

7:0

CRC Error

MSB

Number of back channel CRC errors – 8 most

significant bits

0x0C General Status

7:4

3

Reserved

R

BIST CRC

Error

Back channel CRC error during BIST communication

with Deserializer.

The bit is cleared upon loss of link, restart of BIST, or

assertion of CRC ERROR RESET in register 0x04.

2

1

R

PCLK

Detect

PCLK Status

1: Valid PCLK detected

0: Valid PCLK not detected

DES Error

Back channel CRC error during communication with

Deserializer.

The bit is cleared upon loss of link or assertion of CRC

ERROR RESET in register 0x04.

0

R

LINK Detect LINK Status

1: Cable link detected

0: Cable link not detected (Fault Condition)

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Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

7:4

FUNCTION

DESCRIPTION

13

0x0D Revision ID and

GPIO0

R

0xA0

Rev-ID

Revision ID: 1010

Production Device

Configuration

3

RW

GPIO0

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO

function is enabled, the local GPIO direction is Output,

and remote GPIO control is disabled.

2

RW

GPIO0

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer. The

GPIO pin will be an output, and the value is received

from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

1

0

7

RW

GPIO0

Direction

Local GPIO Direction

1: Input

0: Output

GPIO0

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

14

0x0E GPIO2 and

GPIO1

0x00

GPIO2

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO

function is enabled, the local GPIO direction is Output,

and remote GPIO control is disabled.

Configurations

6

RW

GPIO2

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer. The

GPIO pin will be an output, and the value is received

from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

5

4

3

RW

GPIO2

Direction

Local GPIO Direction

1: Input

0: Output

GPIO2

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

GPIO1

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO

function is enabled, the local GPIO direction is Output,

and remote GPIO control is disabled.

2

RW

GPIO1

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer. The

GPIO pin will be an output, and the value is received

from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

1

0

RW

GPIO1

Direction

Local GPIO Direction

1: Input

0: Output

GPIO1

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

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Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

15

0x0F GPO_REG4

and GPIO3

7

RW

0x00

GPO_REG Local GPO_REG4 output value

4 Output

Value

This value is output on the GPO pin when the GPO

function is enabled.

Configurations

(The local GPO direction is Output, and remote GPO

control is disabled)

6:5

4

Reserved

RW

GPO_REG GPO_REG4 function enable

4 Enable

1: Enable GPO operation

0: Enable normal operation

3

2

GPIO3

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO

function is enabled, the local GPIO direction is Output,

and remote GPIO control is disabled.

RW

GPIO3

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer. The

GPIO pin will be an output, and the value is received

from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

1

0

7

RW

GPIO3

Direction

Local GPIO Direction

1: Input

0: Output

GPIO3

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

16

0x10 GPO_REG6

and

0x00

GPO_REG Local GPO_REG6 output value

6 Output

Value

This value is output on the GPO pin when the GPO

function is enabled.

(The local GPO direction is Output, and remote GPO

control is disabled)

GPO_REG5

Configurations

6:5

4

Reserved

RW

GPO_REG GPO_REG6 function enable

6 Enable

1: Enable GPO operation

0: Enable normal operation

3

GPO_REG Local GPO_REG5 output value

5 Output

Value

This value is output on the GPO pin when the GPO

function is enabled, the local GPO direction is Output,

and remote GPO control is disabled.

2:1

0

Reserved

RW

GPO_REG GPO_REG5 function enable

5 Enable

1: Enable GPO operation

0: Enable normal operation

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Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

17

0x11 GPO_REG8

and

7

RW

0x00

GPO_REG Local GPO_REG8 output value

8 Output

Value

This value is output on the GPO pin when the GPO

function is enabled.

GPO_REG7

Configurations

(The local GPO direction is Output, and remote GPO

control is disabled)

6:5

4

Reserved

RW

GPO_REG GPO_REG8 function enable

8 Enable

1: Enable GPO operation

0: Enable normal operation

3

GPO_REG Local GPO_REG7 output value

7 Output

Value

This value is output on the GPO pin when the GPO

function is enabled, the local GPO direction is Output,

and remote GPO control is disabled.

2:1

0

Reserved

RW

GPO_REG GPO_REG7 function enable

7 Enable

1: Enable GPO operation

0: Enable normal operation

18

0x12 Data Path

Control

7:6

5

0x00

Reserved

DE Polarity The bit indicates the polarity of the DE (Data Enable)

signal.

1: DE is inverted (active low, idle high)

0: DE is positive (active high, idle low)

4

3

RW

I2S

Repeater

Regen

I2S Repeater Regeneration

1: Repeater regenerate I2S from I2S pins

0: Repeater pass through I2S from video pins

I2S

I2S Channel B Enable

Channel B

Enable

Override

1: Set I2S Channel B Enable from reg_12[0]

0: Set I2S Channel B Enable from MODE_SEL pin

2

RW

18-bit Video 18–bit video select

Select

1: Select 18-bit video mode

Note: use of GPIO(s) on unused inputs must be

enabled by register.

0: Select 24-bit video mode

1

0

RW

I2S

Transport

Select

I2S Transport Mode Slect

1: Enable I2S Data Forward Channel Frame Transport

0: Enable I2S Data Island Transport

I2S

I2S Channel B Enable

Channel B

Enable

1: Enable I2S Channel B on B1 input

0: I2S Channel B disabled

19

0x13 Mode Status

7:5

4

0x10

Reserved

R

MODE_SEL MODE_SEL Status

1: MODE_SEL decode circuit is completed

0: MODE_SEL decode circuit is not completed

3

2

1

0

Low

Frequency

Mode

Low Frequency Mode Status

1: Low frequency (5 - <15 MHz)

0: Normal frequency (15 - 85 MHz)

Repeater

Mode

Repeater Mode Status

1: Repeater mode ON

0: Repeater Mode OFF

Backward

Backward Compatible Mode Status

Compatible 1: Backward compatible ON

Mode

0: Backward compatible OFF

I2S

I2S Channel B Mode Status

Channel B

Mode

1: I2S Channel B ON, 18-bit RGB mode with I2S_DB

enabled

0: I2S Channel B OFF; normal 24-bit RGB mode

33

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www.ti.com.cn

Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

20

0x14 Oscillator Clock

Source and

7:3

2:1

0x00

Reserved

OSC Clock OSC Clock Source

RW

BIST Status

Source

(When LFMODE = 1, Oscillator = 12.5MHz ONLY)

00: External Pixel Clock

01: 33 MHz Oscillator

10: Reserved

11: 25 MHz Oscillator

0

R

BIST

Enable

Status

BIST status

1: Enabled

0: Disabled

22

0x16 BCC Watchdog

Control

7:1

RW

0xFE

Timer Value The watchdog timer allows termination of a control

channel transaction if it fails to complete within a

programmed amount of time.

This field sets the Bidirectional Control Channel

Watchdog Timeout value in units of 2 ms.

This field should not be set to 0

0

7

RW

Timer

Control

Disable Bidirectional Control Channel Watchdog Timer

1: Disables BCC Watchdog Timer operation

0: Enables BCC Watchdog Timer operation

23

0x17 I2C Control

0x5E

I2C Pass

All

I2C Control

1: Enable Forward Control Channel pass-through of all

I2C accesses to I2C Slave IDs that do not match the

Serializer I2C Slave ID.

0: Enable Forward Control Channel pass-through only

of I2C accesses to I2C Slave IDs matching either the

remote Deserializer Slave ID or the remote Slave ID.

6

Reserved

5:4

RW

SDA Hold

Time

Internal SDA Hold Time

Configures the amount of internal hold time provided

for the SDA input relative to the SCL input. Units are 40

ns

3:0

7:0

RW

I2C Filter

Depth

Configures the maximum width of glitch pulses on the

SCL and SDA inputs that will be rejected. Units are 5

ns

24

25

0x18 SCL High Time

0xA1

0xA5

SCL HIGH I2C Master SCL High Time

Time

This field configures the high pulse width of the SCL

output when the Serializer is the Master on the local

I2C bus. Units are 40 ns for the nominal oscillator clock

frequency. The default value is set to provide a

minimum 5us SCL high time with the internal oscillator

clock running at 32.5MHz rather than the nominal

25MHz.

0x19 SCL Low Time

7:0

RW

SCL LOW

Time

I2C SCL Low Time

This field configures the low pulse width of the SCL

output when the Serializer is the Master on the local

I2C bus. This value is also used as the SDA setup time

by the I2C Slave for providing data prior to releasing

SCL during accesses over the Bidirectional Control

Channel. Units are 40 ns for the nominal oscillator

clock frequency. The default value is set to provide a

minimum 5us SCL low time with the internal oscillator

clock running at 32.5MHz rather than the nominal

25MHz.

27

0x1B BIST BC Error

7:0

R

0x00

BIST Back BIST Mode Back Channel CRC Error Counter

Channel

CRC Error

Counter

This error counter is active only in the BIST mode. It

clears itself at the start of the BIST run.

34

DS90UB925Q-Q1

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ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

100

0x64 Pattern

Generator

Control

7:4

RW

0x10

Pattern

Generator

Select

Fixed Pattern Select

This field selects the pattern to output when in Fixed

Pattern Mode. Scaled patterns are evenly distributed

across the horizontal or vertical active regions. This

field is ignored when Auto-Scrolling Mode is enabled.

The following table shows the color selections in non-

inverted followed by inverted color mode

0000: Reserved

0001: White/Black

0010: Black/White

0011: Red/Cyan

0100: Green/Magenta

0101: Blue/Yellow

0110: Horizontally Scaled Black to White/White to

Black

0111: Horizontally Scaled Black to Red/Cyan to White

1000: Horizontally Scaled Black to Green/Magenta to

White

1001: Horizontally Scaled Black to Blue/Yellow to White

1010: Vertically Scaled Black to White/White to Black

1011: Vertically Scaled Black to Red/Cyan to White

1100: Vertically Scaled Black to Green/Magenta to

White

1101: Vertically Scaled Black to Blue/Yellow to White

1110: Custom color (or its inversion) configured in

PGRS, PGGS, PGBS registers

1111: Reserved

3:1

0

Reserved

RW

Pattern

Generator

Enable

Pattern Generator Enable

1: Enable Pattern Generator

0: Disable Pattern Generator

35

DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

www.ti.com.cn

Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

101

0x65 Pattern

Generator

Configuration

7:5

4

0x00

Reserved

RW

Pattern

Generator

18 Bits

18-bit Mode Select

1: Enable 18-bit color pattern generation. Scaled

patterns will have 64 levels of brightness and the R, G,

and B outputs use the six most significant color bits.

0: Enable 24-bit pattern generation. Scaled patterns

use 256 levels of brightness.

3

2

Pattern

Generator

External

Clock

Select External Clock Source

1: Selects the external pixel clock when using internal

timing.

0: Selects the internal divided clock when using internal

timing

This bit has no effect in external timing mode

(PATGEN_TSEL = 0).

RW

Pattern

Generator

Timing

Timing Select Control

1: The Pattern Generator creates its own video timing

as configured in the Pattern Generator Total Frame

Size, Active Frame Size. Horizontal Sync Width,

Vertical Sync Width, Horizontal Back Porch, Vertical

Back Porch, and Sync Configuration registers.

0: the Pattern Generator uses external video timing

from the pixel clock, Data Enable, Horizontal Sync, and

Vertical Sync signals.

Select

1

0

RW

Pattern

Generator

Enable Inverted Color Patterns

1: Invert the color output.

Color Invert 0: Do not invert the color output.

Pattern

Auto-Scroll Enable:

Generator

1: The Pattern Generator will automatically move to the

Auto-Scroll next enabled pattern after the number of frames

Enable

specified in the Pattern Generator Frame Time (PGFT)

register.

0: The Pattern Generator retains the current pattern.

102

0x66 Pattern

7:0

RW

0x00

Indirect

Address

This 8-bit field sets the indirect address for accesses to

indirectly-mapped registers. It should be written prior to

reading or writing the Pattern Generator Indirect Data

register.

Generator

Indirect Address

See AN-2198 (SNLA132).

103

198

0x67 Pattern

Indirect

Data

When writing to indirect registers, this register contains

the data to be written. When reading from indirect

registers, this register contains the read back value.

See AN-2198 (SNLA132)

Generator

Indirect Data

0xC6 ICR

7:6

5

Reserved

RW

IS_RX_INT Interrupt on Receiver interrupt

Enables interrupt on indication from the Receiver.

Allows propagation of interrupts from downstream

devices

4:1

0

Reserved

RW

R

INT Enable Global Interrupt Enable

Enables interrupt on the interrupt signal to the

controller.

199

0xC7 ISR

7:6

5

Reserved

IS RX INT

INT

Interrupt on Receiver interrupt

Receiver has indicated an interrupt request from down-

stream device

4:1

0

Reserved

R

Global Interrupt

Set if any enabled interrupt is indicated

36

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ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

Register Maps (continued)

Table 6. Serial Control Bus Registers (continued)

REGIST

ER

TYPE

ADD

(dec)

ADD

(hex)

REGISTER

NAME

DEFAULT

(hex)

BIT(S)

FUNCTION

DESCRIPTION

240

241

242

243

244

245

0xF0 TX ID

0xF1

7:0

R

0x5F

0x55

0x48

0x39

0x32

0x35

ID0

ID1

ID2

ID3

ID4

ID5

First byte ID code, ‘_’

Second byte of ID code, ‘U’

Third byte of ID code. Value will be ‘B’

Forth byte of ID code: ‘9’

0xF2

0xF3

0xF4

Fifth byte of ID code: “2”

0xF5

Sixth byte of ID code: “5”

37

DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

www.ti.com.cn

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90UB925Q-Q1, in conjunction with the DS90UB926Q-Q1, is intended for interface between a host

(graphics processor) and a Display. It supports a 24-bit color depth (RGB888) and high definition (720p) digital

video format. It can receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three control

bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.

8.2 Typical Application

DS90UB925Q-Q1

3.3V/1.8V

3.3V

VDDIO

VDD33

CAPP12

CAPL12

FB1

C5

FB2

C4

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

C6

C7

C9

C8

CAPHS12

DIN8

DIN9

DIN10

DIN11

DIN12

DIN13

DIN14

DIN15

C1

Serial

FPD-Link III

Interface

DOUT+

DOUT-

CMF

LVCMOS

Parallel

Video

C2

Interface

C3

DIN16

DIN17

DIN18

DIN19

DIN20

DIN21

DIN22

DIN23

VDD33

R

3

MODE_SEL

R

4

PCLK

HS

VS

DE

VDD33

VDDIO VDD33*

NOTE:

FB1-FB2: Impedance = 1 k: @ 100 MHz,

Low DC resistance (<1:)

C1-C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)

C4-C9 = 4.7 PF

R

1

R

6

R

5

ID[X]

SCL

SDA

LVCMOS

Control

Interface

INTB

PDB

R

2

C10 =>10 PF

C10

R and R (see IDx Resistor Values Table 5)

1

2

NC

R and R (see MODE_SEL Resistor Values Table 1)

I2S_CLK

I2S_WC

I2S_DA

3

5

6

4

RES

DAP (GND)

R

= 10 k:

= 4.7 k:

* or VDDIO = 3.3V+0.3V

Figure 23. Typical Connection Diagram

38

DS90UB925Q-Q1

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ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

Typical Application (continued)

V

DDIO

DD33

DDIO

(1.8Vor3.3V)

DD33

(3.3V) (1.8Vor3.3V)

(3.3V)

R[7:0]

G[7:0]

R[7:0]

G[7:0]

FPD-Link III

1 Pair / AC Coupled

B[7:0]

HS

VS

DE

PCLK

0.1 PF

HOST

Graphics

Processor

RGB Display

720p

24-bit color depth

HS

DOUT+

DOUT-

RIN+

RIN-

VS

DE

PCLK

100: STP Cable

DS90UB925Q-Q1

Serializer

DS90UB926Q-Q1

Deserializer

LOCK

PASS

PDB

OSS_SEL

OEN

PDB

3

I2S AUDIO

(STEREO)

3

I2S AUDIO

(STEREO)

MODE_SEL

INTB

INTB_IN

MCLK

SCL

SDA

IDx

SCL

SDA

IDx

DAP

Figure 24. Typical Display System Diagram

V

DDIO

(1.8V or 3.3V)

DD33

(3.3V) (1.8V or 3.3V)

(3.3V)

FPD-Link III

1 Pair/AC Coupled

D[0:n]

HS

VS

720p

Megapixel

Image

ROUT[0:n]

0.1 PF

Image

Processor

Unit

HS

VS

PCLK

RIN+

RIN-

DOUT+

DOUT-

PCLK

Sensor

100: STP Cable

GPIO

DS90UB925Q-Q1

Serializer

DS90UB926Q-Q1

Deserializer

GPIO

PDB

OSS_SEL

OEN

LOCK

PASS

MODE_SEL

INTB_IN

MODE_SEL

INTB

PDB

SCL

SDA

IDx

SCL

SDA

IDx

DAP

Figure 25. Typical Camera Applications Diagram

8.2.1 Design Requirements

For the typical design application, use the following as input parameters.

Table 7. Design Parameters

DESIGN PARAMETER

VDDIO

EXAMPLE VALUE

1.8 V or 3.3 V

3.3 V

VDD33

AC Coupling Capacitor for DOUT±

PCLK Frequency

100 nF

85 MHz

39

DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

www.ti.com.cn

8.2.2 Detailed Design Procedure

Figure 23 shows a typical application of the DS90UB925Q-Q1 serializer for an 85 MHz 24-bit Color Display

Application. The camera application has the same recommended connections. The CML outputs must have an

external 0.1 μF AC coupling capacitor on the high speed serial lines. The serializer has an internal termination.

Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors and two (2)

additional 1μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2)

VDDs (V_DD33and V_DDIO) for effective noise suppression. The interface to the graphics source is with 3.3V

LVCMOS levels, thus the V_DDIOpin is connected to the 3.3 V rail. A RC delay is placed on the PDB signal to

delay the enabling of the device until power is stable.

8.2.3 Application Curves

Time (100 ps/DIV)

Time (2.5 ns/DIV)

Figure 26. Serializer Eye Diagram with 78 MHz TX Pixel

Clock

Figure 27. Serializer CML Output with 78 MHz TX Pixel

Clock

40

DS90UB925Q-Q1

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ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

9 Power Supply Recommendations

9.1 Power Up Requirements and PDB Pin

The VDDs (V_DD33and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor

on the PDB pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating

voltage. When PDB pin is pulled to V_DDIO= 3.0V to 3.6V or V_DD33, it is recommended to use a 10 kΩ pull-up and

a >10 uF cap to GND to delay the PDB input signal.

All inputs must not be driven until V_DD33and V_DDIOhas reached its steady state value.

This device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separate

power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects

between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal

description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs.

In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.

9.2 CML Interconnect Guidelines

See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.

•

Use 100Ω coupled differential pairs

Use the S/2S/3S rule in spacings

–

– S = space between the pair

– 2S = space between pairs

– 3S = space to LVCMOS signal

•

Minimize the number of Vias

Use differential connectors when operating above 500 Mbps line speed

Maintain balance of the traces

Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas

Instruments web site at: www.ti.com/lvds.

41

DS90UB925Q-Q1

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www.ti.com.cn

10 Layout

10.1 Layout Guidelines

Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power

feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to

minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly

improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane

capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at

high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass

capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the

range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the

tantalum capacitors should be at least 5X the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per

supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power

entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is

recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors

connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external

bypass capacitor will increase the inductance of the path.

A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body

size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of

these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple

capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At

high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing

the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate

switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not

required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power

pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as

PLLs.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML

lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ohms

are typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will

appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.

Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).

42

DS90UB925Q-Q1

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ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

10.2 Layout Example

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste

deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve

board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow

unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:

Figure 28. No Pullback WQFN, Single Row Reference Diagram

Table 8. No Pullback WQFN Stencil Aperture Summary

DEVICE

COUN

T

MKT Dwg PCB I/O

PCB

PCB DAP

SIZE (mm)

STENCIL I/O

APERTURE

(mm)

STENCIL

DAP

Aperture

(mm)

NUMBER of

DAP

APERTURE

OPENINGS

GAP BETWEEN

DAP APERTURE

(Dim A mm)

Pad Size PITCH

(mm)

DS90UB925

Q-Q1

0.25 x

0.6

48

SQA48A

0.5

5.1 x 5.1

0.25 x 0.7

1.1 x 1.1

16

0.2

Figure 29. 48-Pin WQFN Stencil Example of Via and Opening Placement

Figure 30 PCB layout example is derived from the layout design of the DS90UB925QSEVB Evaluation Board.

The graphic and layout description are used to determine both proper routing and proper solder techniques when

designing the Serializer board.

43

DS90UB925Q-Q1

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

www.ti.com.cn

Figure 30. DS90UB925Q-Q1 Serializer Example Layout

44

DS90UB925Q-Q1

www.ti.com.cn

ZHCSCX8D –APRIL 2012–REVISED OCTOBER 2014

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档ꢀ

•

《AN-2198 探究内部测试模式生成》，SNLA132

《AN-1108 通道链路 PCB 和互连设计指南》，SNLA008

《SCAN18245T 具有三态输出的同向收发器》，SNLA035

TI 接口网站 www.ti.com/lvds

《AN-1187 无引线框架封装 (LLP)》，SNOA401

《半导体和 IC 封装热指标》，SPRA953

11.2 商标

All trademarks are the property of their respective owners.

11.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

12 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

45

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产品型号DS90UB925QSQ/NOPB的概述

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